disp/dpu1/dpu_encoder_phys.h

26  * enum dpu_enc_split_role - Role this physical encoder will play in a
29  * @ENC_ROLE_SOLO:	This is the one and only panel. This encoder is master.
30  * @ENC_ROLE_MASTER:	This encoder is the master of a split panel config.
31  * @ENC_ROLE_SLAVE:	This encoder is not the master of a split panel config.
40  * enum dpu_enc_enable_state - current enabled state of the physical encoder
41  * @DPU_ENC_DISABLING:	Encoder transitioning to disable state
42  *			Events bounding transition are encoder type specific
43  * @DPU_ENC_DISABLED:	Encoder is disabled
44  * @DPU_ENC_ENABLING:	Encoder transitioning to enabled
45  *			Events bounding transition are encoder type specific
46  * @DPU_ENC_ENABLED:	Encoder is enabled
47  * @DPU_ENC_ERR_NEEDS_HW_RESET:	Encoder is enabled, but requires a hw_reset
61  * struct dpu_encoder_virt_ops - Interface the containing virtual encoder
63  * @handle_vblank_virt:	Notify virtual encoder of vblank IRQ reception
65  * @handle_underrun_virt: Notify virtual encoder of underrun IRQ reception
67  * @handle_frame_done:	Notify virtual encoder that this phys encoder
81  *	the containing virtual encoder.
85  *				encoder. Can be switched at enable time. Based
104  *				For CMD encoder, may wait for previous tx done
106  * @trigger_start:		Process start event on physical encoder
107  * @needs_single_flush:		Whether encoder slaves need to be flushed
108  * @irq_control:		Handler to enable/disable all the encoder IRQs
109  * @prepare_idle_pc:		phys encoder can update the vsync_enable status
111  * @restore:			Restore all the encoder configs.
116 	int (*late_register)(struct dpu_encoder_phys *encoder,
118 	void (*prepare_commit)(struct dpu_encoder_phys *encoder);
119 	bool (*is_master)(struct dpu_encoder_phys *encoder);
120 	bool (*mode_fixup)(struct dpu_encoder_phys *encoder,
123 	void (*mode_set)(struct dpu_encoder_phys *encoder,
126 	void (*enable)(struct dpu_encoder_phys *encoder);
127 	void (*disable)(struct dpu_encoder_phys *encoder);
128 	int (*atomic_check)(struct dpu_encoder_phys *encoder,
131 	void (*destroy)(struct dpu_encoder_phys *encoder);
132 	void (*get_hw_resources)(struct dpu_encoder_phys *encoder,
149  * enum dpu_intr_idx - dpu encoder interrupt index
167  * @intr_type:		Encoder interrupt type
168  * @intr_idx:		Encoder interrupt enumeration
184  * struct dpu_encoder_phys - physical encoder that drives a single INTF block
187  * @parent:		Pointer to the containing virtual encoder
189  * @ops:		Operations exposed to the virtual encoder
197  * @enabled:		Whether the encoder has enabled and running a mode
201  * @enc_spinlock:	Virtual-Encoder-Wide Spin Lock for IRQ purposes
204  * @vsync_cnt:		Vsync count for the physical encoder
205  * @underrun_cnt:	Underrun count for the physical encoder
249  * @base:	Baseclass physical encoder structure
250  * @intf_idx:	Intf Block index used by this phys encoder
270  * @parent:		Pointer to the containing virtual encoder
274  * @enc_spinlock:	Virtual-Encoder-Wide Spin Lock for IRQ purposes
298  * dpu_encoder_phys_vid_init - Construct a new video mode physical encoder
300  * Return: Error code or newly allocated encoder
306  * dpu_encoder_phys_cmd_init - Construct a new command mode physical encoder
308  * Return: Error code or newly allocated encoder
317  * @phys_enc: Pointer to physical encoder structure
342  * @phys_enc: Pointer to physical encoder structure
352  * @phys_enc: Pointer to physical encoder structure
361  * @phys_enc: Pointer to physical encoder structure
362  * @intr_idx: encoder interrupt index
372  * @phys_enc: Pointer to physical encoder structure
373  * @intr_idx: encoder interrupt index
381  * @phys_enc: Pointer to physical encoder structure
382  * @intr_idx: encoder interrupt index