51 enum vgt_event_type {
100 enum pc_di_primtype {
149 enum pc_di_src_sel {
156 enum pc_di_face_cull_sel {
163 enum pc_di_index_size {
171 enum pc_di_vis_cull_mode {
176 enum adreno_pm4_packet_type {
185 enum adreno_pm4_type3_packets {
304 enum adreno_state_block {
315 enum adreno_state_type {
320 enum adreno_state_src {
329 enum a4xx_state_block {
346 enum a4xx_state_type {
352 enum a4xx_state_src {
357 enum a6xx_state_block {
374 enum a6xx_state_type {
381 enum a6xx_state_src {
388 enum a4xx_index_size {
394 enum a6xx_patch_type {
400 enum a6xx_draw_indirect_opcode {
405 enum cp_cond_function {
415 enum render_mode_cmd {
424 enum cp_blit_cmd {
430 enum a6xx_render_mode {
445 enum pseudo_reg {
453 enum compare_mode {
459 enum ctxswitch_ib {
466 enum reg_tracker {
481 static inline uint32_t CP_LOAD_STATE_0_STATE_SRC(enum adreno_state_src val)  in CP_LOAD_STATE_0_STATE_SRC()
487 static inline uint32_t CP_LOAD_STATE_0_STATE_BLOCK(enum adreno_state_block val)  in CP_LOAD_STATE_0_STATE_BLOCK()
501 static inline uint32_t CP_LOAD_STATE_1_STATE_TYPE(enum adreno_state_type val)  in CP_LOAD_STATE_1_STATE_TYPE()
521 static inline uint32_t CP_LOAD_STATE4_0_STATE_SRC(enum a4xx_state_src val)  in CP_LOAD_STATE4_0_STATE_SRC()
527 static inline uint32_t CP_LOAD_STATE4_0_STATE_BLOCK(enum a4xx_state_block val)  in CP_LOAD_STATE4_0_STATE_BLOCK()
541 static inline uint32_t CP_LOAD_STATE4_1_STATE_TYPE(enum a4xx_state_type val)  in CP_LOAD_STATE4_1_STATE_TYPE()
569 static inline uint32_t CP_LOAD_STATE6_0_STATE_TYPE(enum a6xx_state_type val)  in CP_LOAD_STATE6_0_STATE_TYPE()
575 static inline uint32_t CP_LOAD_STATE6_0_STATE_SRC(enum a6xx_state_src val)  in CP_LOAD_STATE6_0_STATE_SRC()
581 static inline uint32_t CP_LOAD_STATE6_0_STATE_BLOCK(enum a6xx_state_block val)  in CP_LOAD_STATE6_0_STATE_BLOCK()
621 static inline uint32_t CP_DRAW_INDX_1_PRIM_TYPE(enum pc_di_primtype val)  in CP_DRAW_INDX_1_PRIM_TYPE()
627 static inline uint32_t CP_DRAW_INDX_1_SOURCE_SELECT(enum pc_di_src_sel val)  in CP_DRAW_INDX_1_SOURCE_SELECT()
633 static inline uint32_t CP_DRAW_INDX_1_VIS_CULL(enum pc_di_vis_cull_mode val)  in CP_DRAW_INDX_1_VIS_CULL()
639 static inline uint32_t CP_DRAW_INDX_1_INDEX_SIZE(enum pc_di_index_size val)  in CP_DRAW_INDX_1_INDEX_SIZE()
688 static inline uint32_t CP_DRAW_INDX_2_1_PRIM_TYPE(enum pc_di_primtype val)  in CP_DRAW_INDX_2_1_PRIM_TYPE()
694 static inline uint32_t CP_DRAW_INDX_2_1_SOURCE_SELECT(enum pc_di_src_sel val)  in CP_DRAW_INDX_2_1_SOURCE_SELECT()
700 static inline uint32_t CP_DRAW_INDX_2_1_VIS_CULL(enum pc_di_vis_cull_mode val)  in CP_DRAW_INDX_2_1_VIS_CULL()
706 static inline uint32_t CP_DRAW_INDX_2_1_INDEX_SIZE(enum pc_di_index_size val)  in CP_DRAW_INDX_2_1_INDEX_SIZE()
731 static inline uint32_t CP_DRAW_INDX_OFFSET_0_PRIM_TYPE(enum pc_di_primtype val)  in CP_DRAW_INDX_OFFSET_0_PRIM_TYPE()
737 static inline uint32_t CP_DRAW_INDX_OFFSET_0_SOURCE_SELECT(enum pc_di_src_sel val)  in CP_DRAW_INDX_OFFSET_0_SOURCE_SELECT()
743 static inline uint32_t CP_DRAW_INDX_OFFSET_0_VIS_CULL(enum pc_di_vis_cull_mode val)  in CP_DRAW_INDX_OFFSET_0_VIS_CULL()
749 static inline uint32_t CP_DRAW_INDX_OFFSET_0_INDEX_SIZE(enum a4xx_index_size val)  in CP_DRAW_INDX_OFFSET_0_INDEX_SIZE()
755 static inline uint32_t CP_DRAW_INDX_OFFSET_0_PATCH_TYPE(enum a6xx_patch_type val)  in CP_DRAW_INDX_OFFSET_0_PATCH_TYPE()
832 static inline uint32_t A4XX_CP_DRAW_INDIRECT_0_PRIM_TYPE(enum pc_di_primtype val)  in A4XX_CP_DRAW_INDIRECT_0_PRIM_TYPE()
838 static inline uint32_t A4XX_CP_DRAW_INDIRECT_0_SOURCE_SELECT(enum pc_di_src_sel val)  in A4XX_CP_DRAW_INDIRECT_0_SOURCE_SELECT()
844 static inline uint32_t A4XX_CP_DRAW_INDIRECT_0_VIS_CULL(enum pc_di_vis_cull_mode val)  in A4XX_CP_DRAW_INDIRECT_0_VIS_CULL()
850 static inline uint32_t A4XX_CP_DRAW_INDIRECT_0_INDEX_SIZE(enum a4xx_index_size val)  in A4XX_CP_DRAW_INDIRECT_0_INDEX_SIZE()
856 static inline uint32_t A4XX_CP_DRAW_INDIRECT_0_PATCH_TYPE(enum a6xx_patch_type val)  in A4XX_CP_DRAW_INDIRECT_0_PATCH_TYPE()
894 static inline uint32_t A4XX_CP_DRAW_INDX_INDIRECT_0_PRIM_TYPE(enum pc_di_primtype val)  in A4XX_CP_DRAW_INDX_INDIRECT_0_PRIM_TYPE()
900 static inline uint32_t A4XX_CP_DRAW_INDX_INDIRECT_0_SOURCE_SELECT(enum pc_di_src_sel val)  in A4XX_CP_DRAW_INDX_INDIRECT_0_SOURCE_SELECT()
906 static inline uint32_t A4XX_CP_DRAW_INDX_INDIRECT_0_VIS_CULL(enum pc_di_vis_cull_mode val)  in A4XX_CP_DRAW_INDX_INDIRECT_0_VIS_CULL()
912 static inline uint32_t A4XX_CP_DRAW_INDX_INDIRECT_0_INDEX_SIZE(enum a4xx_index_size val)  in A4XX_CP_DRAW_INDX_INDIRECT_0_INDEX_SIZE()
918 static inline uint32_t A4XX_CP_DRAW_INDX_INDIRECT_0_PATCH_TYPE(enum a6xx_patch_type val)  in A4XX_CP_DRAW_INDX_INDIRECT_0_PATCH_TYPE()
998 static inline uint32_t A6XX_CP_DRAW_INDIRECT_MULTI_0_PRIM_TYPE(enum pc_di_primtype val)  in A6XX_CP_DRAW_INDIRECT_MULTI_0_PRIM_TYPE()
1004 static inline uint32_t A6XX_CP_DRAW_INDIRECT_MULTI_0_SOURCE_SELECT(enum pc_di_src_sel val)  in A6XX_CP_DRAW_INDIRECT_MULTI_0_SOURCE_SELECT()
1010 static inline uint32_t A6XX_CP_DRAW_INDIRECT_MULTI_0_VIS_CULL(enum pc_di_vis_cull_mode val)  in A6XX_CP_DRAW_INDIRECT_MULTI_0_VIS_CULL()
1016 static inline uint32_t A6XX_CP_DRAW_INDIRECT_MULTI_0_INDEX_SIZE(enum a4xx_index_size val)  in A6XX_CP_DRAW_INDIRECT_MULTI_0_INDEX_SIZE()
1022 static inline uint32_t A6XX_CP_DRAW_INDIRECT_MULTI_0_PATCH_TYPE(enum a6xx_patch_type val)  in A6XX_CP_DRAW_INDIRECT_MULTI_0_PATCH_TYPE()
1032 static inline uint32_t A6XX_CP_DRAW_INDIRECT_MULTI_1_OPCODE(enum a6xx_draw_indirect_opcode val)  in A6XX_CP_DRAW_INDIRECT_MULTI_1_OPCODE()
1558 static inline uint32_t CP_COND_WRITE_0_FUNCTION(enum cp_cond_function val)  in CP_COND_WRITE_0_FUNCTION()
1608 static inline uint32_t CP_COND_WRITE5_0_FUNCTION(enum cp_cond_function val)  in CP_COND_WRITE5_0_FUNCTION()
1708 static inline uint32_t CP_WAIT_REG_MEM_0_FUNCTION(enum cp_cond_function val)  in CP_WAIT_REG_MEM_0_FUNCTION()
1810 static inline uint32_t CP_SET_RENDER_MODE_0_MODE(enum render_mode_cmd val)  in CP_SET_RENDER_MODE_0_MODE()
1928 static inline uint32_t CP_EVENT_WRITE_0_EVENT(enum vgt_event_type val)  in CP_EVENT_WRITE_0_EVENT()
1956 static inline uint32_t CP_BLIT_0_OP(enum cp_blit_cmd val)  in CP_BLIT_0_OP()
2114 static inline uint32_t A6XX_CP_SET_MARKER_0_MODE(enum a6xx_render_mode val)  in A6XX_CP_SET_MARKER_0_MODE()
2120 static inline uint32_t A6XX_CP_SET_MARKER_0_MARKER(enum a6xx_render_mode val)  in A6XX_CP_SET_MARKER_0_MARKER()
2130 static inline uint32_t A6XX_CP_SET_PSEUDO_REG__0_PSEUDO_REG(enum pseudo_reg val)  in A6XX_CP_SET_PSEUDO_REG__0_PSEUDO_REG()
2178 static inline uint32_t CP_COND_REG_EXEC_0_MODE(enum compare_mode val)  in CP_COND_REG_EXEC_0_MODE()
2264 static inline uint32_t CP_SET_CTXSWITCH_IB_2_TYPE(enum ctxswitch_ib val)  in CP_SET_CTXSWITCH_IB_2_TYPE()
2272 static inline uint32_t CP_REG_WRITE_0_TRACKER(enum reg_tracker val)  in CP_REG_WRITE_0_TRACKER()