Lines Matching +full:0 +full:x2000
50 in[0] = val; in CRASHDUMP_WRITE()
58 in[0] = target; in CRASHDUMP_READ()
66 in[0] = 0; in CRASHDUMP_FINI()
67 in[1] = 0; in CRASHDUMP_FINI()
148 val & 0x02, 100, 10000); in a6xx_crashdumper_run()
150 gpu_write(gpu, REG_A6XX_CP_CRASH_DUMP_CNTL, 0); in a6xx_crashdumper_run()
170 data[0] = gpu_read(gpu, REG_A6XX_DBGC_CFG_DBGBUS_TRACE_BUF2); in debugbus_read()
197 data[0] = cxdbg_read(cxdbg, REG_A6XX_CX_DBGC_CFG_DBGBUS_TRACE_BUF2); in cx_debugbus_read()
211 for (i = 0; i < count; i++) { in vbif_debugbus_read()
250 gpu_write(gpu, REG_A6XX_VBIF_TEST_BUS1_CTRL0, 0); in a6xx_get_vbif_debugbus_block()
257 for (i = 0; i < AXI_ARB_BLOCKS; i++) in a6xx_get_vbif_debugbus_block()
263 for (i = 0; i < XIN_AXI_BLOCKS; i++) in a6xx_get_vbif_debugbus_block()
270 gpu_write(gpu, REG_A6XX_VBIF_TEST_BUS2_CTRL0, 0); in a6xx_get_vbif_debugbus_block()
272 for (i = 0; i < XIN_CORE_BLOCKS; i++) in a6xx_get_vbif_debugbus_block()
296 for (ptr = obj->data, i = 0; i < block->count; i++) in a6xx_get_debugbus_block()
314 for (ptr = obj->data, i = 0; i < block->count; i++) in a6xx_get_cx_debugbus_block()
328 A6XX_DBGC_CFG_DBGBUS_CNTLT_SEGT(0xf)); in a6xx_get_debugbus()
331 A6XX_DBGC_CFG_DBGBUS_CNTLM_ENABLE(0xf)); in a6xx_get_debugbus()
333 gpu_write(gpu, REG_A6XX_DBGC_CFG_DBGBUS_IVTL_0, 0); in a6xx_get_debugbus()
334 gpu_write(gpu, REG_A6XX_DBGC_CFG_DBGBUS_IVTL_1, 0); in a6xx_get_debugbus()
335 gpu_write(gpu, REG_A6XX_DBGC_CFG_DBGBUS_IVTL_2, 0); in a6xx_get_debugbus()
336 gpu_write(gpu, REG_A6XX_DBGC_CFG_DBGBUS_IVTL_3, 0); in a6xx_get_debugbus()
338 gpu_write(gpu, REG_A6XX_DBGC_CFG_DBGBUS_BYTEL_0, 0x76543210); in a6xx_get_debugbus()
339 gpu_write(gpu, REG_A6XX_DBGC_CFG_DBGBUS_BYTEL_1, 0xFEDCBA98); in a6xx_get_debugbus()
341 gpu_write(gpu, REG_A6XX_DBGC_CFG_DBGBUS_MASKL_0, 0); in a6xx_get_debugbus()
342 gpu_write(gpu, REG_A6XX_DBGC_CFG_DBGBUS_MASKL_1, 0); in a6xx_get_debugbus()
343 gpu_write(gpu, REG_A6XX_DBGC_CFG_DBGBUS_MASKL_2, 0); in a6xx_get_debugbus()
344 gpu_write(gpu, REG_A6XX_DBGC_CFG_DBGBUS_MASKL_3, 0); in a6xx_get_debugbus()
357 A6XX_DBGC_CFG_DBGBUS_CNTLT_SEGT(0xf)); in a6xx_get_debugbus()
360 A6XX_DBGC_CFG_DBGBUS_CNTLM_ENABLE(0xf)); in a6xx_get_debugbus()
362 cxdbg_write(cxdbg, REG_A6XX_CX_DBGC_CFG_DBGBUS_IVTL_0, 0); in a6xx_get_debugbus()
363 cxdbg_write(cxdbg, REG_A6XX_CX_DBGC_CFG_DBGBUS_IVTL_1, 0); in a6xx_get_debugbus()
364 cxdbg_write(cxdbg, REG_A6XX_CX_DBGC_CFG_DBGBUS_IVTL_2, 0); in a6xx_get_debugbus()
365 cxdbg_write(cxdbg, REG_A6XX_CX_DBGC_CFG_DBGBUS_IVTL_3, 0); in a6xx_get_debugbus()
368 0x76543210); in a6xx_get_debugbus()
370 0xFEDCBA98); in a6xx_get_debugbus()
372 cxdbg_write(cxdbg, REG_A6XX_CX_DBGC_CFG_DBGBUS_MASKL_0, 0); in a6xx_get_debugbus()
373 cxdbg_write(cxdbg, REG_A6XX_CX_DBGC_CFG_DBGBUS_MASKL_1, 0); in a6xx_get_debugbus()
374 cxdbg_write(cxdbg, REG_A6XX_CX_DBGC_CFG_DBGBUS_MASKL_2, 0); in a6xx_get_debugbus()
375 cxdbg_write(cxdbg, REG_A6XX_CX_DBGC_CFG_DBGBUS_MASKL_3, 0); in a6xx_get_debugbus()
379 (a6xx_has_gbif(to_adreno_gpu(gpu)) ? 1 : 0); in a6xx_get_debugbus()
387 for (i = 0; i < ARRAY_SIZE(a6xx_debugbus_blocks); i++) in a6xx_get_debugbus()
429 for (i = 0; i < ARRAY_SIZE(a6xx_cx_debugbus_blocks); i++) in a6xx_get_debugbus()
455 int i, regcount = 0; in a6xx_get_dbgahb_cluster()
457 for (i = 0; i < A6XX_NUM_CONTEXTS; i++) { in a6xx_get_dbgahb_cluster()
463 for (j = 0; j < dbgahb->count; j += 2) { in a6xx_get_dbgahb_cluster()
472 if (i == 0) in a6xx_get_dbgahb_cluster()
507 for (i = 0; i < ARRAY_SIZE(a6xx_dbgahb_clusters); i++) in a6xx_get_dbgahb_clusters()
523 int i, regcount = 0; in a6xx_get_cluster()
529 for (i = 0; i < A6XX_NUM_CONTEXTS; i++) { in a6xx_get_cluster()
535 for (j = 0; j < cluster->count; j += 2) { in a6xx_get_cluster()
543 if (i == 0) in a6xx_get_cluster()
577 for (i = 0; i < ARRAY_SIZE(a6xx_clusters); i++) in a6xx_get_clusters()
596 for (i = 0; i < A6XX_NUM_SHADER_BANKS; i++) { in a6xx_get_shader_block()
628 for (i = 0; i < ARRAY_SIZE(a6xx_shader_blocks); i++) in a6xx_get_shaders()
643 int i, regcount = 0; in a6xx_get_crashdumper_hlsq_registers()
647 for (i = 0; i < regs->count; i += 2) { in a6xx_get_crashdumper_hlsq_registers()
681 int i, regcount = 0; in a6xx_get_crashdumper_registers()
687 for (i = 0; i < regs->count; i += 2) { in a6xx_get_crashdumper_registers()
715 int i, regcount = 0, index = 0; in a6xx_get_ahb_gpu_registers()
717 for (i = 0; i < regs->count; i += 2) in a6xx_get_ahb_gpu_registers()
725 for (i = 0; i < regs->count; i += 2) { in a6xx_get_ahb_gpu_registers()
729 for (j = 0; j < count; j++) in a6xx_get_ahb_gpu_registers()
745 int i, regcount = 0, index = 0; in _a6xx_get_gmu_registers()
747 for (i = 0; i < regs->count; i += 2) in _a6xx_get_gmu_registers()
755 for (i = 0; i < regs->count; i += 2) { in _a6xx_get_gmu_registers()
759 for (j = 0; j < count; j++) { in _a6xx_get_gmu_registers()
788 _a6xx_get_gmu_registers(gpu, a6xx_state, &a6xx_gmu_reglist[0], in a6xx_get_gmu_registers()
789 &a6xx_state->gmu_registers[0], false); in a6xx_get_gmu_registers()
797 gpu_write(gpu, REG_A6XX_GMU_AO_AHB_FENCE_CTRL, 0); in a6xx_get_gmu_registers()
811 int index = 0; in a6xx_get_registers()
822 for (i = 0; i < ARRAY_SIZE(a6xx_ahb_reglist); i++) in a6xx_get_registers()
836 for (i = 0; i < ARRAY_SIZE(a6xx_reglist); i++) in a6xx_get_registers()
842 for (i = 0; i < ARRAY_SIZE(a6xx_hlsq_reglist); i++) in a6xx_get_registers()
862 /* All the indexed banks start at address 0 */ in a6xx_get_indexed_regs()
863 gpu_write(gpu, indexed->addr, 0); in a6xx_get_indexed_regs()
866 for (i = 0; i < indexed->count; i++) in a6xx_get_indexed_regs()
882 for (i = 0; i < ARRAY_SIZE(a6xx_indexed_reglist); i++) in a6xx_get_indexed_registers()
886 /* Set the CP mempool size to 0 to stabilize it while dumping */ in a6xx_get_indexed_registers()
888 gpu_write(gpu, REG_A6XX_CP_MEM_POOL_SIZE, 0); in a6xx_get_indexed_registers()
895 * Offset 0x2000 in the mempool is the size - copy the saved size over in a6xx_get_indexed_registers()
898 a6xx_state->indexed_regs[i].data[0x2000] = mempool_size; in a6xx_get_indexed_registers()
908 struct a6xx_crashdumper dumper = { 0 }; in a6xx_gpu_state_get()
973 int i, index = 0; in a6xx_show_registers()
978 for (i = 0; i < count; i += 2) { in a6xx_show_registers()
983 for (j = 0; j < count; index++, offset++, j++) { in a6xx_show_registers()
984 if (data[index] == 0xdeafbead) in a6xx_show_registers()
987 drm_printf(p, " - { offset: 0x%06x, value: 0x%08x }\n", in a6xx_show_registers()
996 long i, l, datalen = 0; in print_ascii85()
998 for (i = 0; i < len >> 2; i++) { in print_ascii85()
1003 if (datalen == 0) in print_ascii85()
1012 for (i = 0; i < l; i++) in print_ascii85()
1036 for (i = 0; i < A6XX_NUM_SHADER_BANKS; i++) { in a6xx_show_shader()
1051 int ctx, index = 0; in a6xx_show_cluster_data()
1053 for (ctx = 0; ctx < A6XX_NUM_CONTEXTS; ctx++) { in a6xx_show_cluster_data()
1058 for (j = 0; j < size; j += 2) { in a6xx_show_cluster_data()
1063 for (k = 0; k < count; index++, offset++, k++) { in a6xx_show_cluster_data()
1064 if (data[index] == 0xdeafbead) in a6xx_show_cluster_data()
1067 drm_printf(p, " - { offset: 0x%06x, value: 0x%08x }\n", in a6xx_show_cluster_data()
1133 for (i = 0; i < a6xx_state->nr_debugbus; i++) { in a6xx_show_debugbus()
1149 for (i = 0; i < a6xx_state->nr_cx_debugbus; i++) { in a6xx_show_debugbus()
1169 for (i = 0; i < a6xx_state->nr_registers; i++) { in a6xx_show()
1180 for (i = 0; i < a6xx_state->nr_gmu_registers; i++) { in a6xx_show()
1191 for (i = 0; i < a6xx_state->nr_indexed_regs; i++) in a6xx_show()
1195 for (i = 0; i < a6xx_state->nr_shaders; i++) in a6xx_show()
1199 for (i = 0; i < a6xx_state->nr_clusters; i++) in a6xx_show()
1202 for (i = 0; i < a6xx_state->nr_dbgahb_clusters; i++) in a6xx_show()