20 	/* Check that the GMU is idle */  in _a6xx_check_idle()
21 	if (!a6xx_gmu_isidle(&a6xx_gpu->gmu))  in _a6xx_check_idle()
153 	 * For PM4 the GMU register offsets are calculated from the base of the  in a6xx_submit()
206 		gmu_read64(&a6xx_gpu->gmu, REG_A6XX_GMU_ALWAYS_ON_COUNTER_L,  in a6xx_submit()
431 	struct a6xx_gmu *gmu = &a6xx_gpu->gmu;  in a6xx_set_hwcg()  local
451 	gmu_rmw(gmu, REG_A6XX_GPU_GMU_GX_SPTPRAC_CLOCK_CONTROL, 1, 0);  in a6xx_set_hwcg()
457 	gmu_rmw(gmu, REG_A6XX_GPU_GMU_GX_SPTPRAC_CLOCK_CONTROL, 0, 1);  in a6xx_set_hwcg()
607 	/* Make sure the GMU keeps the GPU on while we set it up */  in a6xx_hw_init()
608 	a6xx_gmu_set_oob(&a6xx_gpu->gmu, GMU_OOB_GPU_SET);  in a6xx_hw_init()
858 	 * Tell the GMU that we are done touching the GPU and it can start power  in a6xx_hw_init()
861 	a6xx_gmu_clear_oob(&a6xx_gpu->gmu, GMU_OOB_GPU_SET);  in a6xx_hw_init()
863 	if (a6xx_gpu->gmu.legacy) {  in a6xx_hw_init()
864 		/* Take the GMU out of its special boot mode */  in a6xx_hw_init()
865 		a6xx_gmu_clear_oob(&a6xx_gpu->gmu, GMU_OOB_BOOT_SLUMBER);  in a6xx_hw_init()
900 	gmu_write(&a6xx_gpu->gmu, REG_A6XX_GMU_GMU_PWR_COL_KEEPALIVE, 0);  in a6xx_recover()
976 	gmu_write(&a6xx_gpu->gmu, REG_A6XX_GMU_GMU_PWR_COL_KEEPALIVE, 1);  in a6xx_fault_detect_irq()
1062 	a6xx_gmu_set_oob(&a6xx_gpu->gmu, GMU_OOB_GPU_SET);  in a6xx_get_timestamp()
1067 	a6xx_gmu_clear_oob(&a6xx_gpu->gmu, GMU_OOB_GPU_SET);  in a6xx_get_timestamp()
1108 	if (pm_runtime_get_if_in_use(a6xx_gpu->gmu.dev) == 0)  in a6xx_gpu_busy()
1111 	busy_cycles = gmu_read64(&a6xx_gpu->gmu,  in a6xx_gpu_busy()
1120 	pm_runtime_put(a6xx_gpu->gmu.dev);  in a6xx_gpu_busy()
1218 	/* Check if there is a GMU phandle and set it up */  in a6xx_gpu_init()
1219 	node = of_parse_phandle(pdev->dev.of_node, "qcom,gmu", 0);  in a6xx_gpu_init()