25 static inline void set_preempt_state(struct a5xx_gpu *gpu,  in set_preempt_state()  argument
34 	atomic_set(&gpu->preempt_state, new);  in set_preempt_state()
40 static inline void update_wptr(struct msm_gpu *gpu, struct msm_ringbuffer *ring)  in update_wptr()  argument
52 	gpu_write(gpu, REG_A5XX_CP_RB_WPTR, wptr);  in update_wptr()
56 static struct msm_ringbuffer *get_next_ring(struct msm_gpu *gpu)  in get_next_ring()  argument
61 	for (i = 0; i < gpu->nr_rings; i++) {  in get_next_ring()
63 		struct msm_ringbuffer *ring = gpu->rb[i];  in get_next_ring()
79 	struct msm_gpu *gpu = &a5xx_gpu->base.base;  in a5xx_preempt_timer()  local
80 	struct drm_device *dev = gpu->dev;  in a5xx_preempt_timer()
86 	DRM_DEV_ERROR(dev->dev, "%s: preemption timed out\n", gpu->name);  in a5xx_preempt_timer()
87 	queue_work(priv->wq, &gpu->recover_work);  in a5xx_preempt_timer()
91 void a5xx_preempt_trigger(struct msm_gpu *gpu)  in a5xx_preempt_trigger()  argument
93 	struct adreno_gpu *adreno_gpu = to_adreno_gpu(gpu);  in a5xx_preempt_trigger()
98 	if (gpu->nr_rings == 1)  in a5xx_preempt_trigger()
109 	ring = get_next_ring(gpu);  in a5xx_preempt_trigger()
129 		update_wptr(gpu, a5xx_gpu->cur_ring);  in a5xx_preempt_trigger()
140 	gpu_write64(gpu, REG_A5XX_CP_CONTEXT_SWITCH_RESTORE_ADDR_LO,  in a5xx_preempt_trigger()
156 	gpu_write(gpu, REG_A5XX_CP_CONTEXT_SWITCH_CNTL, 1);  in a5xx_preempt_trigger()
159 void a5xx_preempt_irq(struct msm_gpu *gpu)  in a5xx_preempt_irq()  argument
162 	struct adreno_gpu *adreno_gpu = to_adreno_gpu(gpu);  in a5xx_preempt_irq()
164 	struct drm_device *dev = gpu->dev;  in a5xx_preempt_irq()
179 	status = gpu_read(gpu, REG_A5XX_CP_CONTEXT_SWITCH_CNTL);  in a5xx_preempt_irq()
183 			gpu->name);  in a5xx_preempt_irq()
184 		queue_work(priv->wq, &gpu->recover_work);  in a5xx_preempt_irq()
191 	update_wptr(gpu, a5xx_gpu->cur_ring);  in a5xx_preempt_irq()
196 void a5xx_preempt_hw_init(struct msm_gpu *gpu)  in a5xx_preempt_hw_init()  argument
198 	struct adreno_gpu *adreno_gpu = to_adreno_gpu(gpu);  in a5xx_preempt_hw_init()
203 	a5xx_gpu->cur_ring = gpu->rb[0];  in a5xx_preempt_hw_init()
206 	if (gpu->nr_rings == 1)  in a5xx_preempt_hw_init()
209 	for (i = 0; i < gpu->nr_rings; i++) {  in a5xx_preempt_hw_init()
212 		a5xx_gpu->preempt[i]->rbase = gpu->rb[i]->iova;  in a5xx_preempt_hw_init()
216 	gpu_write64(gpu, REG_A5XX_CP_CONTEXT_SWITCH_SMMU_INFO_LO,  in a5xx_preempt_hw_init()
227 	struct msm_gpu *gpu = &adreno_gpu->base;  in preempt_init_ring()  local
233 	ptr = msm_gem_kernel_new(gpu->dev,  in preempt_init_ring()
235 		MSM_BO_UNCACHED | MSM_BO_MAP_PRIV, gpu->aspace, &bo, &iova);  in preempt_init_ring()
241 	counters = msm_gem_kernel_new(gpu->dev,  in preempt_init_ring()
243 		MSM_BO_UNCACHED, gpu->aspace, &counters_bo, &counters_iova);  in preempt_init_ring()
245 		msm_gem_kernel_put(bo, gpu->aspace, true);  in preempt_init_ring()
270 void a5xx_preempt_fini(struct msm_gpu *gpu)  in a5xx_preempt_fini()  argument
272 	struct adreno_gpu *adreno_gpu = to_adreno_gpu(gpu);  in a5xx_preempt_fini()
276 	for (i = 0; i < gpu->nr_rings; i++) {  in a5xx_preempt_fini()
277 		msm_gem_kernel_put(a5xx_gpu->preempt_bo[i], gpu->aspace, true);  in a5xx_preempt_fini()
279 			gpu->aspace, true);  in a5xx_preempt_fini()
283 void a5xx_preempt_init(struct msm_gpu *gpu)  in a5xx_preempt_init()  argument
285 	struct adreno_gpu *adreno_gpu = to_adreno_gpu(gpu);  in a5xx_preempt_init()
290 	if (gpu->nr_rings <= 1)  in a5xx_preempt_init()
293 	for (i = 0; i < gpu->nr_rings; i++) {  in a5xx_preempt_init()
294 		if (preempt_init_ring(a5xx_gpu, gpu->rb[i])) {  in a5xx_preempt_init()
299 			a5xx_preempt_fini(gpu);  in a5xx_preempt_init()
300 			gpu->nr_rings = 1;  in a5xx_preempt_init()