Lines Matching +full:0 +full:x00000e0e
100 TILE4_LINEAR = 0,
259 DEPTH4_NONE = 0,
266 CCU_BUSY_CYCLES = 0,
285 CP_ALWAYS_COUNT = 0,
329 RAS_SUPER_TILES = 0,
346 TSE_INPUT_PRIM = 0,
366 HLSQ_SP_VS_STAGE_CONSTANT = 0,
394 PC_VIS_STREAMS_LOADED = 0,
437 PWR_CORE_CLOCK_CYCLES = 0,
442 RB_BUSY_CYCLES = 0,
494 RBBM_ALWAYS_ON = 0,
526 SP_LM_LOAD_INSTRUCTIONS = 0,
587 TP_L1_REQUESTS = 0,
610 UCHE_VBIF_READ_BEATS_TP = 0,
644 AXI_READ_REQUESTS_ID_0 = 0,
759 VFD_UCHE_BYTE_FETCHED = 0,
797 VSC_BUSY_CYCLES = 0,
805 A4XX_TEX_NEAREST = 0,
811 A4XX_TEX_REPEAT = 0,
819 A4XX_TEX_ANISO_1 = 0,
827 A4XX_TEX_X = 0,
836 A4XX_TEX_1D = 0,
842 #define A4XX_CGC_HLSQ_EARLY_CYC__MASK 0x00700000
848 #define A4XX_INT0_RBBM_GPU_IDLE 0x00000001
849 #define A4XX_INT0_RBBM_AHB_ERROR 0x00000002
850 #define A4XX_INT0_RBBM_REG_TIMEOUT 0x00000004
851 #define A4XX_INT0_RBBM_ME_MS_TIMEOUT 0x00000008
852 #define A4XX_INT0_RBBM_PFP_MS_TIMEOUT 0x00000010
853 #define A4XX_INT0_RBBM_ATB_BUS_OVERFLOW 0x00000020
854 #define A4XX_INT0_VFD_ERROR 0x00000040
855 #define A4XX_INT0_CP_SW_INT 0x00000080
856 #define A4XX_INT0_CP_T0_PACKET_IN_IB 0x00000100
857 #define A4XX_INT0_CP_OPCODE_ERROR 0x00000200
858 #define A4XX_INT0_CP_RESERVED_BIT_ERROR 0x00000400
859 #define A4XX_INT0_CP_HW_FAULT 0x00000800
860 #define A4XX_INT0_CP_DMA 0x00001000
861 #define A4XX_INT0_CP_IB2_INT 0x00002000
862 #define A4XX_INT0_CP_IB1_INT 0x00004000
863 #define A4XX_INT0_CP_RB_INT 0x00008000
864 #define A4XX_INT0_CP_REG_PROTECT_FAULT 0x00010000
865 #define A4XX_INT0_CP_RB_DONE_TS 0x00020000
866 #define A4XX_INT0_CP_VS_DONE_TS 0x00040000
867 #define A4XX_INT0_CP_PS_DONE_TS 0x00080000
868 #define A4XX_INT0_CACHE_FLUSH_TS 0x00100000
869 #define A4XX_INT0_CP_AHB_ERROR_HALT 0x00200000
870 #define A4XX_INT0_MISC_HANG_DETECT 0x01000000
871 #define A4XX_INT0_UCHE_OOB_ACCESS 0x02000000
872 #define REG_A4XX_RB_GMEM_BASE_ADDR 0x00000cc0
874 #define REG_A4XX_RB_PERFCTR_RB_SEL_0 0x00000cc7
876 #define REG_A4XX_RB_PERFCTR_RB_SEL_1 0x00000cc8
878 #define REG_A4XX_RB_PERFCTR_RB_SEL_2 0x00000cc9
880 #define REG_A4XX_RB_PERFCTR_RB_SEL_3 0x00000cca
882 #define REG_A4XX_RB_PERFCTR_RB_SEL_4 0x00000ccb
884 #define REG_A4XX_RB_PERFCTR_RB_SEL_5 0x00000ccc
886 #define REG_A4XX_RB_PERFCTR_RB_SEL_6 0x00000ccd
888 #define REG_A4XX_RB_PERFCTR_RB_SEL_7 0x00000cce
890 #define REG_A4XX_RB_PERFCTR_CCU_SEL_0 0x00000ccf
892 #define REG_A4XX_RB_PERFCTR_CCU_SEL_1 0x00000cd0
894 #define REG_A4XX_RB_PERFCTR_CCU_SEL_2 0x00000cd1
896 #define REG_A4XX_RB_PERFCTR_CCU_SEL_3 0x00000cd2
898 #define REG_A4XX_RB_FRAME_BUFFER_DIMENSION 0x00000ce0
899 #define A4XX_RB_FRAME_BUFFER_DIMENSION_WIDTH__MASK 0x00003fff
900 #define A4XX_RB_FRAME_BUFFER_DIMENSION_WIDTH__SHIFT 0
905 #define A4XX_RB_FRAME_BUFFER_DIMENSION_HEIGHT__MASK 0x3fff0000
912 #define REG_A4XX_RB_CLEAR_COLOR_DW0 0x000020cc
914 #define REG_A4XX_RB_CLEAR_COLOR_DW1 0x000020cd
916 #define REG_A4XX_RB_CLEAR_COLOR_DW2 0x000020ce
918 #define REG_A4XX_RB_CLEAR_COLOR_DW3 0x000020cf
920 #define REG_A4XX_RB_MODE_CONTROL 0x000020a0
921 #define A4XX_RB_MODE_CONTROL_WIDTH__MASK 0x0000003f
922 #define A4XX_RB_MODE_CONTROL_WIDTH__SHIFT 0
927 #define A4XX_RB_MODE_CONTROL_HEIGHT__MASK 0x00003f00
933 #define A4XX_RB_MODE_CONTROL_ENABLE_GMEM 0x00010000
935 #define REG_A4XX_RB_RENDER_CONTROL 0x000020a1
936 #define A4XX_RB_RENDER_CONTROL_BINNING_PASS 0x00000001
937 #define A4XX_RB_RENDER_CONTROL_DISABLE_COLOR_PIPE 0x00000020
939 #define REG_A4XX_RB_MSAA_CONTROL 0x000020a2
940 #define A4XX_RB_MSAA_CONTROL_DISABLE 0x00001000
941 #define A4XX_RB_MSAA_CONTROL_SAMPLES__MASK 0x0000e000
948 #define REG_A4XX_RB_RENDER_CONTROL2 0x000020a3
949 #define A4XX_RB_RENDER_CONTROL2_COORD_MASK__MASK 0x0000000f
950 #define A4XX_RB_RENDER_CONTROL2_COORD_MASK__SHIFT 0
955 #define A4XX_RB_RENDER_CONTROL2_SAMPLEMASK 0x00000010
956 #define A4XX_RB_RENDER_CONTROL2_FACENESS 0x00000020
957 #define A4XX_RB_RENDER_CONTROL2_SAMPLEID 0x00000040
958 #define A4XX_RB_RENDER_CONTROL2_MSAA_SAMPLES__MASK 0x00000380
964 #define A4XX_RB_RENDER_CONTROL2_SAMPLEID_HR 0x00000800
965 #define A4XX_RB_RENDER_CONTROL2_IJ_PERSP_PIXEL 0x00001000
966 #define A4XX_RB_RENDER_CONTROL2_IJ_PERSP_CENTROID 0x00002000
967 #define A4XX_RB_RENDER_CONTROL2_IJ_PERSP_SAMPLE 0x00004000
968 #define A4XX_RB_RENDER_CONTROL2_SIZE 0x00008000
970 static inline uint32_t REG_A4XX_RB_MRT(uint32_t i0) { return 0x000020a4 + 0x5*i0; } in REG_A4XX_RB_MRT()
972 static inline uint32_t REG_A4XX_RB_MRT_CONTROL(uint32_t i0) { return 0x000020a4 + 0x5*i0; } in REG_A4XX_RB_MRT_CONTROL()
973 #define A4XX_RB_MRT_CONTROL_READ_DEST_ENABLE 0x00000008
974 #define A4XX_RB_MRT_CONTROL_BLEND 0x00000010
975 #define A4XX_RB_MRT_CONTROL_BLEND2 0x00000020
976 #define A4XX_RB_MRT_CONTROL_ROP_ENABLE 0x00000040
977 #define A4XX_RB_MRT_CONTROL_ROP_CODE__MASK 0x00000f00
983 #define A4XX_RB_MRT_CONTROL_COMPONENT_ENABLE__MASK 0x0f000000
990 static inline uint32_t REG_A4XX_RB_MRT_BUF_INFO(uint32_t i0) { return 0x000020a5 + 0x5*i0; } in REG_A4XX_RB_MRT_BUF_INFO()
991 #define A4XX_RB_MRT_BUF_INFO_COLOR_FORMAT__MASK 0x0000003f
992 #define A4XX_RB_MRT_BUF_INFO_COLOR_FORMAT__SHIFT 0
997 #define A4XX_RB_MRT_BUF_INFO_COLOR_TILE_MODE__MASK 0x000000c0
1003 #define A4XX_RB_MRT_BUF_INFO_DITHER_MODE__MASK 0x00000600
1009 #define A4XX_RB_MRT_BUF_INFO_COLOR_SWAP__MASK 0x00001800
1015 #define A4XX_RB_MRT_BUF_INFO_COLOR_SRGB 0x00002000
1016 #define A4XX_RB_MRT_BUF_INFO_COLOR_BUF_PITCH__MASK 0xffffc000
1023 static inline uint32_t REG_A4XX_RB_MRT_BASE(uint32_t i0) { return 0x000020a6 + 0x5*i0; } in REG_A4XX_RB_MRT_BASE()
1025 static inline uint32_t REG_A4XX_RB_MRT_CONTROL3(uint32_t i0) { return 0x000020a7 + 0x5*i0; } in REG_A4XX_RB_MRT_CONTROL3()
1026 #define A4XX_RB_MRT_CONTROL3_STRIDE__MASK 0x03fffff8
1033 static inline uint32_t REG_A4XX_RB_MRT_BLEND_CONTROL(uint32_t i0) { return 0x000020a8 + 0x5*i0; } in REG_A4XX_RB_MRT_BLEND_CONTROL()
1034 #define A4XX_RB_MRT_BLEND_CONTROL_RGB_SRC_FACTOR__MASK 0x0000001f
1035 #define A4XX_RB_MRT_BLEND_CONTROL_RGB_SRC_FACTOR__SHIFT 0
1040 #define A4XX_RB_MRT_BLEND_CONTROL_RGB_BLEND_OPCODE__MASK 0x000000e0
1046 #define A4XX_RB_MRT_BLEND_CONTROL_RGB_DEST_FACTOR__MASK 0x00001f00
1052 #define A4XX_RB_MRT_BLEND_CONTROL_ALPHA_SRC_FACTOR__MASK 0x001f0000
1058 #define A4XX_RB_MRT_BLEND_CONTROL_ALPHA_BLEND_OPCODE__MASK 0x00e00000
1064 #define A4XX_RB_MRT_BLEND_CONTROL_ALPHA_DEST_FACTOR__MASK 0x1f000000
1071 #define REG_A4XX_RB_BLEND_RED 0x000020f0
1072 #define A4XX_RB_BLEND_RED_UINT__MASK 0x000000ff
1073 #define A4XX_RB_BLEND_RED_UINT__SHIFT 0
1078 #define A4XX_RB_BLEND_RED_SINT__MASK 0x0000ff00
1084 #define A4XX_RB_BLEND_RED_FLOAT__MASK 0xffff0000
1091 #define REG_A4XX_RB_BLEND_RED_F32 0x000020f1
1092 #define A4XX_RB_BLEND_RED_F32__MASK 0xffffffff
1093 #define A4XX_RB_BLEND_RED_F32__SHIFT 0
1099 #define REG_A4XX_RB_BLEND_GREEN 0x000020f2
1100 #define A4XX_RB_BLEND_GREEN_UINT__MASK 0x000000ff
1101 #define A4XX_RB_BLEND_GREEN_UINT__SHIFT 0
1106 #define A4XX_RB_BLEND_GREEN_SINT__MASK 0x0000ff00
1112 #define A4XX_RB_BLEND_GREEN_FLOAT__MASK 0xffff0000
1119 #define REG_A4XX_RB_BLEND_GREEN_F32 0x000020f3
1120 #define A4XX_RB_BLEND_GREEN_F32__MASK 0xffffffff
1121 #define A4XX_RB_BLEND_GREEN_F32__SHIFT 0
1127 #define REG_A4XX_RB_BLEND_BLUE 0x000020f4
1128 #define A4XX_RB_BLEND_BLUE_UINT__MASK 0x000000ff
1129 #define A4XX_RB_BLEND_BLUE_UINT__SHIFT 0
1134 #define A4XX_RB_BLEND_BLUE_SINT__MASK 0x0000ff00
1140 #define A4XX_RB_BLEND_BLUE_FLOAT__MASK 0xffff0000
1147 #define REG_A4XX_RB_BLEND_BLUE_F32 0x000020f5
1148 #define A4XX_RB_BLEND_BLUE_F32__MASK 0xffffffff
1149 #define A4XX_RB_BLEND_BLUE_F32__SHIFT 0
1155 #define REG_A4XX_RB_BLEND_ALPHA 0x000020f6
1156 #define A4XX_RB_BLEND_ALPHA_UINT__MASK 0x000000ff
1157 #define A4XX_RB_BLEND_ALPHA_UINT__SHIFT 0
1162 #define A4XX_RB_BLEND_ALPHA_SINT__MASK 0x0000ff00
1168 #define A4XX_RB_BLEND_ALPHA_FLOAT__MASK 0xffff0000
1175 #define REG_A4XX_RB_BLEND_ALPHA_F32 0x000020f7
1176 #define A4XX_RB_BLEND_ALPHA_F32__MASK 0xffffffff
1177 #define A4XX_RB_BLEND_ALPHA_F32__SHIFT 0
1183 #define REG_A4XX_RB_ALPHA_CONTROL 0x000020f8
1184 #define A4XX_RB_ALPHA_CONTROL_ALPHA_REF__MASK 0x000000ff
1185 #define A4XX_RB_ALPHA_CONTROL_ALPHA_REF__SHIFT 0
1190 #define A4XX_RB_ALPHA_CONTROL_ALPHA_TEST 0x00000100
1191 #define A4XX_RB_ALPHA_CONTROL_ALPHA_TEST_FUNC__MASK 0x00000e00
1198 #define REG_A4XX_RB_FS_OUTPUT 0x000020f9
1199 #define A4XX_RB_FS_OUTPUT_ENABLE_BLEND__MASK 0x000000ff
1200 #define A4XX_RB_FS_OUTPUT_ENABLE_BLEND__SHIFT 0
1205 #define A4XX_RB_FS_OUTPUT_INDEPENDENT_BLEND 0x00000100
1206 #define A4XX_RB_FS_OUTPUT_SAMPLE_MASK__MASK 0xffff0000
1213 #define REG_A4XX_RB_SAMPLE_COUNT_CONTROL 0x000020fa
1214 #define A4XX_RB_SAMPLE_COUNT_CONTROL_COPY 0x00000002
1215 #define A4XX_RB_SAMPLE_COUNT_CONTROL_ADDR__MASK 0xfffffffc
1222 #define REG_A4XX_RB_RENDER_COMPONENTS 0x000020fb
1223 #define A4XX_RB_RENDER_COMPONENTS_RT0__MASK 0x0000000f
1224 #define A4XX_RB_RENDER_COMPONENTS_RT0__SHIFT 0
1229 #define A4XX_RB_RENDER_COMPONENTS_RT1__MASK 0x000000f0
1235 #define A4XX_RB_RENDER_COMPONENTS_RT2__MASK 0x00000f00
1241 #define A4XX_RB_RENDER_COMPONENTS_RT3__MASK 0x0000f000
1247 #define A4XX_RB_RENDER_COMPONENTS_RT4__MASK 0x000f0000
1253 #define A4XX_RB_RENDER_COMPONENTS_RT5__MASK 0x00f00000
1259 #define A4XX_RB_RENDER_COMPONENTS_RT6__MASK 0x0f000000
1265 #define A4XX_RB_RENDER_COMPONENTS_RT7__MASK 0xf0000000
1272 #define REG_A4XX_RB_COPY_CONTROL 0x000020fc
1273 #define A4XX_RB_COPY_CONTROL_MSAA_RESOLVE__MASK 0x00000003
1274 #define A4XX_RB_COPY_CONTROL_MSAA_RESOLVE__SHIFT 0
1279 #define A4XX_RB_COPY_CONTROL_MODE__MASK 0x00000070
1285 #define A4XX_RB_COPY_CONTROL_FASTCLEAR__MASK 0x00000f00
1291 #define A4XX_RB_COPY_CONTROL_GMEM_BASE__MASK 0xffffc000
1298 #define REG_A4XX_RB_COPY_DEST_BASE 0x000020fd
1299 #define A4XX_RB_COPY_DEST_BASE_BASE__MASK 0xffffffe0
1306 #define REG_A4XX_RB_COPY_DEST_PITCH 0x000020fe
1307 #define A4XX_RB_COPY_DEST_PITCH_PITCH__MASK 0xffffffff
1308 #define A4XX_RB_COPY_DEST_PITCH_PITCH__SHIFT 0
1314 #define REG_A4XX_RB_COPY_DEST_INFO 0x000020ff
1315 #define A4XX_RB_COPY_DEST_INFO_FORMAT__MASK 0x000000fc
1321 #define A4XX_RB_COPY_DEST_INFO_SWAP__MASK 0x00000300
1327 #define A4XX_RB_COPY_DEST_INFO_DITHER_MODE__MASK 0x00000c00
1333 #define A4XX_RB_COPY_DEST_INFO_COMPONENT_ENABLE__MASK 0x0003c000
1339 #define A4XX_RB_COPY_DEST_INFO_ENDIAN__MASK 0x001c0000
1345 #define A4XX_RB_COPY_DEST_INFO_TILE__MASK 0x03000000
1352 #define REG_A4XX_RB_FS_OUTPUT_REG 0x00002100
1353 #define A4XX_RB_FS_OUTPUT_REG_MRT__MASK 0x0000000f
1354 #define A4XX_RB_FS_OUTPUT_REG_MRT__SHIFT 0
1359 #define A4XX_RB_FS_OUTPUT_REG_FRAG_WRITES_Z 0x00000020
1361 #define REG_A4XX_RB_DEPTH_CONTROL 0x00002101
1362 #define A4XX_RB_DEPTH_CONTROL_FRAG_WRITES_Z 0x00000001
1363 #define A4XX_RB_DEPTH_CONTROL_Z_ENABLE 0x00000002
1364 #define A4XX_RB_DEPTH_CONTROL_Z_WRITE_ENABLE 0x00000004
1365 #define A4XX_RB_DEPTH_CONTROL_ZFUNC__MASK 0x00000070
1371 #define A4XX_RB_DEPTH_CONTROL_Z_CLAMP_ENABLE 0x00000080
1372 #define A4XX_RB_DEPTH_CONTROL_EARLY_Z_DISABLE 0x00010000
1373 #define A4XX_RB_DEPTH_CONTROL_FORCE_FRAGZ_TO_FS 0x00020000
1374 #define A4XX_RB_DEPTH_CONTROL_Z_TEST_ENABLE 0x80000000
1376 #define REG_A4XX_RB_DEPTH_CLEAR 0x00002102
1378 #define REG_A4XX_RB_DEPTH_INFO 0x00002103
1379 #define A4XX_RB_DEPTH_INFO_DEPTH_FORMAT__MASK 0x00000003
1380 #define A4XX_RB_DEPTH_INFO_DEPTH_FORMAT__SHIFT 0
1385 #define A4XX_RB_DEPTH_INFO_DEPTH_BASE__MASK 0xfffff000
1392 #define REG_A4XX_RB_DEPTH_PITCH 0x00002104
1393 #define A4XX_RB_DEPTH_PITCH__MASK 0xffffffff
1394 #define A4XX_RB_DEPTH_PITCH__SHIFT 0
1400 #define REG_A4XX_RB_DEPTH_PITCH2 0x00002105
1401 #define A4XX_RB_DEPTH_PITCH2__MASK 0xffffffff
1402 #define A4XX_RB_DEPTH_PITCH2__SHIFT 0
1408 #define REG_A4XX_RB_STENCIL_CONTROL 0x00002106
1409 #define A4XX_RB_STENCIL_CONTROL_STENCIL_ENABLE 0x00000001
1410 #define A4XX_RB_STENCIL_CONTROL_STENCIL_ENABLE_BF 0x00000002
1411 #define A4XX_RB_STENCIL_CONTROL_STENCIL_READ 0x00000004
1412 #define A4XX_RB_STENCIL_CONTROL_FUNC__MASK 0x00000700
1418 #define A4XX_RB_STENCIL_CONTROL_FAIL__MASK 0x00003800
1424 #define A4XX_RB_STENCIL_CONTROL_ZPASS__MASK 0x0001c000
1430 #define A4XX_RB_STENCIL_CONTROL_ZFAIL__MASK 0x000e0000
1436 #define A4XX_RB_STENCIL_CONTROL_FUNC_BF__MASK 0x00700000
1442 #define A4XX_RB_STENCIL_CONTROL_FAIL_BF__MASK 0x03800000
1448 #define A4XX_RB_STENCIL_CONTROL_ZPASS_BF__MASK 0x1c000000
1454 #define A4XX_RB_STENCIL_CONTROL_ZFAIL_BF__MASK 0xe0000000
1461 #define REG_A4XX_RB_STENCIL_CONTROL2 0x00002107
1462 #define A4XX_RB_STENCIL_CONTROL2_STENCIL_BUFFER 0x00000001
1464 #define REG_A4XX_RB_STENCIL_INFO 0x00002108
1465 #define A4XX_RB_STENCIL_INFO_SEPARATE_STENCIL 0x00000001
1466 #define A4XX_RB_STENCIL_INFO_STENCIL_BASE__MASK 0xfffff000
1473 #define REG_A4XX_RB_STENCIL_PITCH 0x00002109
1474 #define A4XX_RB_STENCIL_PITCH__MASK 0xffffffff
1475 #define A4XX_RB_STENCIL_PITCH__SHIFT 0
1481 #define REG_A4XX_RB_STENCILREFMASK 0x0000210b
1482 #define A4XX_RB_STENCILREFMASK_STENCILREF__MASK 0x000000ff
1483 #define A4XX_RB_STENCILREFMASK_STENCILREF__SHIFT 0
1488 #define A4XX_RB_STENCILREFMASK_STENCILMASK__MASK 0x0000ff00
1494 #define A4XX_RB_STENCILREFMASK_STENCILWRITEMASK__MASK 0x00ff0000
1501 #define REG_A4XX_RB_STENCILREFMASK_BF 0x0000210c
1502 #define A4XX_RB_STENCILREFMASK_BF_STENCILREF__MASK 0x000000ff
1503 #define A4XX_RB_STENCILREFMASK_BF_STENCILREF__SHIFT 0
1508 #define A4XX_RB_STENCILREFMASK_BF_STENCILMASK__MASK 0x0000ff00
1514 #define A4XX_RB_STENCILREFMASK_BF_STENCILWRITEMASK__MASK 0x00ff0000
1521 #define REG_A4XX_RB_BIN_OFFSET 0x0000210d
1522 #define A4XX_RB_BIN_OFFSET_WINDOW_OFFSET_DISABLE 0x80000000
1523 #define A4XX_RB_BIN_OFFSET_X__MASK 0x00007fff
1524 #define A4XX_RB_BIN_OFFSET_X__SHIFT 0
1529 #define A4XX_RB_BIN_OFFSET_Y__MASK 0x7fff0000
1536 static inline uint32_t REG_A4XX_RB_VPORT_Z_CLAMP(uint32_t i0) { return 0x00002120 + 0x2*i0; } in REG_A4XX_RB_VPORT_Z_CLAMP()
1538 static inline uint32_t REG_A4XX_RB_VPORT_Z_CLAMP_MIN(uint32_t i0) { return 0x00002120 + 0x2*i0; } in REG_A4XX_RB_VPORT_Z_CLAMP_MIN()
1540 static inline uint32_t REG_A4XX_RB_VPORT_Z_CLAMP_MAX(uint32_t i0) { return 0x00002121 + 0x2*i0; } in REG_A4XX_RB_VPORT_Z_CLAMP_MAX()
1542 #define REG_A4XX_RBBM_HW_VERSION 0x00000000
1544 #define REG_A4XX_RBBM_HW_CONFIGURATION 0x00000002
1546 static inline uint32_t REG_A4XX_RBBM_CLOCK_CTL_TP(uint32_t i0) { return 0x00000004 + 0x1*i0; } in REG_A4XX_RBBM_CLOCK_CTL_TP()
1548 static inline uint32_t REG_A4XX_RBBM_CLOCK_CTL_TP_REG(uint32_t i0) { return 0x00000004 + 0x1*i0; } in REG_A4XX_RBBM_CLOCK_CTL_TP_REG()
1550 static inline uint32_t REG_A4XX_RBBM_CLOCK_CTL2_TP(uint32_t i0) { return 0x00000008 + 0x1*i0; } in REG_A4XX_RBBM_CLOCK_CTL2_TP()
1552 static inline uint32_t REG_A4XX_RBBM_CLOCK_CTL2_TP_REG(uint32_t i0) { return 0x00000008 + 0x1*i0; } in REG_A4XX_RBBM_CLOCK_CTL2_TP_REG()
1554 static inline uint32_t REG_A4XX_RBBM_CLOCK_HYST_TP(uint32_t i0) { return 0x0000000c + 0x1*i0; } in REG_A4XX_RBBM_CLOCK_HYST_TP()
1556 static inline uint32_t REG_A4XX_RBBM_CLOCK_HYST_TP_REG(uint32_t i0) { return 0x0000000c + 0x1*i0; } in REG_A4XX_RBBM_CLOCK_HYST_TP_REG()
1558 static inline uint32_t REG_A4XX_RBBM_CLOCK_DELAY_TP(uint32_t i0) { return 0x00000010 + 0x1*i0; } in REG_A4XX_RBBM_CLOCK_DELAY_TP()
1560 static inline uint32_t REG_A4XX_RBBM_CLOCK_DELAY_TP_REG(uint32_t i0) { return 0x00000010 + 0x1*i0; } in REG_A4XX_RBBM_CLOCK_DELAY_TP_REG()
1562 #define REG_A4XX_RBBM_CLOCK_CTL_UCHE 0x00000014
1564 #define REG_A4XX_RBBM_CLOCK_CTL2_UCHE 0x00000015
1566 #define REG_A4XX_RBBM_CLOCK_CTL3_UCHE 0x00000016
1568 #define REG_A4XX_RBBM_CLOCK_CTL4_UCHE 0x00000017
1570 #define REG_A4XX_RBBM_CLOCK_HYST_UCHE 0x00000018
1572 #define REG_A4XX_RBBM_CLOCK_DELAY_UCHE 0x00000019
1574 #define REG_A4XX_RBBM_CLOCK_MODE_GPC 0x0000001a
1576 #define REG_A4XX_RBBM_CLOCK_DELAY_GPC 0x0000001b
1578 #define REG_A4XX_RBBM_CLOCK_HYST_GPC 0x0000001c
1580 #define REG_A4XX_RBBM_CLOCK_CTL_TSE_RAS_RBBM 0x0000001d
1582 #define REG_A4XX_RBBM_CLOCK_HYST_TSE_RAS_RBBM 0x0000001e
1584 #define REG_A4XX_RBBM_CLOCK_DELAY_TSE_RAS_RBBM 0x0000001f
1586 #define REG_A4XX_RBBM_CLOCK_CTL 0x00000020
1588 #define REG_A4XX_RBBM_SP_HYST_CNT 0x00000021
1590 #define REG_A4XX_RBBM_SW_RESET_CMD 0x00000022
1592 #define REG_A4XX_RBBM_AHB_CTL0 0x00000023
1594 #define REG_A4XX_RBBM_AHB_CTL1 0x00000024
1596 #define REG_A4XX_RBBM_AHB_CMD 0x00000025
1598 #define REG_A4XX_RBBM_RB_SUB_BLOCK_SEL_CTL 0x00000026
1600 #define REG_A4XX_RBBM_RAM_ACC_63_32 0x00000028
1602 #define REG_A4XX_RBBM_WAIT_IDLE_CLOCKS_CTL 0x0000002b
1604 #define REG_A4XX_RBBM_INTERFACE_HANG_INT_CTL 0x0000002f
1606 #define REG_A4XX_RBBM_INTERFACE_HANG_MASK_CTL4 0x00000034
1608 #define REG_A4XX_RBBM_INT_CLEAR_CMD 0x00000036
1610 #define REG_A4XX_RBBM_INT_0_MASK 0x00000037
1612 #define REG_A4XX_RBBM_RBBM_CTL 0x0000003e
1614 #define REG_A4XX_RBBM_AHB_DEBUG_CTL 0x0000003f
1616 #define REG_A4XX_RBBM_VBIF_DEBUG_CTL 0x00000041
1618 #define REG_A4XX_RBBM_CLOCK_CTL2 0x00000042
1620 #define REG_A4XX_RBBM_BLOCK_SW_RESET_CMD 0x00000045
1622 #define REG_A4XX_RBBM_RESET_CYCLES 0x00000047
1624 #define REG_A4XX_RBBM_EXT_TRACE_BUS_CTL 0x00000049
1626 #define REG_A4XX_RBBM_CFG_DEBBUS_SEL_A 0x0000004a
1628 #define REG_A4XX_RBBM_CFG_DEBBUS_SEL_B 0x0000004b
1630 #define REG_A4XX_RBBM_CFG_DEBBUS_SEL_C 0x0000004c
1632 #define REG_A4XX_RBBM_CFG_DEBBUS_SEL_D 0x0000004d
1634 #define REG_A4XX_RBBM_POWER_CNTL_IP 0x00000098
1635 #define A4XX_RBBM_POWER_CNTL_IP_SW_COLLAPSE 0x00000001
1636 #define A4XX_RBBM_POWER_CNTL_IP_SP_TP_PWR_ON 0x00100000
1638 #define REG_A4XX_RBBM_PERFCTR_CP_0_LO 0x0000009c
1640 #define REG_A4XX_RBBM_PERFCTR_CP_0_HI 0x0000009d
1642 #define REG_A4XX_RBBM_PERFCTR_CP_1_LO 0x0000009e
1644 #define REG_A4XX_RBBM_PERFCTR_CP_1_HI 0x0000009f
1646 #define REG_A4XX_RBBM_PERFCTR_CP_2_LO 0x000000a0
1648 #define REG_A4XX_RBBM_PERFCTR_CP_2_HI 0x000000a1
1650 #define REG_A4XX_RBBM_PERFCTR_CP_3_LO 0x000000a2
1652 #define REG_A4XX_RBBM_PERFCTR_CP_3_HI 0x000000a3
1654 #define REG_A4XX_RBBM_PERFCTR_CP_4_LO 0x000000a4
1656 #define REG_A4XX_RBBM_PERFCTR_CP_4_HI 0x000000a5
1658 #define REG_A4XX_RBBM_PERFCTR_CP_5_LO 0x000000a6
1660 #define REG_A4XX_RBBM_PERFCTR_CP_5_HI 0x000000a7
1662 #define REG_A4XX_RBBM_PERFCTR_CP_6_LO 0x000000a8
1664 #define REG_A4XX_RBBM_PERFCTR_CP_6_HI 0x000000a9
1666 #define REG_A4XX_RBBM_PERFCTR_CP_7_LO 0x000000aa
1668 #define REG_A4XX_RBBM_PERFCTR_CP_7_HI 0x000000ab
1670 #define REG_A4XX_RBBM_PERFCTR_RBBM_0_LO 0x000000ac
1672 #define REG_A4XX_RBBM_PERFCTR_RBBM_0_HI 0x000000ad
1674 #define REG_A4XX_RBBM_PERFCTR_RBBM_1_LO 0x000000ae
1676 #define REG_A4XX_RBBM_PERFCTR_RBBM_1_HI 0x000000af
1678 #define REG_A4XX_RBBM_PERFCTR_RBBM_2_LO 0x000000b0
1680 #define REG_A4XX_RBBM_PERFCTR_RBBM_2_HI 0x000000b1
1682 #define REG_A4XX_RBBM_PERFCTR_RBBM_3_LO 0x000000b2
1684 #define REG_A4XX_RBBM_PERFCTR_RBBM_3_HI 0x000000b3
1686 #define REG_A4XX_RBBM_PERFCTR_PC_0_LO 0x000000b4
1688 #define REG_A4XX_RBBM_PERFCTR_PC_0_HI 0x000000b5
1690 #define REG_A4XX_RBBM_PERFCTR_PC_1_LO 0x000000b6
1692 #define REG_A4XX_RBBM_PERFCTR_PC_1_HI 0x000000b7
1694 #define REG_A4XX_RBBM_PERFCTR_PC_2_LO 0x000000b8
1696 #define REG_A4XX_RBBM_PERFCTR_PC_2_HI 0x000000b9
1698 #define REG_A4XX_RBBM_PERFCTR_PC_3_LO 0x000000ba
1700 #define REG_A4XX_RBBM_PERFCTR_PC_3_HI 0x000000bb
1702 #define REG_A4XX_RBBM_PERFCTR_PC_4_LO 0x000000bc
1704 #define REG_A4XX_RBBM_PERFCTR_PC_4_HI 0x000000bd
1706 #define REG_A4XX_RBBM_PERFCTR_PC_5_LO 0x000000be
1708 #define REG_A4XX_RBBM_PERFCTR_PC_5_HI 0x000000bf
1710 #define REG_A4XX_RBBM_PERFCTR_PC_6_LO 0x000000c0
1712 #define REG_A4XX_RBBM_PERFCTR_PC_6_HI 0x000000c1
1714 #define REG_A4XX_RBBM_PERFCTR_PC_7_LO 0x000000c2
1716 #define REG_A4XX_RBBM_PERFCTR_PC_7_HI 0x000000c3
1718 #define REG_A4XX_RBBM_PERFCTR_VFD_0_LO 0x000000c4
1720 #define REG_A4XX_RBBM_PERFCTR_VFD_0_HI 0x000000c5
1722 #define REG_A4XX_RBBM_PERFCTR_VFD_1_LO 0x000000c6
1724 #define REG_A4XX_RBBM_PERFCTR_VFD_1_HI 0x000000c7
1726 #define REG_A4XX_RBBM_PERFCTR_VFD_2_LO 0x000000c8
1728 #define REG_A4XX_RBBM_PERFCTR_VFD_2_HI 0x000000c9
1730 #define REG_A4XX_RBBM_PERFCTR_VFD_3_LO 0x000000ca
1732 #define REG_A4XX_RBBM_PERFCTR_VFD_3_HI 0x000000cb
1734 #define REG_A4XX_RBBM_PERFCTR_VFD_4_LO 0x000000cc
1736 #define REG_A4XX_RBBM_PERFCTR_VFD_4_HI 0x000000cd
1738 #define REG_A4XX_RBBM_PERFCTR_VFD_5_LO 0x000000ce
1740 #define REG_A4XX_RBBM_PERFCTR_VFD_5_HI 0x000000cf
1742 #define REG_A4XX_RBBM_PERFCTR_VFD_6_LO 0x000000d0
1744 #define REG_A4XX_RBBM_PERFCTR_VFD_6_HI 0x000000d1
1746 #define REG_A4XX_RBBM_PERFCTR_VFD_7_LO 0x000000d2
1748 #define REG_A4XX_RBBM_PERFCTR_VFD_7_HI 0x000000d3
1750 #define REG_A4XX_RBBM_PERFCTR_HLSQ_0_LO 0x000000d4
1752 #define REG_A4XX_RBBM_PERFCTR_HLSQ_0_HI 0x000000d5
1754 #define REG_A4XX_RBBM_PERFCTR_HLSQ_1_LO 0x000000d6
1756 #define REG_A4XX_RBBM_PERFCTR_HLSQ_1_HI 0x000000d7
1758 #define REG_A4XX_RBBM_PERFCTR_HLSQ_2_LO 0x000000d8
1760 #define REG_A4XX_RBBM_PERFCTR_HLSQ_2_HI 0x000000d9
1762 #define REG_A4XX_RBBM_PERFCTR_HLSQ_3_LO 0x000000da
1764 #define REG_A4XX_RBBM_PERFCTR_HLSQ_3_HI 0x000000db
1766 #define REG_A4XX_RBBM_PERFCTR_HLSQ_4_LO 0x000000dc
1768 #define REG_A4XX_RBBM_PERFCTR_HLSQ_4_HI 0x000000dd
1770 #define REG_A4XX_RBBM_PERFCTR_HLSQ_5_LO 0x000000de
1772 #define REG_A4XX_RBBM_PERFCTR_HLSQ_5_HI 0x000000df
1774 #define REG_A4XX_RBBM_PERFCTR_HLSQ_6_LO 0x000000e0
1776 #define REG_A4XX_RBBM_PERFCTR_HLSQ_6_HI 0x000000e1
1778 #define REG_A4XX_RBBM_PERFCTR_HLSQ_7_LO 0x000000e2
1780 #define REG_A4XX_RBBM_PERFCTR_HLSQ_7_HI 0x000000e3
1782 #define REG_A4XX_RBBM_PERFCTR_VPC_0_LO 0x000000e4
1784 #define REG_A4XX_RBBM_PERFCTR_VPC_0_HI 0x000000e5
1786 #define REG_A4XX_RBBM_PERFCTR_VPC_1_LO 0x000000e6
1788 #define REG_A4XX_RBBM_PERFCTR_VPC_1_HI 0x000000e7
1790 #define REG_A4XX_RBBM_PERFCTR_VPC_2_LO 0x000000e8
1792 #define REG_A4XX_RBBM_PERFCTR_VPC_2_HI 0x000000e9
1794 #define REG_A4XX_RBBM_PERFCTR_VPC_3_LO 0x000000ea
1796 #define REG_A4XX_RBBM_PERFCTR_VPC_3_HI 0x000000eb
1798 #define REG_A4XX_RBBM_PERFCTR_CCU_0_LO 0x000000ec
1800 #define REG_A4XX_RBBM_PERFCTR_CCU_0_HI 0x000000ed
1802 #define REG_A4XX_RBBM_PERFCTR_CCU_1_LO 0x000000ee
1804 #define REG_A4XX_RBBM_PERFCTR_CCU_1_HI 0x000000ef
1806 #define REG_A4XX_RBBM_PERFCTR_CCU_2_LO 0x000000f0
1808 #define REG_A4XX_RBBM_PERFCTR_CCU_2_HI 0x000000f1
1810 #define REG_A4XX_RBBM_PERFCTR_CCU_3_LO 0x000000f2
1812 #define REG_A4XX_RBBM_PERFCTR_CCU_3_HI 0x000000f3
1814 #define REG_A4XX_RBBM_PERFCTR_TSE_0_LO 0x000000f4
1816 #define REG_A4XX_RBBM_PERFCTR_TSE_0_HI 0x000000f5
1818 #define REG_A4XX_RBBM_PERFCTR_TSE_1_LO 0x000000f6
1820 #define REG_A4XX_RBBM_PERFCTR_TSE_1_HI 0x000000f7
1822 #define REG_A4XX_RBBM_PERFCTR_TSE_2_LO 0x000000f8
1824 #define REG_A4XX_RBBM_PERFCTR_TSE_2_HI 0x000000f9
1826 #define REG_A4XX_RBBM_PERFCTR_TSE_3_LO 0x000000fa
1828 #define REG_A4XX_RBBM_PERFCTR_TSE_3_HI 0x000000fb
1830 #define REG_A4XX_RBBM_PERFCTR_RAS_0_LO 0x000000fc
1832 #define REG_A4XX_RBBM_PERFCTR_RAS_0_HI 0x000000fd
1834 #define REG_A4XX_RBBM_PERFCTR_RAS_1_LO 0x000000fe
1836 #define REG_A4XX_RBBM_PERFCTR_RAS_1_HI 0x000000ff
1838 #define REG_A4XX_RBBM_PERFCTR_RAS_2_LO 0x00000100
1840 #define REG_A4XX_RBBM_PERFCTR_RAS_2_HI 0x00000101
1842 #define REG_A4XX_RBBM_PERFCTR_RAS_3_LO 0x00000102
1844 #define REG_A4XX_RBBM_PERFCTR_RAS_3_HI 0x00000103
1846 #define REG_A4XX_RBBM_PERFCTR_UCHE_0_LO 0x00000104
1848 #define REG_A4XX_RBBM_PERFCTR_UCHE_0_HI 0x00000105
1850 #define REG_A4XX_RBBM_PERFCTR_UCHE_1_LO 0x00000106
1852 #define REG_A4XX_RBBM_PERFCTR_UCHE_1_HI 0x00000107
1854 #define REG_A4XX_RBBM_PERFCTR_UCHE_2_LO 0x00000108
1856 #define REG_A4XX_RBBM_PERFCTR_UCHE_2_HI 0x00000109
1858 #define REG_A4XX_RBBM_PERFCTR_UCHE_3_LO 0x0000010a
1860 #define REG_A4XX_RBBM_PERFCTR_UCHE_3_HI 0x0000010b
1862 #define REG_A4XX_RBBM_PERFCTR_UCHE_4_LO 0x0000010c
1864 #define REG_A4XX_RBBM_PERFCTR_UCHE_4_HI 0x0000010d
1866 #define REG_A4XX_RBBM_PERFCTR_UCHE_5_LO 0x0000010e
1868 #define REG_A4XX_RBBM_PERFCTR_UCHE_5_HI 0x0000010f
1870 #define REG_A4XX_RBBM_PERFCTR_UCHE_6_LO 0x00000110
1872 #define REG_A4XX_RBBM_PERFCTR_UCHE_6_HI 0x00000111
1874 #define REG_A4XX_RBBM_PERFCTR_UCHE_7_LO 0x00000112
1876 #define REG_A4XX_RBBM_PERFCTR_UCHE_7_HI 0x00000113
1878 #define REG_A4XX_RBBM_PERFCTR_TP_0_LO 0x00000114
1880 #define REG_A4XX_RBBM_PERFCTR_TP_0_HI 0x00000115
1882 #define REG_A4XX_RBBM_PERFCTR_TP_1_LO 0x00000116
1884 #define REG_A4XX_RBBM_PERFCTR_TP_1_HI 0x00000117
1886 #define REG_A4XX_RBBM_PERFCTR_TP_2_LO 0x00000118
1888 #define REG_A4XX_RBBM_PERFCTR_TP_2_HI 0x00000119
1890 #define REG_A4XX_RBBM_PERFCTR_TP_3_LO 0x0000011a
1892 #define REG_A4XX_RBBM_PERFCTR_TP_3_HI 0x0000011b
1894 #define REG_A4XX_RBBM_PERFCTR_TP_4_LO 0x0000011c
1896 #define REG_A4XX_RBBM_PERFCTR_TP_4_HI 0x0000011d
1898 #define REG_A4XX_RBBM_PERFCTR_TP_5_LO 0x0000011e
1900 #define REG_A4XX_RBBM_PERFCTR_TP_5_HI 0x0000011f
1902 #define REG_A4XX_RBBM_PERFCTR_TP_6_LO 0x00000120
1904 #define REG_A4XX_RBBM_PERFCTR_TP_6_HI 0x00000121
1906 #define REG_A4XX_RBBM_PERFCTR_TP_7_LO 0x00000122
1908 #define REG_A4XX_RBBM_PERFCTR_TP_7_HI 0x00000123
1910 #define REG_A4XX_RBBM_PERFCTR_SP_0_LO 0x00000124
1912 #define REG_A4XX_RBBM_PERFCTR_SP_0_HI 0x00000125
1914 #define REG_A4XX_RBBM_PERFCTR_SP_1_LO 0x00000126
1916 #define REG_A4XX_RBBM_PERFCTR_SP_1_HI 0x00000127
1918 #define REG_A4XX_RBBM_PERFCTR_SP_2_LO 0x00000128
1920 #define REG_A4XX_RBBM_PERFCTR_SP_2_HI 0x00000129
1922 #define REG_A4XX_RBBM_PERFCTR_SP_3_LO 0x0000012a
1924 #define REG_A4XX_RBBM_PERFCTR_SP_3_HI 0x0000012b
1926 #define REG_A4XX_RBBM_PERFCTR_SP_4_LO 0x0000012c
1928 #define REG_A4XX_RBBM_PERFCTR_SP_4_HI 0x0000012d
1930 #define REG_A4XX_RBBM_PERFCTR_SP_5_LO 0x0000012e
1932 #define REG_A4XX_RBBM_PERFCTR_SP_5_HI 0x0000012f
1934 #define REG_A4XX_RBBM_PERFCTR_SP_6_LO 0x00000130
1936 #define REG_A4XX_RBBM_PERFCTR_SP_6_HI 0x00000131
1938 #define REG_A4XX_RBBM_PERFCTR_SP_7_LO 0x00000132
1940 #define REG_A4XX_RBBM_PERFCTR_SP_7_HI 0x00000133
1942 #define REG_A4XX_RBBM_PERFCTR_SP_8_LO 0x00000134
1944 #define REG_A4XX_RBBM_PERFCTR_SP_8_HI 0x00000135
1946 #define REG_A4XX_RBBM_PERFCTR_SP_9_LO 0x00000136
1948 #define REG_A4XX_RBBM_PERFCTR_SP_9_HI 0x00000137
1950 #define REG_A4XX_RBBM_PERFCTR_SP_10_LO 0x00000138
1952 #define REG_A4XX_RBBM_PERFCTR_SP_10_HI 0x00000139
1954 #define REG_A4XX_RBBM_PERFCTR_SP_11_LO 0x0000013a
1956 #define REG_A4XX_RBBM_PERFCTR_SP_11_HI 0x0000013b
1958 #define REG_A4XX_RBBM_PERFCTR_RB_0_LO 0x0000013c
1960 #define REG_A4XX_RBBM_PERFCTR_RB_0_HI 0x0000013d
1962 #define REG_A4XX_RBBM_PERFCTR_RB_1_LO 0x0000013e
1964 #define REG_A4XX_RBBM_PERFCTR_RB_1_HI 0x0000013f
1966 #define REG_A4XX_RBBM_PERFCTR_RB_2_LO 0x00000140
1968 #define REG_A4XX_RBBM_PERFCTR_RB_2_HI 0x00000141
1970 #define REG_A4XX_RBBM_PERFCTR_RB_3_LO 0x00000142
1972 #define REG_A4XX_RBBM_PERFCTR_RB_3_HI 0x00000143
1974 #define REG_A4XX_RBBM_PERFCTR_RB_4_LO 0x00000144
1976 #define REG_A4XX_RBBM_PERFCTR_RB_4_HI 0x00000145
1978 #define REG_A4XX_RBBM_PERFCTR_RB_5_LO 0x00000146
1980 #define REG_A4XX_RBBM_PERFCTR_RB_5_HI 0x00000147
1982 #define REG_A4XX_RBBM_PERFCTR_RB_6_LO 0x00000148
1984 #define REG_A4XX_RBBM_PERFCTR_RB_6_HI 0x00000149
1986 #define REG_A4XX_RBBM_PERFCTR_RB_7_LO 0x0000014a
1988 #define REG_A4XX_RBBM_PERFCTR_RB_7_HI 0x0000014b
1990 #define REG_A4XX_RBBM_PERFCTR_VSC_0_LO 0x0000014c
1992 #define REG_A4XX_RBBM_PERFCTR_VSC_0_HI 0x0000014d
1994 #define REG_A4XX_RBBM_PERFCTR_VSC_1_LO 0x0000014e
1996 #define REG_A4XX_RBBM_PERFCTR_VSC_1_HI 0x0000014f
1998 #define REG_A4XX_RBBM_PERFCTR_PWR_0_LO 0x00000166
2000 #define REG_A4XX_RBBM_PERFCTR_PWR_0_HI 0x00000167
2002 #define REG_A4XX_RBBM_PERFCTR_PWR_1_LO 0x00000168
2004 #define REG_A4XX_RBBM_PERFCTR_PWR_1_HI 0x00000169
2006 #define REG_A4XX_RBBM_ALWAYSON_COUNTER_LO 0x0000016e
2008 #define REG_A4XX_RBBM_ALWAYSON_COUNTER_HI 0x0000016f
2010 static inline uint32_t REG_A4XX_RBBM_CLOCK_CTL_SP(uint32_t i0) { return 0x00000068 + 0x1*i0; } in REG_A4XX_RBBM_CLOCK_CTL_SP()
2012 static inline uint32_t REG_A4XX_RBBM_CLOCK_CTL_SP_REG(uint32_t i0) { return 0x00000068 + 0x1*i0; } in REG_A4XX_RBBM_CLOCK_CTL_SP_REG()
2014 static inline uint32_t REG_A4XX_RBBM_CLOCK_CTL2_SP(uint32_t i0) { return 0x0000006c + 0x1*i0; } in REG_A4XX_RBBM_CLOCK_CTL2_SP()
2016 static inline uint32_t REG_A4XX_RBBM_CLOCK_CTL2_SP_REG(uint32_t i0) { return 0x0000006c + 0x1*i0; } in REG_A4XX_RBBM_CLOCK_CTL2_SP_REG()
2018 static inline uint32_t REG_A4XX_RBBM_CLOCK_HYST_SP(uint32_t i0) { return 0x00000070 + 0x1*i0; } in REG_A4XX_RBBM_CLOCK_HYST_SP()
2020 static inline uint32_t REG_A4XX_RBBM_CLOCK_HYST_SP_REG(uint32_t i0) { return 0x00000070 + 0x1*i0; } in REG_A4XX_RBBM_CLOCK_HYST_SP_REG()
2022 static inline uint32_t REG_A4XX_RBBM_CLOCK_DELAY_SP(uint32_t i0) { return 0x00000074 + 0x1*i0; } in REG_A4XX_RBBM_CLOCK_DELAY_SP()
2024 static inline uint32_t REG_A4XX_RBBM_CLOCK_DELAY_SP_REG(uint32_t i0) { return 0x00000074 + 0x1*i0; } in REG_A4XX_RBBM_CLOCK_DELAY_SP_REG()
2026 static inline uint32_t REG_A4XX_RBBM_CLOCK_CTL_RB(uint32_t i0) { return 0x00000078 + 0x1*i0; } in REG_A4XX_RBBM_CLOCK_CTL_RB()
2028 static inline uint32_t REG_A4XX_RBBM_CLOCK_CTL_RB_REG(uint32_t i0) { return 0x00000078 + 0x1*i0; } in REG_A4XX_RBBM_CLOCK_CTL_RB_REG()
2030 static inline uint32_t REG_A4XX_RBBM_CLOCK_CTL2_RB(uint32_t i0) { return 0x0000007c + 0x1*i0; } in REG_A4XX_RBBM_CLOCK_CTL2_RB()
2032 static inline uint32_t REG_A4XX_RBBM_CLOCK_CTL2_RB_REG(uint32_t i0) { return 0x0000007c + 0x1*i0; } in REG_A4XX_RBBM_CLOCK_CTL2_RB_REG()
2034 static inline uint32_t REG_A4XX_RBBM_CLOCK_CTL_MARB_CCU(uint32_t i0) { return 0x00000082 + 0x1*i0; } in REG_A4XX_RBBM_CLOCK_CTL_MARB_CCU()
2036 static inline uint32_t REG_A4XX_RBBM_CLOCK_CTL_MARB_CCU_REG(uint32_t i0) { return 0x00000082 + 0x1*… in REG_A4XX_RBBM_CLOCK_CTL_MARB_CCU_REG()
2038 static inline uint32_t REG_A4XX_RBBM_CLOCK_HYST_RB_MARB_CCU(uint32_t i0) { return 0x00000086 + 0x1*… in REG_A4XX_RBBM_CLOCK_HYST_RB_MARB_CCU()
2040 …line uint32_t REG_A4XX_RBBM_CLOCK_HYST_RB_MARB_CCU_REG(uint32_t i0) { return 0x00000086 + 0x1*i0; } in REG_A4XX_RBBM_CLOCK_HYST_RB_MARB_CCU_REG()
2042 #define REG_A4XX_RBBM_CLOCK_HYST_COM_DCOM 0x00000080
2044 #define REG_A4XX_RBBM_CLOCK_CTL_COM_DCOM 0x00000081
2046 #define REG_A4XX_RBBM_CLOCK_CTL_HLSQ 0x0000008a
2048 #define REG_A4XX_RBBM_CLOCK_HYST_HLSQ 0x0000008b
2050 #define REG_A4XX_RBBM_CLOCK_DELAY_HLSQ 0x0000008c
2052 #define REG_A4XX_RBBM_CLOCK_DELAY_COM_DCOM 0x0000008d
2054 …line uint32_t REG_A4XX_RBBM_CLOCK_DELAY_RB_MARB_CCU_L1(uint32_t i0) { return 0x0000008e + 0x1*i0; } in REG_A4XX_RBBM_CLOCK_DELAY_RB_MARB_CCU_L1()
2056 … uint32_t REG_A4XX_RBBM_CLOCK_DELAY_RB_MARB_CCU_L1_REG(uint32_t i0) { return 0x0000008e + 0x1*i0; } in REG_A4XX_RBBM_CLOCK_DELAY_RB_MARB_CCU_L1_REG()
2058 #define REG_A4XX_RBBM_SP_REGFILE_SLEEP_CNTL_0 0x00000099
2060 #define REG_A4XX_RBBM_SP_REGFILE_SLEEP_CNTL_1 0x0000009a
2062 #define REG_A4XX_RBBM_PERFCTR_CTL 0x00000170
2064 #define REG_A4XX_RBBM_PERFCTR_LOAD_CMD0 0x00000171
2066 #define REG_A4XX_RBBM_PERFCTR_LOAD_CMD1 0x00000172
2068 #define REG_A4XX_RBBM_PERFCTR_LOAD_CMD2 0x00000173
2070 #define REG_A4XX_RBBM_PERFCTR_LOAD_VALUE_LO 0x00000174
2072 #define REG_A4XX_RBBM_PERFCTR_LOAD_VALUE_HI 0x00000175
2074 #define REG_A4XX_RBBM_PERFCTR_RBBM_SEL_0 0x00000176
2076 #define REG_A4XX_RBBM_PERFCTR_RBBM_SEL_1 0x00000177
2078 #define REG_A4XX_RBBM_PERFCTR_RBBM_SEL_2 0x00000178
2080 #define REG_A4XX_RBBM_PERFCTR_RBBM_SEL_3 0x00000179
2082 #define REG_A4XX_RBBM_GPU_BUSY_MASKED 0x0000017a
2084 #define REG_A4XX_RBBM_INT_0_STATUS 0x0000017d
2086 #define REG_A4XX_RBBM_CLOCK_STATUS 0x00000182
2088 #define REG_A4XX_RBBM_AHB_STATUS 0x00000189
2090 #define REG_A4XX_RBBM_AHB_ME_SPLIT_STATUS 0x0000018c
2092 #define REG_A4XX_RBBM_AHB_PFP_SPLIT_STATUS 0x0000018d
2094 #define REG_A4XX_RBBM_AHB_ERROR_STATUS 0x0000018f
2096 #define REG_A4XX_RBBM_STATUS 0x00000191
2097 #define A4XX_RBBM_STATUS_HI_BUSY 0x00000001
2098 #define A4XX_RBBM_STATUS_CP_ME_BUSY 0x00000002
2099 #define A4XX_RBBM_STATUS_CP_PFP_BUSY 0x00000004
2100 #define A4XX_RBBM_STATUS_CP_NRT_BUSY 0x00004000
2101 #define A4XX_RBBM_STATUS_VBIF_BUSY 0x00008000
2102 #define A4XX_RBBM_STATUS_TSE_BUSY 0x00010000
2103 #define A4XX_RBBM_STATUS_RAS_BUSY 0x00020000
2104 #define A4XX_RBBM_STATUS_RB_BUSY 0x00040000
2105 #define A4XX_RBBM_STATUS_PC_DCALL_BUSY 0x00080000
2106 #define A4XX_RBBM_STATUS_PC_VSD_BUSY 0x00100000
2107 #define A4XX_RBBM_STATUS_VFD_BUSY 0x00200000
2108 #define A4XX_RBBM_STATUS_VPC_BUSY 0x00400000
2109 #define A4XX_RBBM_STATUS_UCHE_BUSY 0x00800000
2110 #define A4XX_RBBM_STATUS_SP_BUSY 0x01000000
2111 #define A4XX_RBBM_STATUS_TPL1_BUSY 0x02000000
2112 #define A4XX_RBBM_STATUS_MARB_BUSY 0x04000000
2113 #define A4XX_RBBM_STATUS_VSC_BUSY 0x08000000
2114 #define A4XX_RBBM_STATUS_ARB_BUSY 0x10000000
2115 #define A4XX_RBBM_STATUS_HLSQ_BUSY 0x20000000
2116 #define A4XX_RBBM_STATUS_GPU_BUSY_NOHC 0x40000000
2117 #define A4XX_RBBM_STATUS_GPU_BUSY 0x80000000
2119 #define REG_A4XX_RBBM_INTERFACE_RRDY_STATUS5 0x0000019f
2121 #define REG_A4XX_RBBM_POWER_STATUS 0x000001b0
2122 #define A4XX_RBBM_POWER_STATUS_SP_TP_PWR_ON 0x00100000
2124 #define REG_A4XX_RBBM_WAIT_IDLE_CLOCKS_CTL2 0x000001b8
2126 #define REG_A4XX_CP_SCRATCH_UMASK 0x00000228
2128 #define REG_A4XX_CP_SCRATCH_ADDR 0x00000229
2130 #define REG_A4XX_CP_RB_BASE 0x00000200
2132 #define REG_A4XX_CP_RB_CNTL 0x00000201
2134 #define REG_A4XX_CP_RB_WPTR 0x00000205
2136 #define REG_A4XX_CP_RB_RPTR_ADDR 0x00000203
2138 #define REG_A4XX_CP_RB_RPTR 0x00000204
2140 #define REG_A4XX_CP_IB1_BASE 0x00000206
2142 #define REG_A4XX_CP_IB1_BUFSZ 0x00000207
2144 #define REG_A4XX_CP_IB2_BASE 0x00000208
2146 #define REG_A4XX_CP_IB2_BUFSZ 0x00000209
2148 #define REG_A4XX_CP_ME_NRT_ADDR 0x0000020c
2150 #define REG_A4XX_CP_ME_NRT_DATA 0x0000020d
2152 #define REG_A4XX_CP_ME_RB_DONE_DATA 0x00000217
2154 #define REG_A4XX_CP_QUEUE_THRESH2 0x00000219
2156 #define REG_A4XX_CP_MERCIU_SIZE 0x0000021b
2158 #define REG_A4XX_CP_ROQ_ADDR 0x0000021c
2160 #define REG_A4XX_CP_ROQ_DATA 0x0000021d
2162 #define REG_A4XX_CP_MEQ_ADDR 0x0000021e
2164 #define REG_A4XX_CP_MEQ_DATA 0x0000021f
2166 #define REG_A4XX_CP_MERCIU_ADDR 0x00000220
2168 #define REG_A4XX_CP_MERCIU_DATA 0x00000221
2170 #define REG_A4XX_CP_MERCIU_DATA2 0x00000222
2172 #define REG_A4XX_CP_PFP_UCODE_ADDR 0x00000223
2174 #define REG_A4XX_CP_PFP_UCODE_DATA 0x00000224
2176 #define REG_A4XX_CP_ME_RAM_WADDR 0x00000225
2178 #define REG_A4XX_CP_ME_RAM_RADDR 0x00000226
2180 #define REG_A4XX_CP_ME_RAM_DATA 0x00000227
2182 #define REG_A4XX_CP_PREEMPT 0x0000022a
2184 #define REG_A4XX_CP_CNTL 0x0000022c
2186 #define REG_A4XX_CP_ME_CNTL 0x0000022d
2188 #define REG_A4XX_CP_DEBUG 0x0000022e
2190 #define REG_A4XX_CP_DEBUG_ECO_CONTROL 0x00000231
2192 #define REG_A4XX_CP_DRAW_STATE_ADDR 0x00000232
2194 static inline uint32_t REG_A4XX_CP_PROTECT(uint32_t i0) { return 0x00000240 + 0x1*i0; } in REG_A4XX_CP_PROTECT()
2196 static inline uint32_t REG_A4XX_CP_PROTECT_REG(uint32_t i0) { return 0x00000240 + 0x1*i0; } in REG_A4XX_CP_PROTECT_REG()
2197 #define A4XX_CP_PROTECT_REG_BASE_ADDR__MASK 0x0001ffff
2198 #define A4XX_CP_PROTECT_REG_BASE_ADDR__SHIFT 0
2203 #define A4XX_CP_PROTECT_REG_MASK_LEN__MASK 0x1f000000
2209 #define A4XX_CP_PROTECT_REG_TRAP_WRITE__MASK 0x20000000
2215 #define A4XX_CP_PROTECT_REG_TRAP_READ__MASK 0x40000000
2222 #define REG_A4XX_CP_PROTECT_CTRL 0x00000250
2224 #define REG_A4XX_CP_ST_BASE 0x000004c0
2226 #define REG_A4XX_CP_STQ_AVAIL 0x000004ce
2228 #define REG_A4XX_CP_MERCIU_STAT 0x000004d0
2230 #define REG_A4XX_CP_WFI_PEND_CTR 0x000004d2
2232 #define REG_A4XX_CP_HW_FAULT 0x000004d8
2234 #define REG_A4XX_CP_PROTECT_STATUS 0x000004da
2236 #define REG_A4XX_CP_EVENTS_IN_FLIGHT 0x000004dd
2238 #define REG_A4XX_CP_PERFCTR_CP_SEL_0 0x00000500
2240 #define REG_A4XX_CP_PERFCTR_CP_SEL_1 0x00000501
2242 #define REG_A4XX_CP_PERFCTR_CP_SEL_2 0x00000502
2244 #define REG_A4XX_CP_PERFCTR_CP_SEL_3 0x00000503
2246 #define REG_A4XX_CP_PERFCTR_CP_SEL_4 0x00000504
2248 #define REG_A4XX_CP_PERFCTR_CP_SEL_5 0x00000505
2250 #define REG_A4XX_CP_PERFCTR_CP_SEL_6 0x00000506
2252 #define REG_A4XX_CP_PERFCTR_CP_SEL_7 0x00000507
2254 #define REG_A4XX_CP_PERFCOMBINER_SELECT 0x0000050b
2256 static inline uint32_t REG_A4XX_CP_SCRATCH(uint32_t i0) { return 0x00000578 + 0x1*i0; } in REG_A4XX_CP_SCRATCH()
2258 static inline uint32_t REG_A4XX_CP_SCRATCH_REG(uint32_t i0) { return 0x00000578 + 0x1*i0; } in REG_A4XX_CP_SCRATCH_REG()
2260 #define REG_A4XX_SP_VS_STATUS 0x00000ec0
2262 #define REG_A4XX_SP_MODE_CONTROL 0x00000ec3
2264 #define REG_A4XX_SP_PERFCTR_SP_SEL_0 0x00000ec4
2266 #define REG_A4XX_SP_PERFCTR_SP_SEL_1 0x00000ec5
2268 #define REG_A4XX_SP_PERFCTR_SP_SEL_2 0x00000ec6
2270 #define REG_A4XX_SP_PERFCTR_SP_SEL_3 0x00000ec7
2272 #define REG_A4XX_SP_PERFCTR_SP_SEL_4 0x00000ec8
2274 #define REG_A4XX_SP_PERFCTR_SP_SEL_5 0x00000ec9
2276 #define REG_A4XX_SP_PERFCTR_SP_SEL_6 0x00000eca
2278 #define REG_A4XX_SP_PERFCTR_SP_SEL_7 0x00000ecb
2280 #define REG_A4XX_SP_PERFCTR_SP_SEL_8 0x00000ecc
2282 #define REG_A4XX_SP_PERFCTR_SP_SEL_9 0x00000ecd
2284 #define REG_A4XX_SP_PERFCTR_SP_SEL_10 0x00000ece
2286 #define REG_A4XX_SP_PERFCTR_SP_SEL_11 0x00000ecf
2288 #define REG_A4XX_SP_SP_CTRL_REG 0x000022c0
2289 #define A4XX_SP_SP_CTRL_REG_BINNING_PASS 0x00080000
2291 #define REG_A4XX_SP_INSTR_CACHE_CTRL 0x000022c1
2292 #define A4XX_SP_INSTR_CACHE_CTRL_VS_BUFFER 0x00000080
2293 #define A4XX_SP_INSTR_CACHE_CTRL_FS_BUFFER 0x00000100
2294 #define A4XX_SP_INSTR_CACHE_CTRL_INSTR_BUFFER 0x00000400
2296 #define REG_A4XX_SP_VS_CTRL_REG0 0x000022c4
2297 #define A4XX_SP_VS_CTRL_REG0_THREADMODE__MASK 0x00000001
2298 #define A4XX_SP_VS_CTRL_REG0_THREADMODE__SHIFT 0
2303 #define A4XX_SP_VS_CTRL_REG0_VARYING 0x00000002
2304 #define A4XX_SP_VS_CTRL_REG0_CACHEINVALID 0x00000004
2305 #define A4XX_SP_VS_CTRL_REG0_HALFREGFOOTPRINT__MASK 0x000003f0
2311 #define A4XX_SP_VS_CTRL_REG0_FULLREGFOOTPRINT__MASK 0x0000fc00
2317 #define A4XX_SP_VS_CTRL_REG0_INOUTREGOVERLAP__MASK 0x000c0000
2323 #define A4XX_SP_VS_CTRL_REG0_THREADSIZE__MASK 0x00100000
2329 #define A4XX_SP_VS_CTRL_REG0_SUPERTHREADMODE 0x00200000
2330 #define A4XX_SP_VS_CTRL_REG0_PIXLODENABLE 0x00400000
2332 #define REG_A4XX_SP_VS_CTRL_REG1 0x000022c5
2333 #define A4XX_SP_VS_CTRL_REG1_CONSTLENGTH__MASK 0x000000ff
2334 #define A4XX_SP_VS_CTRL_REG1_CONSTLENGTH__SHIFT 0
2339 #define A4XX_SP_VS_CTRL_REG1_INITIALOUTSTANDING__MASK 0x7f000000
2346 #define REG_A4XX_SP_VS_PARAM_REG 0x000022c6
2347 #define A4XX_SP_VS_PARAM_REG_POSREGID__MASK 0x000000ff
2348 #define A4XX_SP_VS_PARAM_REG_POSREGID__SHIFT 0
2353 #define A4XX_SP_VS_PARAM_REG_PSIZEREGID__MASK 0x0000ff00
2359 #define A4XX_SP_VS_PARAM_REG_TOTALVSOUTVAR__MASK 0xfff00000
2366 static inline uint32_t REG_A4XX_SP_VS_OUT(uint32_t i0) { return 0x000022c7 + 0x1*i0; } in REG_A4XX_SP_VS_OUT()
2368 static inline uint32_t REG_A4XX_SP_VS_OUT_REG(uint32_t i0) { return 0x000022c7 + 0x1*i0; } in REG_A4XX_SP_VS_OUT_REG()
2369 #define A4XX_SP_VS_OUT_REG_A_REGID__MASK 0x000001ff
2370 #define A4XX_SP_VS_OUT_REG_A_REGID__SHIFT 0
2375 #define A4XX_SP_VS_OUT_REG_A_COMPMASK__MASK 0x00001e00
2381 #define A4XX_SP_VS_OUT_REG_B_REGID__MASK 0x01ff0000
2387 #define A4XX_SP_VS_OUT_REG_B_COMPMASK__MASK 0x1e000000
2394 static inline uint32_t REG_A4XX_SP_VS_VPC_DST(uint32_t i0) { return 0x000022d8 + 0x1*i0; } in REG_A4XX_SP_VS_VPC_DST()
2396 static inline uint32_t REG_A4XX_SP_VS_VPC_DST_REG(uint32_t i0) { return 0x000022d8 + 0x1*i0; } in REG_A4XX_SP_VS_VPC_DST_REG()
2397 #define A4XX_SP_VS_VPC_DST_REG_OUTLOC0__MASK 0x000000ff
2398 #define A4XX_SP_VS_VPC_DST_REG_OUTLOC0__SHIFT 0
2403 #define A4XX_SP_VS_VPC_DST_REG_OUTLOC1__MASK 0x0000ff00
2409 #define A4XX_SP_VS_VPC_DST_REG_OUTLOC2__MASK 0x00ff0000
2415 #define A4XX_SP_VS_VPC_DST_REG_OUTLOC3__MASK 0xff000000
2422 #define REG_A4XX_SP_VS_OBJ_OFFSET_REG 0x000022e0
2423 #define A4XX_SP_VS_OBJ_OFFSET_REG_CONSTOBJECTOFFSET__MASK 0x01ff0000
2429 #define A4XX_SP_VS_OBJ_OFFSET_REG_SHADEROBJOFFSET__MASK 0xfe000000
2436 #define REG_A4XX_SP_VS_OBJ_START 0x000022e1
2438 #define REG_A4XX_SP_VS_PVT_MEM_PARAM 0x000022e2
2440 #define REG_A4XX_SP_VS_PVT_MEM_ADDR 0x000022e3
2442 #define REG_A4XX_SP_VS_LENGTH_REG 0x000022e5
2444 #define REG_A4XX_SP_FS_CTRL_REG0 0x000022e8
2445 #define A4XX_SP_FS_CTRL_REG0_THREADMODE__MASK 0x00000001
2446 #define A4XX_SP_FS_CTRL_REG0_THREADMODE__SHIFT 0
2451 #define A4XX_SP_FS_CTRL_REG0_VARYING 0x00000002
2452 #define A4XX_SP_FS_CTRL_REG0_CACHEINVALID 0x00000004
2453 #define A4XX_SP_FS_CTRL_REG0_HALFREGFOOTPRINT__MASK 0x000003f0
2459 #define A4XX_SP_FS_CTRL_REG0_FULLREGFOOTPRINT__MASK 0x0000fc00
2465 #define A4XX_SP_FS_CTRL_REG0_INOUTREGOVERLAP__MASK 0x000c0000
2471 #define A4XX_SP_FS_CTRL_REG0_THREADSIZE__MASK 0x00100000
2477 #define A4XX_SP_FS_CTRL_REG0_SUPERTHREADMODE 0x00200000
2478 #define A4XX_SP_FS_CTRL_REG0_PIXLODENABLE 0x00400000
2480 #define REG_A4XX_SP_FS_CTRL_REG1 0x000022e9
2481 #define A4XX_SP_FS_CTRL_REG1_CONSTLENGTH__MASK 0x000000ff
2482 #define A4XX_SP_FS_CTRL_REG1_CONSTLENGTH__SHIFT 0
2487 #define A4XX_SP_FS_CTRL_REG1_FACENESS 0x00080000
2488 #define A4XX_SP_FS_CTRL_REG1_VARYING 0x00100000
2489 #define A4XX_SP_FS_CTRL_REG1_FRAGCOORD 0x00200000
2491 #define REG_A4XX_SP_FS_OBJ_OFFSET_REG 0x000022ea
2492 #define A4XX_SP_FS_OBJ_OFFSET_REG_CONSTOBJECTOFFSET__MASK 0x01ff0000
2498 #define A4XX_SP_FS_OBJ_OFFSET_REG_SHADEROBJOFFSET__MASK 0xfe000000
2505 #define REG_A4XX_SP_FS_OBJ_START 0x000022eb
2507 #define REG_A4XX_SP_FS_PVT_MEM_PARAM 0x000022ec
2509 #define REG_A4XX_SP_FS_PVT_MEM_ADDR 0x000022ed
2511 #define REG_A4XX_SP_FS_LENGTH_REG 0x000022ef
2513 #define REG_A4XX_SP_FS_OUTPUT_REG 0x000022f0
2514 #define A4XX_SP_FS_OUTPUT_REG_MRT__MASK 0x0000000f
2515 #define A4XX_SP_FS_OUTPUT_REG_MRT__SHIFT 0
2520 #define A4XX_SP_FS_OUTPUT_REG_DEPTH_ENABLE 0x00000080
2521 #define A4XX_SP_FS_OUTPUT_REG_DEPTH_REGID__MASK 0x0000ff00
2527 #define A4XX_SP_FS_OUTPUT_REG_SAMPLEMASK_REGID__MASK 0xff000000
2534 static inline uint32_t REG_A4XX_SP_FS_MRT(uint32_t i0) { return 0x000022f1 + 0x1*i0; } in REG_A4XX_SP_FS_MRT()
2536 static inline uint32_t REG_A4XX_SP_FS_MRT_REG(uint32_t i0) { return 0x000022f1 + 0x1*i0; } in REG_A4XX_SP_FS_MRT_REG()
2537 #define A4XX_SP_FS_MRT_REG_REGID__MASK 0x000000ff
2538 #define A4XX_SP_FS_MRT_REG_REGID__SHIFT 0
2543 #define A4XX_SP_FS_MRT_REG_HALF_PRECISION 0x00000100
2544 #define A4XX_SP_FS_MRT_REG_MRTFORMAT__MASK 0x0003f000
2550 #define A4XX_SP_FS_MRT_REG_COLOR_SRGB 0x00040000
2552 #define REG_A4XX_SP_CS_CTRL_REG0 0x00002300
2554 #define REG_A4XX_SP_CS_OBJ_OFFSET_REG 0x00002301
2556 #define REG_A4XX_SP_CS_OBJ_START 0x00002302
2558 #define REG_A4XX_SP_CS_PVT_MEM_PARAM 0x00002303
2560 #define REG_A4XX_SP_CS_PVT_MEM_ADDR 0x00002304
2562 #define REG_A4XX_SP_CS_PVT_MEM_SIZE 0x00002305
2564 #define REG_A4XX_SP_CS_LENGTH_REG 0x00002306
2566 #define REG_A4XX_SP_HS_OBJ_OFFSET_REG 0x0000230d
2567 #define A4XX_SP_HS_OBJ_OFFSET_REG_CONSTOBJECTOFFSET__MASK 0x01ff0000
2573 #define A4XX_SP_HS_OBJ_OFFSET_REG_SHADEROBJOFFSET__MASK 0xfe000000
2580 #define REG_A4XX_SP_HS_OBJ_START 0x0000230e
2582 #define REG_A4XX_SP_HS_PVT_MEM_PARAM 0x0000230f
2584 #define REG_A4XX_SP_HS_PVT_MEM_ADDR 0x00002310
2586 #define REG_A4XX_SP_HS_LENGTH_REG 0x00002312
2588 #define REG_A4XX_SP_DS_PARAM_REG 0x0000231a
2589 #define A4XX_SP_DS_PARAM_REG_POSREGID__MASK 0x000000ff
2590 #define A4XX_SP_DS_PARAM_REG_POSREGID__SHIFT 0
2595 #define A4XX_SP_DS_PARAM_REG_TOTALGSOUTVAR__MASK 0xfff00000
2602 static inline uint32_t REG_A4XX_SP_DS_OUT(uint32_t i0) { return 0x0000231b + 0x1*i0; } in REG_A4XX_SP_DS_OUT()
2604 static inline uint32_t REG_A4XX_SP_DS_OUT_REG(uint32_t i0) { return 0x0000231b + 0x1*i0; } in REG_A4XX_SP_DS_OUT_REG()
2605 #define A4XX_SP_DS_OUT_REG_A_REGID__MASK 0x000001ff
2606 #define A4XX_SP_DS_OUT_REG_A_REGID__SHIFT 0
2611 #define A4XX_SP_DS_OUT_REG_A_COMPMASK__MASK 0x00001e00
2617 #define A4XX_SP_DS_OUT_REG_B_REGID__MASK 0x01ff0000
2623 #define A4XX_SP_DS_OUT_REG_B_COMPMASK__MASK 0x1e000000
2630 static inline uint32_t REG_A4XX_SP_DS_VPC_DST(uint32_t i0) { return 0x0000232c + 0x1*i0; } in REG_A4XX_SP_DS_VPC_DST()
2632 static inline uint32_t REG_A4XX_SP_DS_VPC_DST_REG(uint32_t i0) { return 0x0000232c + 0x1*i0; } in REG_A4XX_SP_DS_VPC_DST_REG()
2633 #define A4XX_SP_DS_VPC_DST_REG_OUTLOC0__MASK 0x000000ff
2634 #define A4XX_SP_DS_VPC_DST_REG_OUTLOC0__SHIFT 0
2639 #define A4XX_SP_DS_VPC_DST_REG_OUTLOC1__MASK 0x0000ff00
2645 #define A4XX_SP_DS_VPC_DST_REG_OUTLOC2__MASK 0x00ff0000
2651 #define A4XX_SP_DS_VPC_DST_REG_OUTLOC3__MASK 0xff000000
2658 #define REG_A4XX_SP_DS_OBJ_OFFSET_REG 0x00002334
2659 #define A4XX_SP_DS_OBJ_OFFSET_REG_CONSTOBJECTOFFSET__MASK 0x01ff0000
2665 #define A4XX_SP_DS_OBJ_OFFSET_REG_SHADEROBJOFFSET__MASK 0xfe000000
2672 #define REG_A4XX_SP_DS_OBJ_START 0x00002335
2674 #define REG_A4XX_SP_DS_PVT_MEM_PARAM 0x00002336
2676 #define REG_A4XX_SP_DS_PVT_MEM_ADDR 0x00002337
2678 #define REG_A4XX_SP_DS_LENGTH_REG 0x00002339
2680 #define REG_A4XX_SP_GS_PARAM_REG 0x00002341
2681 #define A4XX_SP_GS_PARAM_REG_POSREGID__MASK 0x000000ff
2682 #define A4XX_SP_GS_PARAM_REG_POSREGID__SHIFT 0
2687 #define A4XX_SP_GS_PARAM_REG_PRIMREGID__MASK 0x0000ff00
2693 #define A4XX_SP_GS_PARAM_REG_TOTALGSOUTVAR__MASK 0xfff00000
2700 static inline uint32_t REG_A4XX_SP_GS_OUT(uint32_t i0) { return 0x00002342 + 0x1*i0; } in REG_A4XX_SP_GS_OUT()
2702 static inline uint32_t REG_A4XX_SP_GS_OUT_REG(uint32_t i0) { return 0x00002342 + 0x1*i0; } in REG_A4XX_SP_GS_OUT_REG()
2703 #define A4XX_SP_GS_OUT_REG_A_REGID__MASK 0x000001ff
2704 #define A4XX_SP_GS_OUT_REG_A_REGID__SHIFT 0
2709 #define A4XX_SP_GS_OUT_REG_A_COMPMASK__MASK 0x00001e00
2715 #define A4XX_SP_GS_OUT_REG_B_REGID__MASK 0x01ff0000
2721 #define A4XX_SP_GS_OUT_REG_B_COMPMASK__MASK 0x1e000000
2728 static inline uint32_t REG_A4XX_SP_GS_VPC_DST(uint32_t i0) { return 0x00002353 + 0x1*i0; } in REG_A4XX_SP_GS_VPC_DST()
2730 static inline uint32_t REG_A4XX_SP_GS_VPC_DST_REG(uint32_t i0) { return 0x00002353 + 0x1*i0; } in REG_A4XX_SP_GS_VPC_DST_REG()
2731 #define A4XX_SP_GS_VPC_DST_REG_OUTLOC0__MASK 0x000000ff
2732 #define A4XX_SP_GS_VPC_DST_REG_OUTLOC0__SHIFT 0
2737 #define A4XX_SP_GS_VPC_DST_REG_OUTLOC1__MASK 0x0000ff00
2743 #define A4XX_SP_GS_VPC_DST_REG_OUTLOC2__MASK 0x00ff0000
2749 #define A4XX_SP_GS_VPC_DST_REG_OUTLOC3__MASK 0xff000000
2756 #define REG_A4XX_SP_GS_OBJ_OFFSET_REG 0x0000235b
2757 #define A4XX_SP_GS_OBJ_OFFSET_REG_CONSTOBJECTOFFSET__MASK 0x01ff0000
2763 #define A4XX_SP_GS_OBJ_OFFSET_REG_SHADEROBJOFFSET__MASK 0xfe000000
2770 #define REG_A4XX_SP_GS_OBJ_START 0x0000235c
2772 #define REG_A4XX_SP_GS_PVT_MEM_PARAM 0x0000235d
2774 #define REG_A4XX_SP_GS_PVT_MEM_ADDR 0x0000235e
2776 #define REG_A4XX_SP_GS_LENGTH_REG 0x00002360
2778 #define REG_A4XX_VPC_DEBUG_RAM_SEL 0x00000e60
2780 #define REG_A4XX_VPC_DEBUG_RAM_READ 0x00000e61
2782 #define REG_A4XX_VPC_DEBUG_ECO_CONTROL 0x00000e64
2784 #define REG_A4XX_VPC_PERFCTR_VPC_SEL_0 0x00000e65
2786 #define REG_A4XX_VPC_PERFCTR_VPC_SEL_1 0x00000e66
2788 #define REG_A4XX_VPC_PERFCTR_VPC_SEL_2 0x00000e67
2790 #define REG_A4XX_VPC_PERFCTR_VPC_SEL_3 0x00000e68
2792 #define REG_A4XX_VPC_ATTR 0x00002140
2793 #define A4XX_VPC_ATTR_TOTALATTR__MASK 0x000001ff
2794 #define A4XX_VPC_ATTR_TOTALATTR__SHIFT 0
2799 #define A4XX_VPC_ATTR_PSIZE 0x00000200
2800 #define A4XX_VPC_ATTR_THRDASSIGN__MASK 0x00003000
2806 #define A4XX_VPC_ATTR_ENABLE 0x02000000
2808 #define REG_A4XX_VPC_PACK 0x00002141
2809 #define A4XX_VPC_PACK_NUMBYPASSVAR__MASK 0x000000ff
2810 #define A4XX_VPC_PACK_NUMBYPASSVAR__SHIFT 0
2815 #define A4XX_VPC_PACK_NUMFPNONPOSVAR__MASK 0x0000ff00
2821 #define A4XX_VPC_PACK_NUMNONPOSVSVAR__MASK 0x00ff0000
2828 static inline uint32_t REG_A4XX_VPC_VARYING_INTERP(uint32_t i0) { return 0x00002142 + 0x1*i0; } in REG_A4XX_VPC_VARYING_INTERP()
2830 static inline uint32_t REG_A4XX_VPC_VARYING_INTERP_MODE(uint32_t i0) { return 0x00002142 + 0x1*i0; } in REG_A4XX_VPC_VARYING_INTERP_MODE()
2832 static inline uint32_t REG_A4XX_VPC_VARYING_PS_REPL(uint32_t i0) { return 0x0000214a + 0x1*i0; } in REG_A4XX_VPC_VARYING_PS_REPL()
2834 static inline uint32_t REG_A4XX_VPC_VARYING_PS_REPL_MODE(uint32_t i0) { return 0x0000214a + 0x1*i0;… in REG_A4XX_VPC_VARYING_PS_REPL_MODE()
2836 #define REG_A4XX_VPC_SO_FLUSH_WADDR_3 0x0000216e
2838 #define REG_A4XX_VSC_BIN_SIZE 0x00000c00
2839 #define A4XX_VSC_BIN_SIZE_WIDTH__MASK 0x0000001f
2840 #define A4XX_VSC_BIN_SIZE_WIDTH__SHIFT 0
2845 #define A4XX_VSC_BIN_SIZE_HEIGHT__MASK 0x000003e0
2852 #define REG_A4XX_VSC_SIZE_ADDRESS 0x00000c01
2854 #define REG_A4XX_VSC_SIZE_ADDRESS2 0x00000c02
2856 #define REG_A4XX_VSC_DEBUG_ECO_CONTROL 0x00000c03
2858 static inline uint32_t REG_A4XX_VSC_PIPE_CONFIG(uint32_t i0) { return 0x00000c08 + 0x1*i0; } in REG_A4XX_VSC_PIPE_CONFIG()
2860 static inline uint32_t REG_A4XX_VSC_PIPE_CONFIG_REG(uint32_t i0) { return 0x00000c08 + 0x1*i0; } in REG_A4XX_VSC_PIPE_CONFIG_REG()
2861 #define A4XX_VSC_PIPE_CONFIG_REG_X__MASK 0x000003ff
2862 #define A4XX_VSC_PIPE_CONFIG_REG_X__SHIFT 0
2867 #define A4XX_VSC_PIPE_CONFIG_REG_Y__MASK 0x000ffc00
2873 #define A4XX_VSC_PIPE_CONFIG_REG_W__MASK 0x00f00000
2879 #define A4XX_VSC_PIPE_CONFIG_REG_H__MASK 0x0f000000
2886 static inline uint32_t REG_A4XX_VSC_PIPE_DATA_ADDRESS(uint32_t i0) { return 0x00000c10 + 0x1*i0; } in REG_A4XX_VSC_PIPE_DATA_ADDRESS()
2888 static inline uint32_t REG_A4XX_VSC_PIPE_DATA_ADDRESS_REG(uint32_t i0) { return 0x00000c10 + 0x1*i0… in REG_A4XX_VSC_PIPE_DATA_ADDRESS_REG()
2890 static inline uint32_t REG_A4XX_VSC_PIPE_DATA_LENGTH(uint32_t i0) { return 0x00000c18 + 0x1*i0; } in REG_A4XX_VSC_PIPE_DATA_LENGTH()
2892 static inline uint32_t REG_A4XX_VSC_PIPE_DATA_LENGTH_REG(uint32_t i0) { return 0x00000c18 + 0x1*i0;… in REG_A4XX_VSC_PIPE_DATA_LENGTH_REG()
2894 #define REG_A4XX_VSC_PIPE_PARTIAL_POSN_1 0x00000c41
2896 #define REG_A4XX_VSC_PERFCTR_VSC_SEL_0 0x00000c50
2898 #define REG_A4XX_VSC_PERFCTR_VSC_SEL_1 0x00000c51
2900 #define REG_A4XX_VFD_DEBUG_CONTROL 0x00000e40
2902 #define REG_A4XX_VFD_PERFCTR_VFD_SEL_0 0x00000e43
2904 #define REG_A4XX_VFD_PERFCTR_VFD_SEL_1 0x00000e44
2906 #define REG_A4XX_VFD_PERFCTR_VFD_SEL_2 0x00000e45
2908 #define REG_A4XX_VFD_PERFCTR_VFD_SEL_3 0x00000e46
2910 #define REG_A4XX_VFD_PERFCTR_VFD_SEL_4 0x00000e47
2912 #define REG_A4XX_VFD_PERFCTR_VFD_SEL_5 0x00000e48
2914 #define REG_A4XX_VFD_PERFCTR_VFD_SEL_6 0x00000e49
2916 #define REG_A4XX_VFD_PERFCTR_VFD_SEL_7 0x00000e4a
2918 #define REG_A4XX_VGT_CL_INITIATOR 0x000021d0
2920 #define REG_A4XX_VGT_EVENT_INITIATOR 0x000021d9
2922 #define REG_A4XX_VFD_CONTROL_0 0x00002200
2923 #define A4XX_VFD_CONTROL_0_TOTALATTRTOVS__MASK 0x000000ff
2924 #define A4XX_VFD_CONTROL_0_TOTALATTRTOVS__SHIFT 0
2929 #define A4XX_VFD_CONTROL_0_BYPASSATTROVS__MASK 0x0001fe00
2935 #define A4XX_VFD_CONTROL_0_STRMDECINSTRCNT__MASK 0x03f00000
2941 #define A4XX_VFD_CONTROL_0_STRMFETCHINSTRCNT__MASK 0xfc000000
2948 #define REG_A4XX_VFD_CONTROL_1 0x00002201
2949 #define A4XX_VFD_CONTROL_1_MAXSTORAGE__MASK 0x0000ffff
2950 #define A4XX_VFD_CONTROL_1_MAXSTORAGE__SHIFT 0
2955 #define A4XX_VFD_CONTROL_1_REGID4VTX__MASK 0x00ff0000
2961 #define A4XX_VFD_CONTROL_1_REGID4INST__MASK 0xff000000
2968 #define REG_A4XX_VFD_CONTROL_2 0x00002202
2970 #define REG_A4XX_VFD_CONTROL_3 0x00002203
2971 #define A4XX_VFD_CONTROL_3_REGID_VTXCNT__MASK 0x0000ff00
2977 #define A4XX_VFD_CONTROL_3_REGID_TESSX__MASK 0x00ff0000
2983 #define A4XX_VFD_CONTROL_3_REGID_TESSY__MASK 0xff000000
2990 #define REG_A4XX_VFD_CONTROL_4 0x00002204
2992 #define REG_A4XX_VFD_INDEX_OFFSET 0x00002208
2994 static inline uint32_t REG_A4XX_VFD_FETCH(uint32_t i0) { return 0x0000220a + 0x4*i0; } in REG_A4XX_VFD_FETCH()
2996 static inline uint32_t REG_A4XX_VFD_FETCH_INSTR_0(uint32_t i0) { return 0x0000220a + 0x4*i0; } in REG_A4XX_VFD_FETCH_INSTR_0()
2997 #define A4XX_VFD_FETCH_INSTR_0_FETCHSIZE__MASK 0x0000007f
2998 #define A4XX_VFD_FETCH_INSTR_0_FETCHSIZE__SHIFT 0
3003 #define A4XX_VFD_FETCH_INSTR_0_BUFSTRIDE__MASK 0x0001ff80
3009 #define A4XX_VFD_FETCH_INSTR_0_SWITCHNEXT 0x00080000
3010 #define A4XX_VFD_FETCH_INSTR_0_INSTANCED 0x00100000
3012 static inline uint32_t REG_A4XX_VFD_FETCH_INSTR_1(uint32_t i0) { return 0x0000220b + 0x4*i0; } in REG_A4XX_VFD_FETCH_INSTR_1()
3014 static inline uint32_t REG_A4XX_VFD_FETCH_INSTR_2(uint32_t i0) { return 0x0000220c + 0x4*i0; } in REG_A4XX_VFD_FETCH_INSTR_2()
3015 #define A4XX_VFD_FETCH_INSTR_2_SIZE__MASK 0xffffffff
3016 #define A4XX_VFD_FETCH_INSTR_2_SIZE__SHIFT 0
3022 static inline uint32_t REG_A4XX_VFD_FETCH_INSTR_3(uint32_t i0) { return 0x0000220d + 0x4*i0; } in REG_A4XX_VFD_FETCH_INSTR_3()
3023 #define A4XX_VFD_FETCH_INSTR_3_STEPRATE__MASK 0x000001ff
3024 #define A4XX_VFD_FETCH_INSTR_3_STEPRATE__SHIFT 0
3030 static inline uint32_t REG_A4XX_VFD_DECODE(uint32_t i0) { return 0x0000228a + 0x1*i0; } in REG_A4XX_VFD_DECODE()
3032 static inline uint32_t REG_A4XX_VFD_DECODE_INSTR(uint32_t i0) { return 0x0000228a + 0x1*i0; } in REG_A4XX_VFD_DECODE_INSTR()
3033 #define A4XX_VFD_DECODE_INSTR_WRITEMASK__MASK 0x0000000f
3034 #define A4XX_VFD_DECODE_INSTR_WRITEMASK__SHIFT 0
3039 #define A4XX_VFD_DECODE_INSTR_CONSTFILL 0x00000010
3040 #define A4XX_VFD_DECODE_INSTR_FORMAT__MASK 0x00000fc0
3046 #define A4XX_VFD_DECODE_INSTR_REGID__MASK 0x000ff000
3052 #define A4XX_VFD_DECODE_INSTR_INT 0x00100000
3053 #define A4XX_VFD_DECODE_INSTR_SWAP__MASK 0x00c00000
3059 #define A4XX_VFD_DECODE_INSTR_SHIFTCNT__MASK 0x1f000000
3065 #define A4XX_VFD_DECODE_INSTR_LASTCOMPVALID 0x20000000
3066 #define A4XX_VFD_DECODE_INSTR_SWITCHNEXT 0x40000000
3068 #define REG_A4XX_TPL1_DEBUG_ECO_CONTROL 0x00000f00
3070 #define REG_A4XX_TPL1_TP_MODE_CONTROL 0x00000f03
3072 #define REG_A4XX_TPL1_PERFCTR_TP_SEL_0 0x00000f04
3074 #define REG_A4XX_TPL1_PERFCTR_TP_SEL_1 0x00000f05
3076 #define REG_A4XX_TPL1_PERFCTR_TP_SEL_2 0x00000f06
3078 #define REG_A4XX_TPL1_PERFCTR_TP_SEL_3 0x00000f07
3080 #define REG_A4XX_TPL1_PERFCTR_TP_SEL_4 0x00000f08
3082 #define REG_A4XX_TPL1_PERFCTR_TP_SEL_5 0x00000f09
3084 #define REG_A4XX_TPL1_PERFCTR_TP_SEL_6 0x00000f0a
3086 #define REG_A4XX_TPL1_PERFCTR_TP_SEL_7 0x00000f0b
3088 #define REG_A4XX_TPL1_TP_TEX_OFFSET 0x00002380
3090 #define REG_A4XX_TPL1_TP_TEX_COUNT 0x00002381
3091 #define A4XX_TPL1_TP_TEX_COUNT_VS__MASK 0x000000ff
3092 #define A4XX_TPL1_TP_TEX_COUNT_VS__SHIFT 0
3097 #define A4XX_TPL1_TP_TEX_COUNT_HS__MASK 0x0000ff00
3103 #define A4XX_TPL1_TP_TEX_COUNT_DS__MASK 0x00ff0000
3109 #define A4XX_TPL1_TP_TEX_COUNT_GS__MASK 0xff000000
3116 #define REG_A4XX_TPL1_TP_VS_BORDER_COLOR_BASE_ADDR 0x00002384
3118 #define REG_A4XX_TPL1_TP_HS_BORDER_COLOR_BASE_ADDR 0x00002387
3120 #define REG_A4XX_TPL1_TP_DS_BORDER_COLOR_BASE_ADDR 0x0000238a
3122 #define REG_A4XX_TPL1_TP_GS_BORDER_COLOR_BASE_ADDR 0x0000238d
3124 #define REG_A4XX_TPL1_TP_FS_TEX_COUNT 0x000023a0
3126 #define REG_A4XX_TPL1_TP_FS_BORDER_COLOR_BASE_ADDR 0x000023a1
3128 #define REG_A4XX_TPL1_TP_CS_BORDER_COLOR_BASE_ADDR 0x000023a4
3130 #define REG_A4XX_TPL1_TP_CS_SAMPLER_BASE_ADDR 0x000023a5
3132 #define REG_A4XX_TPL1_TP_CS_TEXMEMOBJ_BASE_ADDR 0x000023a6
3134 #define REG_A4XX_GRAS_TSE_STATUS 0x00000c80
3136 #define REG_A4XX_GRAS_DEBUG_ECO_CONTROL 0x00000c81
3138 #define REG_A4XX_GRAS_PERFCTR_TSE_SEL_0 0x00000c88
3140 #define REG_A4XX_GRAS_PERFCTR_TSE_SEL_1 0x00000c89
3142 #define REG_A4XX_GRAS_PERFCTR_TSE_SEL_2 0x00000c8a
3144 #define REG_A4XX_GRAS_PERFCTR_TSE_SEL_3 0x00000c8b
3146 #define REG_A4XX_GRAS_PERFCTR_RAS_SEL_0 0x00000c8c
3148 #define REG_A4XX_GRAS_PERFCTR_RAS_SEL_1 0x00000c8d
3150 #define REG_A4XX_GRAS_PERFCTR_RAS_SEL_2 0x00000c8e
3152 #define REG_A4XX_GRAS_PERFCTR_RAS_SEL_3 0x00000c8f
3154 #define REG_A4XX_GRAS_CL_CLIP_CNTL 0x00002000
3155 #define A4XX_GRAS_CL_CLIP_CNTL_CLIP_DISABLE 0x00008000
3156 #define A4XX_GRAS_CL_CLIP_CNTL_ZNEAR_CLIP_DISABLE 0x00010000
3157 #define A4XX_GRAS_CL_CLIP_CNTL_ZFAR_CLIP_DISABLE 0x00020000
3158 #define A4XX_GRAS_CL_CLIP_CNTL_ZERO_GB_SCALE_Z 0x00400000
3160 #define REG_A4XX_GRAS_CNTL 0x00002003
3161 #define A4XX_GRAS_CNTL_IJ_PERSP 0x00000001
3162 #define A4XX_GRAS_CNTL_IJ_LINEAR 0x00000002
3164 #define REG_A4XX_GRAS_CL_GB_CLIP_ADJ 0x00002004
3165 #define A4XX_GRAS_CL_GB_CLIP_ADJ_HORZ__MASK 0x000003ff
3166 #define A4XX_GRAS_CL_GB_CLIP_ADJ_HORZ__SHIFT 0
3171 #define A4XX_GRAS_CL_GB_CLIP_ADJ_VERT__MASK 0x000ffc00
3178 #define REG_A4XX_GRAS_CL_VPORT_XOFFSET_0 0x00002008
3179 #define A4XX_GRAS_CL_VPORT_XOFFSET_0__MASK 0xffffffff
3180 #define A4XX_GRAS_CL_VPORT_XOFFSET_0__SHIFT 0
3186 #define REG_A4XX_GRAS_CL_VPORT_XSCALE_0 0x00002009
3187 #define A4XX_GRAS_CL_VPORT_XSCALE_0__MASK 0xffffffff
3188 #define A4XX_GRAS_CL_VPORT_XSCALE_0__SHIFT 0
3194 #define REG_A4XX_GRAS_CL_VPORT_YOFFSET_0 0x0000200a
3195 #define A4XX_GRAS_CL_VPORT_YOFFSET_0__MASK 0xffffffff
3196 #define A4XX_GRAS_CL_VPORT_YOFFSET_0__SHIFT 0
3202 #define REG_A4XX_GRAS_CL_VPORT_YSCALE_0 0x0000200b
3203 #define A4XX_GRAS_CL_VPORT_YSCALE_0__MASK 0xffffffff
3204 #define A4XX_GRAS_CL_VPORT_YSCALE_0__SHIFT 0
3210 #define REG_A4XX_GRAS_CL_VPORT_ZOFFSET_0 0x0000200c
3211 #define A4XX_GRAS_CL_VPORT_ZOFFSET_0__MASK 0xffffffff
3212 #define A4XX_GRAS_CL_VPORT_ZOFFSET_0__SHIFT 0
3218 #define REG_A4XX_GRAS_CL_VPORT_ZSCALE_0 0x0000200d
3219 #define A4XX_GRAS_CL_VPORT_ZSCALE_0__MASK 0xffffffff
3220 #define A4XX_GRAS_CL_VPORT_ZSCALE_0__SHIFT 0
3226 #define REG_A4XX_GRAS_SU_POINT_MINMAX 0x00002070
3227 #define A4XX_GRAS_SU_POINT_MINMAX_MIN__MASK 0x0000ffff
3228 #define A4XX_GRAS_SU_POINT_MINMAX_MIN__SHIFT 0
3233 #define A4XX_GRAS_SU_POINT_MINMAX_MAX__MASK 0xffff0000
3240 #define REG_A4XX_GRAS_SU_POINT_SIZE 0x00002071
3241 #define A4XX_GRAS_SU_POINT_SIZE__MASK 0xffffffff
3242 #define A4XX_GRAS_SU_POINT_SIZE__SHIFT 0
3248 #define REG_A4XX_GRAS_ALPHA_CONTROL 0x00002073
3249 #define A4XX_GRAS_ALPHA_CONTROL_ALPHA_TEST_ENABLE 0x00000004
3250 #define A4XX_GRAS_ALPHA_CONTROL_FORCE_FRAGZ_TO_FS 0x00000008
3252 #define REG_A4XX_GRAS_SU_POLY_OFFSET_SCALE 0x00002074
3253 #define A4XX_GRAS_SU_POLY_OFFSET_SCALE__MASK 0xffffffff
3254 #define A4XX_GRAS_SU_POLY_OFFSET_SCALE__SHIFT 0
3260 #define REG_A4XX_GRAS_SU_POLY_OFFSET_OFFSET 0x00002075
3261 #define A4XX_GRAS_SU_POLY_OFFSET_OFFSET__MASK 0xffffffff
3262 #define A4XX_GRAS_SU_POLY_OFFSET_OFFSET__SHIFT 0
3268 #define REG_A4XX_GRAS_SU_POLY_OFFSET_CLAMP 0x00002076
3269 #define A4XX_GRAS_SU_POLY_OFFSET_CLAMP__MASK 0xffffffff
3270 #define A4XX_GRAS_SU_POLY_OFFSET_CLAMP__SHIFT 0
3276 #define REG_A4XX_GRAS_DEPTH_CONTROL 0x00002077
3277 #define A4XX_GRAS_DEPTH_CONTROL_FORMAT__MASK 0x00000003
3278 #define A4XX_GRAS_DEPTH_CONTROL_FORMAT__SHIFT 0
3284 #define REG_A4XX_GRAS_SU_MODE_CONTROL 0x00002078
3285 #define A4XX_GRAS_SU_MODE_CONTROL_CULL_FRONT 0x00000001
3286 #define A4XX_GRAS_SU_MODE_CONTROL_CULL_BACK 0x00000002
3287 #define A4XX_GRAS_SU_MODE_CONTROL_FRONT_CW 0x00000004
3288 #define A4XX_GRAS_SU_MODE_CONTROL_LINEHALFWIDTH__MASK 0x000007f8
3294 #define A4XX_GRAS_SU_MODE_CONTROL_POLY_OFFSET 0x00000800
3295 #define A4XX_GRAS_SU_MODE_CONTROL_MSAA_ENABLE 0x00002000
3296 #define A4XX_GRAS_SU_MODE_CONTROL_RENDERING_PASS 0x00100000
3298 #define REG_A4XX_GRAS_SC_CONTROL 0x0000207b
3299 #define A4XX_GRAS_SC_CONTROL_RENDER_MODE__MASK 0x0000000c
3305 #define A4XX_GRAS_SC_CONTROL_MSAA_SAMPLES__MASK 0x00000380
3311 #define A4XX_GRAS_SC_CONTROL_MSAA_DISABLE 0x00000800
3312 #define A4XX_GRAS_SC_CONTROL_RASTER_MODE__MASK 0x0000f000
3319 #define REG_A4XX_GRAS_SC_SCREEN_SCISSOR_TL 0x0000207c
3320 #define A4XX_GRAS_SC_SCREEN_SCISSOR_TL_WINDOW_OFFSET_DISABLE 0x80000000
3321 #define A4XX_GRAS_SC_SCREEN_SCISSOR_TL_X__MASK 0x00007fff
3322 #define A4XX_GRAS_SC_SCREEN_SCISSOR_TL_X__SHIFT 0
3327 #define A4XX_GRAS_SC_SCREEN_SCISSOR_TL_Y__MASK 0x7fff0000
3334 #define REG_A4XX_GRAS_SC_SCREEN_SCISSOR_BR 0x0000207d
3335 #define A4XX_GRAS_SC_SCREEN_SCISSOR_BR_WINDOW_OFFSET_DISABLE 0x80000000
3336 #define A4XX_GRAS_SC_SCREEN_SCISSOR_BR_X__MASK 0x00007fff
3337 #define A4XX_GRAS_SC_SCREEN_SCISSOR_BR_X__SHIFT 0
3342 #define A4XX_GRAS_SC_SCREEN_SCISSOR_BR_Y__MASK 0x7fff0000
3349 #define REG_A4XX_GRAS_SC_WINDOW_SCISSOR_BR 0x0000209c
3350 #define A4XX_GRAS_SC_WINDOW_SCISSOR_BR_WINDOW_OFFSET_DISABLE 0x80000000
3351 #define A4XX_GRAS_SC_WINDOW_SCISSOR_BR_X__MASK 0x00007fff
3352 #define A4XX_GRAS_SC_WINDOW_SCISSOR_BR_X__SHIFT 0
3357 #define A4XX_GRAS_SC_WINDOW_SCISSOR_BR_Y__MASK 0x7fff0000
3364 #define REG_A4XX_GRAS_SC_WINDOW_SCISSOR_TL 0x0000209d
3365 #define A4XX_GRAS_SC_WINDOW_SCISSOR_TL_WINDOW_OFFSET_DISABLE 0x80000000
3366 #define A4XX_GRAS_SC_WINDOW_SCISSOR_TL_X__MASK 0x00007fff
3367 #define A4XX_GRAS_SC_WINDOW_SCISSOR_TL_X__SHIFT 0
3372 #define A4XX_GRAS_SC_WINDOW_SCISSOR_TL_Y__MASK 0x7fff0000
3379 #define REG_A4XX_GRAS_SC_EXTENT_WINDOW_BR 0x0000209e
3380 #define A4XX_GRAS_SC_EXTENT_WINDOW_BR_WINDOW_OFFSET_DISABLE 0x80000000
3381 #define A4XX_GRAS_SC_EXTENT_WINDOW_BR_X__MASK 0x00007fff
3382 #define A4XX_GRAS_SC_EXTENT_WINDOW_BR_X__SHIFT 0
3387 #define A4XX_GRAS_SC_EXTENT_WINDOW_BR_Y__MASK 0x7fff0000
3394 #define REG_A4XX_GRAS_SC_EXTENT_WINDOW_TL 0x0000209f
3395 #define A4XX_GRAS_SC_EXTENT_WINDOW_TL_WINDOW_OFFSET_DISABLE 0x80000000
3396 #define A4XX_GRAS_SC_EXTENT_WINDOW_TL_X__MASK 0x00007fff
3397 #define A4XX_GRAS_SC_EXTENT_WINDOW_TL_X__SHIFT 0
3402 #define A4XX_GRAS_SC_EXTENT_WINDOW_TL_Y__MASK 0x7fff0000
3409 #define REG_A4XX_UCHE_CACHE_MODE_CONTROL 0x00000e80
3411 #define REG_A4XX_UCHE_TRAP_BASE_LO 0x00000e83
3413 #define REG_A4XX_UCHE_TRAP_BASE_HI 0x00000e84
3415 #define REG_A4XX_UCHE_CACHE_STATUS 0x00000e88
3417 #define REG_A4XX_UCHE_INVALIDATE0 0x00000e8a
3419 #define REG_A4XX_UCHE_INVALIDATE1 0x00000e8b
3421 #define REG_A4XX_UCHE_CACHE_WAYS_VFD 0x00000e8c
3423 #define REG_A4XX_UCHE_PERFCTR_UCHE_SEL_0 0x00000e8e
3425 #define REG_A4XX_UCHE_PERFCTR_UCHE_SEL_1 0x00000e8f
3427 #define REG_A4XX_UCHE_PERFCTR_UCHE_SEL_2 0x00000e90
3429 #define REG_A4XX_UCHE_PERFCTR_UCHE_SEL_3 0x00000e91
3431 #define REG_A4XX_UCHE_PERFCTR_UCHE_SEL_4 0x00000e92
3433 #define REG_A4XX_UCHE_PERFCTR_UCHE_SEL_5 0x00000e93
3435 #define REG_A4XX_UCHE_PERFCTR_UCHE_SEL_6 0x00000e94
3437 #define REG_A4XX_UCHE_PERFCTR_UCHE_SEL_7 0x00000e95
3439 #define REG_A4XX_HLSQ_TIMEOUT_THRESHOLD 0x00000e00
3441 #define REG_A4XX_HLSQ_DEBUG_ECO_CONTROL 0x00000e04
3443 #define REG_A4XX_HLSQ_MODE_CONTROL 0x00000e05
3445 #define REG_A4XX_HLSQ_PERF_PIPE_MASK 0x00000e0e
3447 #define REG_A4XX_HLSQ_PERFCTR_HLSQ_SEL_0 0x00000e06
3449 #define REG_A4XX_HLSQ_PERFCTR_HLSQ_SEL_1 0x00000e07
3451 #define REG_A4XX_HLSQ_PERFCTR_HLSQ_SEL_2 0x00000e08
3453 #define REG_A4XX_HLSQ_PERFCTR_HLSQ_SEL_3 0x00000e09
3455 #define REG_A4XX_HLSQ_PERFCTR_HLSQ_SEL_4 0x00000e0a
3457 #define REG_A4XX_HLSQ_PERFCTR_HLSQ_SEL_5 0x00000e0b
3459 #define REG_A4XX_HLSQ_PERFCTR_HLSQ_SEL_6 0x00000e0c
3461 #define REG_A4XX_HLSQ_PERFCTR_HLSQ_SEL_7 0x00000e0d
3463 #define REG_A4XX_HLSQ_CONTROL_0_REG 0x000023c0
3464 #define A4XX_HLSQ_CONTROL_0_REG_FSTHREADSIZE__MASK 0x00000010
3470 #define A4XX_HLSQ_CONTROL_0_REG_FSSUPERTHREADENABLE 0x00000040
3471 #define A4XX_HLSQ_CONTROL_0_REG_SPSHADERRESTART 0x00000200
3472 #define A4XX_HLSQ_CONTROL_0_REG_RESERVED2 0x00000400
3473 #define A4XX_HLSQ_CONTROL_0_REG_CHUNKDISABLE 0x04000000
3474 #define A4XX_HLSQ_CONTROL_0_REG_CONSTMODE__MASK 0x08000000
3480 #define A4XX_HLSQ_CONTROL_0_REG_LAZYUPDATEDISABLE 0x10000000
3481 #define A4XX_HLSQ_CONTROL_0_REG_SPCONSTFULLUPDATE 0x20000000
3482 #define A4XX_HLSQ_CONTROL_0_REG_TPFULLUPDATE 0x40000000
3483 #define A4XX_HLSQ_CONTROL_0_REG_SINGLECONTEXT 0x80000000
3485 #define REG_A4XX_HLSQ_CONTROL_1_REG 0x000023c1
3486 #define A4XX_HLSQ_CONTROL_1_REG_VSTHREADSIZE__MASK 0x00000040
3492 #define A4XX_HLSQ_CONTROL_1_REG_VSSUPERTHREADENABLE 0x00000100
3493 #define A4XX_HLSQ_CONTROL_1_REG_RESERVED1 0x00000200
3494 #define A4XX_HLSQ_CONTROL_1_REG_COORDREGID__MASK 0x00ff0000
3500 #define A4XX_HLSQ_CONTROL_1_REG_ZWCOORDREGID__MASK 0xff000000
3507 #define REG_A4XX_HLSQ_CONTROL_2_REG 0x000023c2
3508 #define A4XX_HLSQ_CONTROL_2_REG_PRIMALLOCTHRESHOLD__MASK 0xfc000000
3514 #define A4XX_HLSQ_CONTROL_2_REG_FACEREGID__MASK 0x000003fc
3520 #define A4XX_HLSQ_CONTROL_2_REG_SAMPLEID_REGID__MASK 0x0003fc00
3526 #define A4XX_HLSQ_CONTROL_2_REG_SAMPLEMASK_REGID__MASK 0x03fc0000
3533 #define REG_A4XX_HLSQ_CONTROL_3_REG 0x000023c3
3534 #define A4XX_HLSQ_CONTROL_3_REG_IJ_PERSP_PIXEL__MASK 0x000000ff
3535 #define A4XX_HLSQ_CONTROL_3_REG_IJ_PERSP_PIXEL__SHIFT 0
3540 #define A4XX_HLSQ_CONTROL_3_REG_IJ_LINEAR_PIXEL__MASK 0x0000ff00
3546 #define A4XX_HLSQ_CONTROL_3_REG_IJ_PERSP_CENTROID__MASK 0x00ff0000
3552 #define A4XX_HLSQ_CONTROL_3_REG_IJ_LINEAR_CENTROID__MASK 0xff000000
3559 #define REG_A4XX_HLSQ_CONTROL_4_REG 0x000023c4
3560 #define A4XX_HLSQ_CONTROL_4_REG_IJ_PERSP_SAMPLE__MASK 0x000000ff
3561 #define A4XX_HLSQ_CONTROL_4_REG_IJ_PERSP_SAMPLE__SHIFT 0
3566 #define A4XX_HLSQ_CONTROL_4_REG_IJ_LINEAR_SAMPLE__MASK 0x0000ff00
3573 #define REG_A4XX_HLSQ_VS_CONTROL_REG 0x000023c5
3574 #define A4XX_HLSQ_VS_CONTROL_REG_CONSTLENGTH__MASK 0x000000ff
3575 #define A4XX_HLSQ_VS_CONTROL_REG_CONSTLENGTH__SHIFT 0
3580 #define A4XX_HLSQ_VS_CONTROL_REG_CONSTOBJECTOFFSET__MASK 0x00007f00
3586 #define A4XX_HLSQ_VS_CONTROL_REG_SSBO_ENABLE 0x00008000
3587 #define A4XX_HLSQ_VS_CONTROL_REG_ENABLED 0x00010000
3588 #define A4XX_HLSQ_VS_CONTROL_REG_SHADEROBJOFFSET__MASK 0x00fe0000
3594 #define A4XX_HLSQ_VS_CONTROL_REG_INSTRLENGTH__MASK 0xff000000
3601 #define REG_A4XX_HLSQ_FS_CONTROL_REG 0x000023c6
3602 #define A4XX_HLSQ_FS_CONTROL_REG_CONSTLENGTH__MASK 0x000000ff
3603 #define A4XX_HLSQ_FS_CONTROL_REG_CONSTLENGTH__SHIFT 0
3608 #define A4XX_HLSQ_FS_CONTROL_REG_CONSTOBJECTOFFSET__MASK 0x00007f00
3614 #define A4XX_HLSQ_FS_CONTROL_REG_SSBO_ENABLE 0x00008000
3615 #define A4XX_HLSQ_FS_CONTROL_REG_ENABLED 0x00010000
3616 #define A4XX_HLSQ_FS_CONTROL_REG_SHADEROBJOFFSET__MASK 0x00fe0000
3622 #define A4XX_HLSQ_FS_CONTROL_REG_INSTRLENGTH__MASK 0xff000000
3629 #define REG_A4XX_HLSQ_HS_CONTROL_REG 0x000023c7
3630 #define A4XX_HLSQ_HS_CONTROL_REG_CONSTLENGTH__MASK 0x000000ff
3631 #define A4XX_HLSQ_HS_CONTROL_REG_CONSTLENGTH__SHIFT 0
3636 #define A4XX_HLSQ_HS_CONTROL_REG_CONSTOBJECTOFFSET__MASK 0x00007f00
3642 #define A4XX_HLSQ_HS_CONTROL_REG_SSBO_ENABLE 0x00008000
3643 #define A4XX_HLSQ_HS_CONTROL_REG_ENABLED 0x00010000
3644 #define A4XX_HLSQ_HS_CONTROL_REG_SHADEROBJOFFSET__MASK 0x00fe0000
3650 #define A4XX_HLSQ_HS_CONTROL_REG_INSTRLENGTH__MASK 0xff000000
3657 #define REG_A4XX_HLSQ_DS_CONTROL_REG 0x000023c8
3658 #define A4XX_HLSQ_DS_CONTROL_REG_CONSTLENGTH__MASK 0x000000ff
3659 #define A4XX_HLSQ_DS_CONTROL_REG_CONSTLENGTH__SHIFT 0
3664 #define A4XX_HLSQ_DS_CONTROL_REG_CONSTOBJECTOFFSET__MASK 0x00007f00
3670 #define A4XX_HLSQ_DS_CONTROL_REG_SSBO_ENABLE 0x00008000
3671 #define A4XX_HLSQ_DS_CONTROL_REG_ENABLED 0x00010000
3672 #define A4XX_HLSQ_DS_CONTROL_REG_SHADEROBJOFFSET__MASK 0x00fe0000
3678 #define A4XX_HLSQ_DS_CONTROL_REG_INSTRLENGTH__MASK 0xff000000
3685 #define REG_A4XX_HLSQ_GS_CONTROL_REG 0x000023c9
3686 #define A4XX_HLSQ_GS_CONTROL_REG_CONSTLENGTH__MASK 0x000000ff
3687 #define A4XX_HLSQ_GS_CONTROL_REG_CONSTLENGTH__SHIFT 0
3692 #define A4XX_HLSQ_GS_CONTROL_REG_CONSTOBJECTOFFSET__MASK 0x00007f00
3698 #define A4XX_HLSQ_GS_CONTROL_REG_SSBO_ENABLE 0x00008000
3699 #define A4XX_HLSQ_GS_CONTROL_REG_ENABLED 0x00010000
3700 #define A4XX_HLSQ_GS_CONTROL_REG_SHADEROBJOFFSET__MASK 0x00fe0000
3706 #define A4XX_HLSQ_GS_CONTROL_REG_INSTRLENGTH__MASK 0xff000000
3713 #define REG_A4XX_HLSQ_CS_CONTROL_REG 0x000023ca
3714 #define A4XX_HLSQ_CS_CONTROL_REG_CONSTLENGTH__MASK 0x000000ff
3715 #define A4XX_HLSQ_CS_CONTROL_REG_CONSTLENGTH__SHIFT 0
3720 #define A4XX_HLSQ_CS_CONTROL_REG_CONSTOBJECTOFFSET__MASK 0x00007f00
3726 #define A4XX_HLSQ_CS_CONTROL_REG_SSBO_ENABLE 0x00008000
3727 #define A4XX_HLSQ_CS_CONTROL_REG_ENABLED 0x00010000
3728 #define A4XX_HLSQ_CS_CONTROL_REG_SHADEROBJOFFSET__MASK 0x00fe0000
3734 #define A4XX_HLSQ_CS_CONTROL_REG_INSTRLENGTH__MASK 0xff000000
3741 #define REG_A4XX_HLSQ_CL_NDRANGE_0 0x000023cd
3742 #define A4XX_HLSQ_CL_NDRANGE_0_KERNELDIM__MASK 0x00000003
3743 #define A4XX_HLSQ_CL_NDRANGE_0_KERNELDIM__SHIFT 0
3748 #define A4XX_HLSQ_CL_NDRANGE_0_LOCALSIZEX__MASK 0x00000ffc
3754 #define A4XX_HLSQ_CL_NDRANGE_0_LOCALSIZEY__MASK 0x003ff000
3760 #define A4XX_HLSQ_CL_NDRANGE_0_LOCALSIZEZ__MASK 0xffc00000
3767 #define REG_A4XX_HLSQ_CL_NDRANGE_1 0x000023ce
3768 #define A4XX_HLSQ_CL_NDRANGE_1_SIZE_X__MASK 0xffffffff
3769 #define A4XX_HLSQ_CL_NDRANGE_1_SIZE_X__SHIFT 0
3775 #define REG_A4XX_HLSQ_CL_NDRANGE_2 0x000023cf
3777 #define REG_A4XX_HLSQ_CL_NDRANGE_3 0x000023d0
3778 #define A4XX_HLSQ_CL_NDRANGE_3_SIZE_Y__MASK 0xffffffff
3779 #define A4XX_HLSQ_CL_NDRANGE_3_SIZE_Y__SHIFT 0
3785 #define REG_A4XX_HLSQ_CL_NDRANGE_4 0x000023d1
3787 #define REG_A4XX_HLSQ_CL_NDRANGE_5 0x000023d2
3788 #define A4XX_HLSQ_CL_NDRANGE_5_SIZE_Z__MASK 0xffffffff
3789 #define A4XX_HLSQ_CL_NDRANGE_5_SIZE_Z__SHIFT 0
3795 #define REG_A4XX_HLSQ_CL_NDRANGE_6 0x000023d3
3797 #define REG_A4XX_HLSQ_CL_CONTROL_0 0x000023d4
3798 #define A4XX_HLSQ_CL_CONTROL_0_WGIDCONSTID__MASK 0x000000ff
3799 #define A4XX_HLSQ_CL_CONTROL_0_WGIDCONSTID__SHIFT 0
3804 #define A4XX_HLSQ_CL_CONTROL_0_LOCALIDREGID__MASK 0xff000000
3811 #define REG_A4XX_HLSQ_CL_CONTROL_1 0x000023d5
3813 #define REG_A4XX_HLSQ_CL_KERNEL_CONST 0x000023d6
3815 #define REG_A4XX_HLSQ_CL_KERNEL_GROUP_X 0x000023d7
3817 #define REG_A4XX_HLSQ_CL_KERNEL_GROUP_Y 0x000023d8
3819 #define REG_A4XX_HLSQ_CL_KERNEL_GROUP_Z 0x000023d9
3821 #define REG_A4XX_HLSQ_CL_WG_OFFSET 0x000023da
3823 #define REG_A4XX_HLSQ_UPDATE_CONTROL 0x000023db
3825 #define REG_A4XX_PC_BINNING_COMMAND 0x00000d00
3826 #define A4XX_PC_BINNING_COMMAND_BINNING_ENABLE 0x00000001
3828 #define REG_A4XX_PC_TESSFACTOR_ADDR 0x00000d08
3830 #define REG_A4XX_PC_DRAWCALL_SETUP_OVERRIDE 0x00000d0c
3832 #define REG_A4XX_PC_PERFCTR_PC_SEL_0 0x00000d10
3834 #define REG_A4XX_PC_PERFCTR_PC_SEL_1 0x00000d11
3836 #define REG_A4XX_PC_PERFCTR_PC_SEL_2 0x00000d12
3838 #define REG_A4XX_PC_PERFCTR_PC_SEL_3 0x00000d13
3840 #define REG_A4XX_PC_PERFCTR_PC_SEL_4 0x00000d14
3842 #define REG_A4XX_PC_PERFCTR_PC_SEL_5 0x00000d15
3844 #define REG_A4XX_PC_PERFCTR_PC_SEL_6 0x00000d16
3846 #define REG_A4XX_PC_PERFCTR_PC_SEL_7 0x00000d17
3848 #define REG_A4XX_PC_BIN_BASE 0x000021c0
3850 #define REG_A4XX_PC_VSTREAM_CONTROL 0x000021c2
3851 #define A4XX_PC_VSTREAM_CONTROL_SIZE__MASK 0x003f0000
3857 #define A4XX_PC_VSTREAM_CONTROL_N__MASK 0x07c00000
3864 #define REG_A4XX_PC_PRIM_VTX_CNTL 0x000021c4
3865 #define A4XX_PC_PRIM_VTX_CNTL_VAROUT__MASK 0x0000000f
3866 #define A4XX_PC_PRIM_VTX_CNTL_VAROUT__SHIFT 0
3871 #define A4XX_PC_PRIM_VTX_CNTL_PRIMITIVE_RESTART 0x00100000
3872 #define A4XX_PC_PRIM_VTX_CNTL_PROVOKING_VTX_LAST 0x02000000
3873 #define A4XX_PC_PRIM_VTX_CNTL_PSIZE 0x04000000
3875 #define REG_A4XX_PC_PRIM_VTX_CNTL2 0x000021c5
3876 #define A4XX_PC_PRIM_VTX_CNTL2_POLYMODE_FRONT_PTYPE__MASK 0x00000007
3877 #define A4XX_PC_PRIM_VTX_CNTL2_POLYMODE_FRONT_PTYPE__SHIFT 0
3882 #define A4XX_PC_PRIM_VTX_CNTL2_POLYMODE_BACK_PTYPE__MASK 0x00000038
3888 #define A4XX_PC_PRIM_VTX_CNTL2_POLYMODE_ENABLE 0x00000040
3890 #define REG_A4XX_PC_RESTART_INDEX 0x000021c6
3892 #define REG_A4XX_PC_GS_PARAM 0x000021e5
3893 #define A4XX_PC_GS_PARAM_MAX_VERTICES__MASK 0x000003ff
3894 #define A4XX_PC_GS_PARAM_MAX_VERTICES__SHIFT 0
3899 #define A4XX_PC_GS_PARAM_INVOCATIONS__MASK 0x0000f800
3905 #define A4XX_PC_GS_PARAM_PRIMTYPE__MASK 0x01800000
3911 #define A4XX_PC_GS_PARAM_LAYER 0x80000000
3913 #define REG_A4XX_PC_HS_PARAM 0x000021e7
3914 #define A4XX_PC_HS_PARAM_VERTICES_OUT__MASK 0x0000003f
3915 #define A4XX_PC_HS_PARAM_VERTICES_OUT__SHIFT 0
3920 #define A4XX_PC_HS_PARAM_SPACING__MASK 0x00600000
3926 #define A4XX_PC_HS_PARAM_CW 0x00800000
3927 #define A4XX_PC_HS_PARAM_CONNECTED 0x01000000
3929 #define REG_A4XX_VBIF_VERSION 0x00003000
3931 #define REG_A4XX_VBIF_CLKON 0x00003001
3932 #define A4XX_VBIF_CLKON_FORCE_ON_TESTBUS 0x00000001
3934 #define REG_A4XX_VBIF_ABIT_SORT 0x0000301c
3936 #define REG_A4XX_VBIF_ABIT_SORT_CONF 0x0000301d
3938 #define REG_A4XX_VBIF_GATE_OFF_WRREQ_EN 0x0000302a
3940 #define REG_A4XX_VBIF_IN_RD_LIM_CONF0 0x0000302c
3942 #define REG_A4XX_VBIF_IN_RD_LIM_CONF1 0x0000302d
3944 #define REG_A4XX_VBIF_IN_WR_LIM_CONF0 0x00003030
3946 #define REG_A4XX_VBIF_IN_WR_LIM_CONF1 0x00003031
3948 #define REG_A4XX_VBIF_ROUND_ROBIN_QOS_ARB 0x00003049
3950 #define REG_A4XX_VBIF_PERF_CNT_EN0 0x000030c0
3952 #define REG_A4XX_VBIF_PERF_CNT_EN1 0x000030c1
3954 #define REG_A4XX_VBIF_PERF_CNT_EN2 0x000030c2
3956 #define REG_A4XX_VBIF_PERF_CNT_EN3 0x000030c3
3958 #define REG_A4XX_VBIF_PERF_CNT_SEL0 0x000030d0
3960 #define REG_A4XX_VBIF_PERF_CNT_SEL1 0x000030d1
3962 #define REG_A4XX_VBIF_PERF_CNT_SEL2 0x000030d2
3964 #define REG_A4XX_VBIF_PERF_CNT_SEL3 0x000030d3
3966 #define REG_A4XX_VBIF_PERF_CNT_LOW0 0x000030d8
3968 #define REG_A4XX_VBIF_PERF_CNT_LOW1 0x000030d9
3970 #define REG_A4XX_VBIF_PERF_CNT_LOW2 0x000030da
3972 #define REG_A4XX_VBIF_PERF_CNT_LOW3 0x000030db
3974 #define REG_A4XX_VBIF_PERF_CNT_HIGH0 0x000030e0
3976 #define REG_A4XX_VBIF_PERF_CNT_HIGH1 0x000030e1
3978 #define REG_A4XX_VBIF_PERF_CNT_HIGH2 0x000030e2
3980 #define REG_A4XX_VBIF_PERF_CNT_HIGH3 0x000030e3
3982 #define REG_A4XX_VBIF_PERF_PWR_CNT_EN0 0x00003100
3984 #define REG_A4XX_VBIF_PERF_PWR_CNT_EN1 0x00003101
3986 #define REG_A4XX_VBIF_PERF_PWR_CNT_EN2 0x00003102
3988 #define REG_A4XX_UNKNOWN_0CC5 0x00000cc5
3990 #define REG_A4XX_UNKNOWN_0CC6 0x00000cc6
3992 #define REG_A4XX_UNKNOWN_0D01 0x00000d01
3994 #define REG_A4XX_UNKNOWN_0E42 0x00000e42
3996 #define REG_A4XX_UNKNOWN_0EC2 0x00000ec2
3998 #define REG_A4XX_UNKNOWN_2001 0x00002001
4000 #define REG_A4XX_UNKNOWN_209B 0x0000209b
4002 #define REG_A4XX_UNKNOWN_20EF 0x000020ef
4004 #define REG_A4XX_UNKNOWN_2152 0x00002152
4006 #define REG_A4XX_UNKNOWN_2153 0x00002153
4008 #define REG_A4XX_UNKNOWN_2154 0x00002154
4010 #define REG_A4XX_UNKNOWN_2155 0x00002155
4012 #define REG_A4XX_UNKNOWN_2156 0x00002156
4014 #define REG_A4XX_UNKNOWN_2157 0x00002157
4016 #define REG_A4XX_UNKNOWN_21C3 0x000021c3
4018 #define REG_A4XX_UNKNOWN_21E6 0x000021e6
4020 #define REG_A4XX_UNKNOWN_2209 0x00002209
4022 #define REG_A4XX_UNKNOWN_22D7 0x000022d7
4024 #define REG_A4XX_UNKNOWN_2352 0x00002352
4026 #define REG_A4XX_TEX_SAMP_0 0x00000000
4027 #define A4XX_TEX_SAMP_0_MIPFILTER_LINEAR_NEAR 0x00000001
4028 #define A4XX_TEX_SAMP_0_XY_MAG__MASK 0x00000006
4034 #define A4XX_TEX_SAMP_0_XY_MIN__MASK 0x00000018
4040 #define A4XX_TEX_SAMP_0_WRAP_S__MASK 0x000000e0
4046 #define A4XX_TEX_SAMP_0_WRAP_T__MASK 0x00000700
4052 #define A4XX_TEX_SAMP_0_WRAP_R__MASK 0x00003800
4058 #define A4XX_TEX_SAMP_0_ANISO__MASK 0x0001c000
4064 #define A4XX_TEX_SAMP_0_LOD_BIAS__MASK 0xfff80000
4071 #define REG_A4XX_TEX_SAMP_1 0x00000001
4072 #define A4XX_TEX_SAMP_1_COMPARE_FUNC__MASK 0x0000000e
4078 #define A4XX_TEX_SAMP_1_CUBEMAPSEAMLESSFILTOFF 0x00000010
4079 #define A4XX_TEX_SAMP_1_UNNORM_COORDS 0x00000020
4080 #define A4XX_TEX_SAMP_1_MIPFILTER_LINEAR_FAR 0x00000040
4081 #define A4XX_TEX_SAMP_1_MAX_LOD__MASK 0x000fff00
4087 #define A4XX_TEX_SAMP_1_MIN_LOD__MASK 0xfff00000
4094 #define REG_A4XX_TEX_CONST_0 0x00000000
4095 #define A4XX_TEX_CONST_0_TILED 0x00000001
4096 #define A4XX_TEX_CONST_0_SRGB 0x00000004
4097 #define A4XX_TEX_CONST_0_SWIZ_X__MASK 0x00000070
4103 #define A4XX_TEX_CONST_0_SWIZ_Y__MASK 0x00000380
4109 #define A4XX_TEX_CONST_0_SWIZ_Z__MASK 0x00001c00
4115 #define A4XX_TEX_CONST_0_SWIZ_W__MASK 0x0000e000
4121 #define A4XX_TEX_CONST_0_MIPLVLS__MASK 0x000f0000
4127 #define A4XX_TEX_CONST_0_FMT__MASK 0x1fc00000
4133 #define A4XX_TEX_CONST_0_TYPE__MASK 0x60000000
4140 #define REG_A4XX_TEX_CONST_1 0x00000001
4141 #define A4XX_TEX_CONST_1_HEIGHT__MASK 0x00007fff
4142 #define A4XX_TEX_CONST_1_HEIGHT__SHIFT 0
4147 #define A4XX_TEX_CONST_1_WIDTH__MASK 0x3fff8000
4154 #define REG_A4XX_TEX_CONST_2 0x00000002
4155 #define A4XX_TEX_CONST_2_PITCHALIGN__MASK 0x0000000f
4156 #define A4XX_TEX_CONST_2_PITCHALIGN__SHIFT 0
4161 #define A4XX_TEX_CONST_2_PITCH__MASK 0x3ffffe00
4167 #define A4XX_TEX_CONST_2_SWAP__MASK 0xc0000000
4174 #define REG_A4XX_TEX_CONST_3 0x00000003
4175 #define A4XX_TEX_CONST_3_LAYERSZ__MASK 0x00003fff
4176 #define A4XX_TEX_CONST_3_LAYERSZ__SHIFT 0
4181 #define A4XX_TEX_CONST_3_DEPTH__MASK 0x7ffc0000
4188 #define REG_A4XX_TEX_CONST_4 0x00000004
4189 #define A4XX_TEX_CONST_4_LAYERSZ__MASK 0x0000000f
4190 #define A4XX_TEX_CONST_4_LAYERSZ__SHIFT 0
4195 #define A4XX_TEX_CONST_4_BASE__MASK 0xffffffe0
4202 #define REG_A4XX_TEX_CONST_5 0x00000005
4204 #define REG_A4XX_TEX_CONST_6 0x00000006
4206 #define REG_A4XX_TEX_CONST_7 0x00000007
4208 #define REG_A4XX_SSBO_0_0 0x00000000
4209 #define A4XX_SSBO_0_0_BASE__MASK 0xffffffe0
4216 #define REG_A4XX_SSBO_0_1 0x00000001
4217 #define A4XX_SSBO_0_1_PITCH__MASK 0x003fffff
4218 #define A4XX_SSBO_0_1_PITCH__SHIFT 0
4224 #define REG_A4XX_SSBO_0_2 0x00000002
4225 #define A4XX_SSBO_0_2_ARRAY_PITCH__MASK 0x03fff000
4232 #define REG_A4XX_SSBO_0_3 0x00000003
4233 #define A4XX_SSBO_0_3_CPP__MASK 0x0000003f
4234 #define A4XX_SSBO_0_3_CPP__SHIFT 0
4240 #define REG_A4XX_SSBO_1_0 0x00000000
4241 #define A4XX_SSBO_1_0_CPP__MASK 0x0000001f
4242 #define A4XX_SSBO_1_0_CPP__SHIFT 0
4247 #define A4XX_SSBO_1_0_FMT__MASK 0x0000ff00
4253 #define A4XX_SSBO_1_0_WIDTH__MASK 0xffff0000
4260 #define REG_A4XX_SSBO_1_1 0x00000001
4261 #define A4XX_SSBO_1_1_HEIGHT__MASK 0x0000ffff
4262 #define A4XX_SSBO_1_1_HEIGHT__SHIFT 0
4267 #define A4XX_SSBO_1_1_DEPTH__MASK 0xffff0000