Lines Matching +full:protected +full:- +full:clocks
1 // SPDX-License-Identifier: GPL-2.0
15 struct msm_drm_private *priv = gpu->dev->dev_private; in a2xx_submit()
16 struct msm_ringbuffer *ring = submit->ring; in a2xx_submit()
19 for (i = 0; i < submit->nr_cmds; i++) { in a2xx_submit()
20 switch (submit->cmd[i].type) { in a2xx_submit()
22 /* ignore IB-targets */ in a2xx_submit()
26 if (priv->lastctx == submit->queue->ctx) in a2xx_submit()
31 OUT_RING(ring, lower_32_bits(submit->cmd[i].iova)); in a2xx_submit()
32 OUT_RING(ring, submit->cmd[i].size); in a2xx_submit()
39 OUT_RING(ring, submit->seqno); in a2xx_submit()
48 OUT_RING(ring, submit->seqno); in a2xx_submit()
57 struct msm_ringbuffer *ring = gpu->rb[0]; in a2xx_me_init()
63 /* Disable/Enable Real-Time Stream processing (present but ignored) */ in a2xx_me_init()
65 /* Enable (2D <-> 3D) implicit synchronization (present but ignored) */ in a2xx_me_init()
68 OUT_RING(ring, REG_A2XX_RB_SURFACE_INFO - 0x2000); in a2xx_me_init()
69 OUT_RING(ring, REG_A2XX_PA_SC_WINDOW_OFFSET - 0x2000); in a2xx_me_init()
70 OUT_RING(ring, REG_A2XX_VGT_MAX_VTX_INDX - 0x2000); in a2xx_me_init()
71 OUT_RING(ring, REG_A2XX_SQ_PROGRAM_CNTL - 0x2000); in a2xx_me_init()
72 OUT_RING(ring, REG_A2XX_RB_DEPTHCONTROL - 0x2000); in a2xx_me_init()
73 OUT_RING(ring, REG_A2XX_PA_SU_POINT_SIZE - 0x2000); in a2xx_me_init()
74 OUT_RING(ring, REG_A2XX_PA_SC_LINE_CNTL - 0x2000); in a2xx_me_init()
75 OUT_RING(ring, REG_A2XX_PA_SU_POLY_OFFSET_FRONT_SCALE - 0x2000); in a2xx_me_init()
83 * wait_interval * 16 clocks between polling */ in a2xx_me_init()
87 /* protected mode error checking (0x1f2 is REG_AXXX_CP_INT_CNTL) */ in a2xx_me_init()
94 /* enable protected mode */ in a2xx_me_init()
109 msm_gpummu_params(gpu->aspace->mmu, &pt_base, &tran_error); in a2xx_hw_init()
111 DBG("%s", gpu->name); in a2xx_hw_init()
201 if ((SZ_16K << i) == adreno_gpu->gmem) in a2xx_hw_init()
212 gpu_write(gpu, REG_AXXX_CP_RB_BASE, lower_32_bits(gpu->rb[0]->iova)); in a2xx_hw_init()
214 /* NOTE: PM4/micro-engine firmware registers look to be the same in a2xx_hw_init()
221 ptr = (uint32_t *)(adreno_gpu->fw[ADRENO_FW_PM4]->data); in a2xx_hw_init()
222 len = adreno_gpu->fw[ADRENO_FW_PM4]->size / 4; in a2xx_hw_init()
232 ptr = (uint32_t *)(adreno_gpu->fw[ADRENO_FW_PFP]->data); in a2xx_hw_init()
233 len = adreno_gpu->fw[ADRENO_FW_PFP]->size / 4; in a2xx_hw_init()
245 return a2xx_me_init(gpu) ? 0 : -EINVAL; in a2xx_hw_init()
274 DBG("%s", gpu->name); in a2xx_destroy()
284 if (!adreno_idle(gpu, gpu->rb[0])) in a2xx_idle()
290 DRM_ERROR("%s: timeout waiting for GPU to idle!\n", gpu->name); in a2xx_idle()
308 dev_warn(gpu->dev->dev, "MH_INT: %08X\n", status); in a2xx_irq()
309 dev_warn(gpu->dev->dev, "MMU_PAGE_FAULT: %08X\n", in a2xx_irq()
320 dev_warn(gpu->dev->dev, "CP_INT: %08X\n", status); in a2xx_irq()
328 dev_warn(gpu->dev->dev, "RBBM_INT: %08X\n", status); in a2xx_irq()
442 return ERR_PTR(-ENOMEM); in a2xx_gpu_state_get()
446 state->rbbm_status = gpu_read(gpu, REG_A2XX_RBBM_STATUS); in a2xx_gpu_state_get()
454 struct msm_mmu *mmu = msm_gpummu_new(&pdev->dev, gpu); in a2xx_create_address_space()
461 mmu->funcs->destroy(mmu); in a2xx_create_address_space()
468 ring->memptrs->rptr = gpu_read(gpu, REG_AXXX_CP_RB_RPTR); in a2xx_get_rptr()
469 return ring->memptrs->rptr; in a2xx_get_rptr()
502 struct msm_drm_private *priv = dev->dev_private; in a2xx_gpu_init()
503 struct platform_device *pdev = priv->gpu_pdev; in a2xx_gpu_init()
507 dev_err(dev->dev, "no a2xx device\n"); in a2xx_gpu_init()
508 ret = -ENXIO; in a2xx_gpu_init()
514 ret = -ENOMEM; in a2xx_gpu_init()
518 adreno_gpu = &a2xx_gpu->base; in a2xx_gpu_init()
519 gpu = &adreno_gpu->base; in a2xx_gpu_init()
521 gpu->perfcntrs = perfcntrs; in a2xx_gpu_init()
522 gpu->num_perfcntrs = ARRAY_SIZE(perfcntrs); in a2xx_gpu_init()
525 adreno_gpu->registers = a200_registers; in a2xx_gpu_init()
527 adreno_gpu->registers = a225_registers; in a2xx_gpu_init()
529 adreno_gpu->registers = a220_registers; in a2xx_gpu_init()
535 if (!gpu->aspace) { in a2xx_gpu_init()
536 dev_err(dev->dev, "No memory protection without MMU\n"); in a2xx_gpu_init()
537 ret = -ENXIO; in a2xx_gpu_init()
545 a2xx_destroy(&a2xx_gpu->base.base); in a2xx_gpu_init()