10 static void a2xx_dump(struct msm_gpu *gpu);
11 static bool a2xx_idle(struct msm_gpu *gpu);
13 static void a2xx_submit(struct msm_gpu *gpu, struct msm_gem_submit *submit)  in a2xx_submit()  argument
15 	struct msm_drm_private *priv = gpu->dev->dev_private;  in a2xx_submit()
52 	adreno_flush(gpu, ring, REG_AXXX_CP_RB_WPTR);  in a2xx_submit()
55 static bool a2xx_me_init(struct msm_gpu *gpu)  in a2xx_me_init()  argument
57 	struct msm_ringbuffer *ring = gpu->rb[0];  in a2xx_me_init()
98 	adreno_flush(gpu, ring, REG_AXXX_CP_RB_WPTR);  in a2xx_me_init()
99 	return a2xx_idle(gpu);  in a2xx_me_init()
102 static int a2xx_hw_init(struct msm_gpu *gpu)  in a2xx_hw_init()  argument
104 	struct adreno_gpu *adreno_gpu = to_adreno_gpu(gpu);  in a2xx_hw_init()
109 	msm_gpummu_params(gpu->aspace->mmu, &pt_base, &tran_error);  in a2xx_hw_init()
111 	DBG("%s", gpu->name);  in a2xx_hw_init()
114 	gpu_write(gpu, REG_AXXX_CP_ME_CNTL, AXXX_CP_ME_CNTL_HALT);  in a2xx_hw_init()
116 	gpu_write(gpu, REG_A2XX_RBBM_PM_OVERRIDE1, 0xfffffffe);  in a2xx_hw_init()
117 	gpu_write(gpu, REG_A2XX_RBBM_PM_OVERRIDE2, 0xffffffff);  in a2xx_hw_init()
120 	gpu_write(gpu, REG_A2XX_RBBM_SOFT_RESET, 0xffffffff);  in a2xx_hw_init()
122 	gpu_write(gpu, REG_A2XX_RBBM_SOFT_RESET, 0x00000000);  in a2xx_hw_init()
125 		gpu_write(gpu, REG_A2XX_SQ_FLOW_CONTROL, 0x18000000);  in a2xx_hw_init()
128 	gpu_write(gpu, REG_A2XX_RBBM_CNTL, 0x00004442);  in a2xx_hw_init()
131 	gpu_write(gpu, REG_A2XX_MH_MMU_MPU_BASE, 0x00000000);  in a2xx_hw_init()
132 	gpu_write(gpu, REG_A2XX_MH_MMU_MPU_END, 0xfffff000);  in a2xx_hw_init()
134 	gpu_write(gpu, REG_A2XX_MH_MMU_CONFIG, A2XX_MH_MMU_CONFIG_MMU_ENABLE |  in a2xx_hw_init()
148 	gpu_write(gpu, REG_A2XX_MH_MMU_VA_RANGE, SZ_16M |  in a2xx_hw_init()
151 	gpu_write(gpu, REG_A2XX_MH_MMU_PT_BASE, pt_base);  in a2xx_hw_init()
152 	gpu_write(gpu, REG_A2XX_MH_MMU_TRAN_ERROR, tran_error);  in a2xx_hw_init()
154 	gpu_write(gpu, REG_A2XX_MH_MMU_INVALIDATE,  in a2xx_hw_init()
158 	gpu_write(gpu, REG_A2XX_MH_ARBITER_CONFIG,  in a2xx_hw_init()
173 		gpu_write(gpu, REG_A2XX_MH_CLNT_INTF_CTRL_CONFIG1, 0x00032f07);  in a2xx_hw_init()
175 	gpu_write(gpu, REG_A2XX_SQ_VS_PROGRAM, 0x00000000);  in a2xx_hw_init()
176 	gpu_write(gpu, REG_A2XX_SQ_PS_PROGRAM, 0x00000000);  in a2xx_hw_init()
178 	gpu_write(gpu, REG_A2XX_RBBM_PM_OVERRIDE1, 0); /* 0x200 for msm8960? */  in a2xx_hw_init()
179 	gpu_write(gpu, REG_A2XX_RBBM_PM_OVERRIDE2, 0); /* 0x80/0x1a0 for a22x? */  in a2xx_hw_init()
182 	gpu_write(gpu, REG_A2XX_RBBM_DEBUG, 0x00080000);  in a2xx_hw_init()
184 	gpu_write(gpu, REG_A2XX_RBBM_INT_CNTL,  in a2xx_hw_init()
186 	gpu_write(gpu, REG_AXXX_CP_INT_CNTL,  in a2xx_hw_init()
194 	gpu_write(gpu, REG_A2XX_SQ_INT_CNTL, 0);  in a2xx_hw_init()
195 	gpu_write(gpu, REG_A2XX_MH_INTERRUPT_MASK,  in a2xx_hw_init()
203 	gpu_write(gpu, REG_A2XX_RB_EDRAM_INFO, i);  in a2xx_hw_init()
205 	ret = adreno_hw_init(gpu);  in a2xx_hw_init()
209 	gpu_write(gpu, REG_AXXX_CP_RB_CNTL,  in a2xx_hw_init()
212 	gpu_write(gpu, REG_AXXX_CP_RB_BASE, lower_32_bits(gpu->rb[0]->iova));  in a2xx_hw_init()
225 	gpu_write(gpu, REG_AXXX_CP_DEBUG,  in a2xx_hw_init()
227 	gpu_write(gpu, REG_AXXX_CP_ME_RAM_WADDR, 0);  in a2xx_hw_init()
229 		gpu_write(gpu, REG_AXXX_CP_ME_RAM_DATA, ptr[i]);  in a2xx_hw_init()
236 	gpu_write(gpu, REG_A2XX_CP_PFP_UCODE_ADDR, 0);  in a2xx_hw_init()
238 		gpu_write(gpu, REG_A2XX_CP_PFP_UCODE_DATA, ptr[i]);  in a2xx_hw_init()
240 	gpu_write(gpu, REG_AXXX_CP_QUEUE_THRESHOLDS, 0x000C0804);  in a2xx_hw_init()
243 	gpu_write(gpu, REG_AXXX_CP_ME_CNTL, 0);  in a2xx_hw_init()
245 	return a2xx_me_init(gpu) ? 0 : -EINVAL;  in a2xx_hw_init()
248 static void a2xx_recover(struct msm_gpu *gpu)  in a2xx_recover()  argument
252 	adreno_dump_info(gpu);  in a2xx_recover()
256 			gpu_read(gpu, REG_AXXX_CP_SCRATCH_REG0 + i));  in a2xx_recover()
259 	/* dump registers before resetting gpu, if enabled: */  in a2xx_recover()
261 		a2xx_dump(gpu);  in a2xx_recover()
263 	gpu_write(gpu, REG_A2XX_RBBM_SOFT_RESET, 1);  in a2xx_recover()
264 	gpu_read(gpu, REG_A2XX_RBBM_SOFT_RESET);  in a2xx_recover()
265 	gpu_write(gpu, REG_A2XX_RBBM_SOFT_RESET, 0);  in a2xx_recover()
266 	adreno_recover(gpu);  in a2xx_recover()
269 static void a2xx_destroy(struct msm_gpu *gpu)  in a2xx_destroy()  argument
271 	struct adreno_gpu *adreno_gpu = to_adreno_gpu(gpu);  in a2xx_destroy()
274 	DBG("%s", gpu->name);  in a2xx_destroy()
281 static bool a2xx_idle(struct msm_gpu *gpu)  in a2xx_idle()  argument
284 	if (!adreno_idle(gpu, gpu->rb[0]))  in a2xx_idle()
287 	/* then wait for GPU to finish: */  in a2xx_idle()
288 	if (spin_until(!(gpu_read(gpu, REG_A2XX_RBBM_STATUS) &  in a2xx_idle()
290 		DRM_ERROR("%s: timeout waiting for GPU to idle!\n", gpu->name);  in a2xx_idle()
292 		/* TODO maybe we need to reset GPU here to recover from hang? */  in a2xx_idle()
299 static irqreturn_t a2xx_irq(struct msm_gpu *gpu)  in a2xx_irq()  argument
303 	mstatus = gpu_read(gpu, REG_A2XX_MASTER_INT_SIGNAL);  in a2xx_irq()
306 		status = gpu_read(gpu, REG_A2XX_MH_INTERRUPT_STATUS);  in a2xx_irq()
308 		dev_warn(gpu->dev->dev, "MH_INT: %08X\n", status);  in a2xx_irq()
309 		dev_warn(gpu->dev->dev, "MMU_PAGE_FAULT: %08X\n",  in a2xx_irq()
310 			gpu_read(gpu, REG_A2XX_MH_MMU_PAGE_FAULT));  in a2xx_irq()
312 		gpu_write(gpu, REG_A2XX_MH_INTERRUPT_CLEAR, status);  in a2xx_irq()
316 		status = gpu_read(gpu, REG_AXXX_CP_INT_STATUS);  in a2xx_irq()
320 			dev_warn(gpu->dev->dev, "CP_INT: %08X\n", status);  in a2xx_irq()
322 		gpu_write(gpu, REG_AXXX_CP_INT_ACK, status);  in a2xx_irq()
326 		status = gpu_read(gpu, REG_A2XX_RBBM_INT_STATUS);  in a2xx_irq()
328 		dev_warn(gpu->dev->dev, "RBBM_INT: %08X\n", status);  in a2xx_irq()
330 		gpu_write(gpu, REG_A2XX_RBBM_INT_ACK, status);  in a2xx_irq()
333 	msm_gpu_retire(gpu);  in a2xx_irq()
430 static void a2xx_dump(struct msm_gpu *gpu)  in a2xx_dump()  argument
433 			gpu_read(gpu, REG_A2XX_RBBM_STATUS));  in a2xx_dump()
434 	adreno_dump(gpu);  in a2xx_dump()
437 static struct msm_gpu_state *a2xx_gpu_state_get(struct msm_gpu *gpu)  in a2xx_gpu_state_get()  argument
444 	adreno_gpu_state_get(gpu, state);  in a2xx_gpu_state_get()
446 	state->rbbm_status = gpu_read(gpu, REG_A2XX_RBBM_STATUS);  in a2xx_gpu_state_get()
452 a2xx_create_address_space(struct msm_gpu *gpu, struct platform_device *pdev)  in a2xx_create_address_space()  argument
454 	struct msm_mmu *mmu = msm_gpummu_new(&pdev->dev, gpu);  in a2xx_create_address_space()
457 	aspace = msm_gem_address_space_create(mmu, "gpu", SZ_16M,  in a2xx_create_address_space()
466 static u32 a2xx_get_rptr(struct msm_gpu *gpu, struct msm_ringbuffer *ring)  in a2xx_get_rptr()  argument
468 	ring->memptrs->rptr = gpu_read(gpu, REG_AXXX_CP_RB_RPTR);  in a2xx_get_rptr()
501 	struct msm_gpu *gpu;  in a2xx_gpu_init()  local
519 	gpu = &adreno_gpu->base;  in a2xx_gpu_init()
521 	gpu->perfcntrs = perfcntrs;  in a2xx_gpu_init()
522 	gpu->num_perfcntrs = ARRAY_SIZE(perfcntrs);  in a2xx_gpu_init()
535 	if (!gpu->aspace) {  in a2xx_gpu_init()
541 	return gpu;  in a2xx_gpu_init()