1090 static int g4x_plane_fifo_size(enum plane_id plane_id, int level)  in g4x_plane_fifo_size()
1119 static int g4x_fbc_fifo_size(int level)  in g4x_fbc_fifo_size()
1134 			  int level)  in g4x_compute_wm()
1194 				 int level, enum plane_id plane_id, u16 value)  in g4x_raw_plane_wm_set()
1210 			       int level, u16 value)  in g4x_raw_fbc_wm_set()
1240 	int level;  in g4x_raw_plane_wm_compute()  local
1307 				      enum plane_id plane_id, int level)  in g4x_raw_plane_wm_is_valid()
1315 				     int level)  in g4x_raw_crtc_wm_is_valid()
1329 			       struct g4x_wm_state *wm_state, int level)  in g4x_invalidate_wms()
1354 			       int level)  in g4x_compute_fbc_en()
1383 	int i, level;  in g4x_compute_pipe_wm()  local
1659 				int level)  in vlv_compute_wm_level()
1785 			       struct vlv_wm_state *wm_state, int level)  in vlv_invalidate_wms()
1813 				 int level, enum plane_id plane_id, u16 value)  in vlv_raw_plane_wm_set()
1836 	int level;  in vlv_raw_plane_wm_compute()  local
1872 				      enum plane_id plane_id, int level)  in vlv_raw_plane_wm_is_valid()
1882 static bool vlv_raw_crtc_wm_is_valid(const struct intel_crtc_state *crtc_state, int level)  in vlv_raw_crtc_wm_is_valid()
1906 	int level, ret, i;  in vlv_compute_pipe_wm()  local
2105 	int level;  in vlv_compute_intermediate_wm()  local
2663 		     int level, bool is_sprite)  in ilk_plane_wm_reg_max()
2680 ilk_cursor_wm_reg_max(const struct drm_i915_private *dev_priv, int level)  in ilk_cursor_wm_reg_max()
2698 				     int level,  in ilk_plane_wm_max()
2739 				      int level,  in ilk_cursor_wm_max()
2751 				    int level,  in ilk_compute_wm_maximums()
2763 					int level,  in ilk_compute_wm_reg_maximums()
2772 static bool ilk_validate_wm_level(int level,  in ilk_validate_wm_level()
2815 				 int level,  in ilk_compute_wm_level()
2856 		int level, max_level = ilk_wm_max_level(dev_priv);  in intel_read_wm_latency()  local
2997 	int level, max_level = ilk_wm_max_level(dev_priv);  in intel_print_wm_latency()  local
3027 	int level, max_level = ilk_wm_max_level(dev_priv);  in ilk_increase_wm_latency()  local
3152 	int level, max_level = ilk_wm_max_level(dev_priv), usable_level;  in ilk_compute_pipe_wm()  local
3228 	int level, max_level = ilk_wm_max_level(dev_priv);  in ilk_compute_intermediate_wm()  local
3278 			       int level,  in ilk_merge_wm_level()
3315 	int level, max_level = ilk_wm_max_level(dev_priv);  in ilk_wm_merge()  local
3373 				      int level)  in ilk_wm_lp_latency()
3387 	int level, wm_lp;  in ilk_compute_wm_results()  local
3453 	int level, max_level = ilk_wm_max_level(dev_priv);  in ilk_find_best_result()  local
3878 	int level, latency;  in skl_crtc_can_enable_sagv()  local
4262 	int level, max_level = ilk_wm_max_level(dev_priv);  in skl_cursor_allocation()  local
4782 		   int level)  in skl_plane_wm_level()
4808 	int level;  in skl_allocate_pipe_ddb()  local
5242 static bool skl_wm_has_lines(struct drm_i915_private *dev_priv, int level)  in skl_wm_has_lines()
5252 				 int level,  in skl_compute_plane_wm()
5384 	int level, max_level = ilk_wm_max_level(dev_priv);  in skl_compute_wm_levels()  local
5627 			       const struct skl_wm_level *level)  in skl_write_wm_level()
5645 	int level, max_level = ilk_wm_max_level(dev_priv);  in skl_write_plane_wm()  local
5685 	int level, max_level = ilk_wm_max_level(dev_priv);  in skl_write_cursor_wm()  local
5719 	int level, max_level = ilk_wm_max_level(dev_priv);  in skl_plane_wm_equals()  local
6218 static void skl_wm_level_from_reg_val(u32 val, struct skl_wm_level *level)  in skl_wm_level_from_reg_val()
6232 	int level, max_level;  in skl_pipe_wm_get_hw_state()  local
6316 		int level, max_level = ilk_wm_max_level(dev_priv);  in ilk_pipe_wm_get_hw_state()  local
6453 		int level, max_level;  in g4x_wm_get_hw_state()  local
6540 		int level;  in g4x_wm_sanitize()  local
6634 		int level;  in vlv_wm_get_hw_state()  local
6698 		int level;  in vlv_wm_sanitize()  local