Lines Matching +full:0 +full:x700
44 #define DPCD_SIZE 0x700
62 #define DPCD_SIZE 0x700
65 #define DP_SET_POWER 0x600
66 #define DP_SET_POWER_D0 0x1
67 #define AUX_NATIVE_WRITE 0x8
68 #define AUX_NATIVE_READ 0x9
70 #define AUX_NATIVE_REPLY_MASK (0x3 << 4)
71 #define AUX_NATIVE_REPLY_ACK (0x0 << 4)
72 #define AUX_NATIVE_REPLY_NAK (0x1 << 4)
73 #define AUX_NATIVE_REPLY_DEFER (0x2 << 4)
78 #define DPCD_REV 0x000
79 #define DPCD_MAX_LINK_RATE 0x001
80 #define DPCD_MAX_LANE_COUNT 0x002
82 #define DPCD_TRAINING_PATTERN_SET 0x102
83 #define DPCD_SINK_COUNT 0x200
84 #define DPCD_LANE0_1_STATUS 0x202
85 #define DPCD_LANE2_3_STATUS 0x203
86 #define DPCD_LANE_ALIGN_STATUS_UPDATED 0x204
87 #define DPCD_SINK_STATUS 0x205
90 #define DPCD_TRAINING_PATTERN_SET_MASK 0x03
91 #define DPCD_LINK_TRAINING_DISABLED 0x00
92 #define DPCD_TRAINING_PATTERN_1 0x01
93 #define DPCD_TRAINING_PATTERN_2 0x02
98 #define DPCD_LANES_CR_DONE 0x11
99 #define DPCD_LANES_EQ_DONE 0x22
100 #define DPCD_SYMBOL_LOCKED 0x44
102 #define DPCD_INTERLANE_ALIGN_DONE 0x01
104 #define DPCD_SINK_IN_SYNC 0x03
107 #define SBI_RESPONSE_MASK 0x3
108 #define SBI_RESPONSE_SHIFT 0x1
109 #define SBI_STAT_MASK 0x1
110 #define SBI_STAT_SHIFT 0x0
112 #define SBI_OPCODE_MASK (0xff << SBI_OPCODE_SHIFT)
118 #define SBI_ADDR_OFFSET_MASK (0xffff << SBI_ADDR_OFFSET_SHIFT)
131 PRIMARY_PLANE = 0,
143 GVT_CRT = 0,
189 return 0; in vgpu_edid_xres()
201 return 0; in vgpu_edid_yres()