35 u32 intel_sseu_get_subslices(const struct sseu_dev_info *sseu, u8 slice)  in intel_sseu_get_subslices()  argument
37 	int i, offset = slice * sseu->ss_stride;  in intel_sseu_get_subslices()
40 	GEM_BUG_ON(slice >= sseu->max_slices);  in intel_sseu_get_subslices()
49 void intel_sseu_set_subslices(struct sseu_dev_info *sseu, int slice,  in intel_sseu_set_subslices()  argument
52 	int offset = slice * sseu->ss_stride;  in intel_sseu_set_subslices()
58 intel_sseu_subslices_per_slice(const struct sseu_dev_info *sseu, u8 slice)  in intel_sseu_subslices_per_slice()  argument
60 	return hweight32(intel_sseu_get_subslices(sseu, slice));  in intel_sseu_subslices_per_slice()
63 static int sseu_eu_idx(const struct sseu_dev_info *sseu, int slice,  in sseu_eu_idx()  argument
68 	return slice * slice_stride + subslice * sseu->eu_stride;  in sseu_eu_idx()
71 static u16 sseu_get_eus(const struct sseu_dev_info *sseu, int slice,  in sseu_get_eus()  argument
74 	int i, offset = sseu_eu_idx(sseu, slice, subslice);  in sseu_get_eus()
84 static void sseu_set_eus(struct sseu_dev_info *sseu, int slice, int subslice,  in sseu_set_eus()  argument
87 	int i, offset = sseu_eu_idx(sseu, slice, subslice);  in sseu_set_eus()
160 	/* TGL only supports slice-level power gating */  in gen12_sseu_info_init()
337 	/* BXT has a single slice and at most 3 subslices. */  in gen9_sseu_info_init()
355 			/* skip disabled slice */  in gen9_sseu_info_init()
401 	 * SKL+ supports slice power gating on devices with more than  in gen9_sseu_info_init()
402 	 * one slice, and supports EU power gating on devices with  in gen9_sseu_info_init()
467 			/* skip disabled slice */  in bdw_sseu_info_init()
508 	 * BDW supports slice power gating on devices with more than  in bdw_sseu_info_init()
509 	 * one slice.  in bdw_sseu_info_init()
615 	 * slice/subslice/EU enablement prior to Gen9.  in intel_sseu_make_rpcs()
646 	 * When more than one slice is enabled, hardware ignores the subslice  in intel_sseu_make_rpcs()
653 	 * slice.  in intel_sseu_make_rpcs()
666 	 * slice/subslice/EU in a partially enabled state. We  in intel_sseu_make_rpcs()
723 	drm_printf(p, "slice total: %u, mask=%04x\n",  in intel_sseu_dump()
727 		drm_printf(p, "slice%d: %u subslices, mask=%08x\n",  in intel_sseu_dump()
733 	drm_printf(p, "has slice power gating: %s\n",  in intel_sseu_dump()
751 		drm_printf(p, "slice%d: %u subslice(s) (0x%08x):\n",  in intel_sseu_print_topology()