160 	/* TGL only supports slice-level power gating */  in gen12_sseu_info_init()
186 	/* ICL has no power gating restrictions. */  in gen11_sseu_info_init()
263 	/* No restrictions on Power Gating */  in gen10_sseu_info_init()
315 	 * CHV supports subslice power gating on devices with more than  in cherryview_sseu_info_init()
316 	 * one subslice, and supports EU power gating on devices with  in cherryview_sseu_info_init()
401 	 * SKL+ supports slice power gating on devices with more than  in gen9_sseu_info_init()
402 	 * one slice, and supports EU power gating on devices with  in gen9_sseu_info_init()
404 	 * power gating on devices with more than one subslice, and  in gen9_sseu_info_init()
405 	 * supports EU power gating on devices with more than one EU  in gen9_sseu_info_init()
508 	 * BDW supports slice power gating on devices with more than  in bdw_sseu_info_init()
665 	 * Starting in Gen9, render power gating can leave  in intel_sseu_make_rpcs()
733 	drm_printf(p, "has slice power gating: %s\n",  in intel_sseu_dump()
735 	drm_printf(p, "has subslice power gating: %s\n",  in intel_sseu_dump()
737 	drm_printf(p, "has EU power gating: %s\n", yesno(sseu->has_eu_pg));  in intel_sseu_dump()