Lines Matching full:engine
44 struct intel_engine_cs *engine = rq->engine; in engine_skip_context() local
50 lockdep_assert_held(&engine->active.lock); in engine_skip_context()
51 list_for_each_entry_continue(rq, &engine->active.requests, sched.link) in engine_skip_context()
325 struct intel_engine_cs *engine; in gen6_reset_engines() local
334 for_each_engine_masked(engine, gt, engine_mask, tmp) { in gen6_reset_engines()
335 GEM_BUG_ON(engine->id >= ARRAY_SIZE(hw_engine_mask)); in gen6_reset_engines()
336 hw_mask |= hw_engine_mask[engine->id]; in gen6_reset_engines()
343 static int gen11_lock_sfc(struct intel_engine_cs *engine, u32 *hw_mask) in gen11_lock_sfc() argument
345 struct intel_uncore *uncore = engine->uncore; in gen11_lock_sfc()
346 u8 vdbox_sfc_access = engine->gt->info.vdbox_sfc_access; in gen11_lock_sfc()
354 switch (engine->class) { in gen11_lock_sfc()
356 if ((BIT(engine->instance) & vdbox_sfc_access) == 0) in gen11_lock_sfc()
359 sfc_forced_lock = GEN11_VCS_SFC_FORCED_LOCK(engine); in gen11_lock_sfc()
362 sfc_forced_lock_ack = GEN11_VCS_SFC_LOCK_STATUS(engine); in gen11_lock_sfc()
365 sfc_usage = GEN11_VCS_SFC_LOCK_STATUS(engine); in gen11_lock_sfc()
367 sfc_reset_bit = GEN11_VCS_SFC_RESET_BIT(engine->instance); in gen11_lock_sfc()
371 sfc_forced_lock = GEN11_VECS_SFC_FORCED_LOCK(engine); in gen11_lock_sfc()
374 sfc_forced_lock_ack = GEN11_VECS_SFC_LOCK_ACK(engine); in gen11_lock_sfc()
377 sfc_usage = GEN11_VECS_SFC_USAGE(engine); in gen11_lock_sfc()
379 sfc_reset_bit = GEN11_VECS_SFC_RESET_BIT(engine->instance); in gen11_lock_sfc()
387 * If the engine is using a SFC, tell the engine that a software reset in gen11_lock_sfc()
388 * is going to happen. The engine will then try to force lock the SFC. in gen11_lock_sfc()
389 * If SFC ends up being locked to the engine we want to reset, we have in gen11_lock_sfc()
409 drm_dbg(&engine->i915->drm, in gen11_lock_sfc()
418 static void gen11_unlock_sfc(struct intel_engine_cs *engine) in gen11_unlock_sfc() argument
420 struct intel_uncore *uncore = engine->uncore; in gen11_unlock_sfc()
421 u8 vdbox_sfc_access = engine->gt->info.vdbox_sfc_access; in gen11_unlock_sfc()
425 switch (engine->class) { in gen11_unlock_sfc()
427 if ((BIT(engine->instance) & vdbox_sfc_access) == 0) in gen11_unlock_sfc()
430 sfc_forced_lock = GEN11_VCS_SFC_FORCED_LOCK(engine); in gen11_unlock_sfc()
435 sfc_forced_lock = GEN11_VECS_SFC_FORCED_LOCK(engine); in gen11_unlock_sfc()
460 struct intel_engine_cs *engine; in gen11_reset_engines() local
469 for_each_engine_masked(engine, gt, engine_mask, tmp) { in gen11_reset_engines()
470 GEM_BUG_ON(engine->id >= ARRAY_SIZE(hw_engine_mask)); in gen11_reset_engines()
471 hw_mask |= hw_engine_mask[engine->id]; in gen11_reset_engines()
472 ret = gen11_lock_sfc(engine, &hw_mask); in gen11_reset_engines()
488 for_each_engine_masked(engine, gt, engine_mask, tmp) in gen11_reset_engines()
489 gen11_unlock_sfc(engine); in gen11_reset_engines()
494 static int gen8_engine_reset_prepare(struct intel_engine_cs *engine) in gen8_engine_reset_prepare() argument
496 struct intel_uncore *uncore = engine->uncore; in gen8_engine_reset_prepare()
497 const i915_reg_t reg = RING_RESET_CTL(engine->mmio_base); in gen8_engine_reset_prepare()
524 drm_err(&engine->i915->drm, in gen8_engine_reset_prepare()
526 engine->name, request, in gen8_engine_reset_prepare()
532 static void gen8_engine_reset_cancel(struct intel_engine_cs *engine) in gen8_engine_reset_cancel() argument
534 intel_uncore_write_fw(engine->uncore, in gen8_engine_reset_cancel()
535 RING_RESET_CTL(engine->mmio_base), in gen8_engine_reset_cancel()
543 struct intel_engine_cs *engine; in gen8_reset_engines() local
548 for_each_engine_masked(engine, gt, engine_mask, tmp) { in gen8_reset_engines()
549 ret = gen8_engine_reset_prepare(engine); in gen8_reset_engines()
574 for_each_engine_masked(engine, gt, engine_mask, tmp) in gen8_reset_engines()
575 gen8_engine_reset_cancel(engine); in gen8_reset_engines()
675 static void reset_prepare_engine(struct intel_engine_cs *engine) in reset_prepare_engine() argument
678 * During the reset sequence, we must prevent the engine from in reset_prepare_engine()
680 * the engine, if it does enter RC6 during the reset, the state in reset_prepare_engine()
684 intel_uncore_forcewake_get(engine->uncore, FORCEWAKE_ALL); in reset_prepare_engine()
685 if (engine->reset.prepare) in reset_prepare_engine()
686 engine->reset.prepare(engine); in reset_prepare_engine()
722 struct intel_engine_cs *engine; in reset_prepare() local
726 for_each_engine(engine, gt, id) { in reset_prepare()
727 if (intel_engine_pm_get_if_awake(engine)) in reset_prepare()
728 awake |= engine->mask; in reset_prepare()
729 reset_prepare_engine(engine); in reset_prepare()
744 struct intel_engine_cs *engine; in gt_reset() local
756 for_each_engine(engine, gt, id) in gt_reset()
757 __intel_engine_reset(engine, stalled_mask & engine->mask); in gt_reset()
764 static void reset_finish_engine(struct intel_engine_cs *engine) in reset_finish_engine() argument
766 if (engine->reset.finish) in reset_finish_engine()
767 engine->reset.finish(engine); in reset_finish_engine()
768 intel_uncore_forcewake_put(engine->uncore, FORCEWAKE_ALL); in reset_finish_engine()
770 intel_engine_signal_breadcrumbs(engine); in reset_finish_engine()
775 struct intel_engine_cs *engine; in reset_finish() local
778 for_each_engine(engine, gt, id) { in reset_finish()
779 reset_finish_engine(engine); in reset_finish()
780 if (awake & engine->mask) in reset_finish()
781 intel_engine_pm_put(engine); in reset_finish()
787 struct intel_engine_cs *engine = request->engine; in nop_submit_request() local
793 spin_lock_irqsave(&engine->active.lock, flags); in nop_submit_request()
796 spin_unlock_irqrestore(&engine->active.lock, flags); in nop_submit_request()
798 intel_engine_signal_breadcrumbs(engine); in nop_submit_request()
803 struct intel_engine_cs *engine; in __intel_gt_set_wedged() local
823 for_each_engine(engine, gt, id) in __intel_gt_set_wedged()
824 engine->submit_request = nop_submit_request; in __intel_gt_set_wedged()
835 for_each_engine(engine, gt, id) in __intel_gt_set_wedged()
836 if (engine->reset.cancel) in __intel_gt_set_wedged()
837 engine->reset.cancel(engine); in __intel_gt_set_wedged()
856 struct intel_engine_cs *engine; in intel_gt_set_wedged() local
860 for_each_engine(engine, gt, id) { in intel_gt_set_wedged()
861 if (intel_engine_is_idle(engine)) in intel_gt_set_wedged()
864 intel_engine_dump(engine, &p, "%s\n", engine->name); in intel_gt_set_wedged()
943 * engine->submit_request() as we swap over. So unlike installing in __intel_gt_unset_wedged()
987 struct intel_engine_cs *engine; in resume() local
991 for_each_engine(engine, gt, id) { in resume()
992 ret = intel_engine_resume(engine); in resume()
1107 static inline int intel_gt_reset_engine(struct intel_engine_cs *engine) in intel_gt_reset_engine() argument
1109 return __intel_gt_reset(engine->gt, engine->mask); in intel_gt_reset_engine()
1113 * intel_engine_reset - reset GPU engine to recover from a hang
1114 * @engine: engine to reset
1117 * Reset a specific GPU engine. Useful if a hang is detected.
1122 * - reset engine (which will force the engine to idle)
1123 * - re-init/configure engine
1125 int intel_engine_reset(struct intel_engine_cs *engine, const char *msg) in intel_engine_reset() argument
1127 struct intel_gt *gt = engine->gt; in intel_engine_reset()
1128 bool uses_guc = intel_engine_in_guc_submission_mode(engine); in intel_engine_reset()
1131 ENGINE_TRACE(engine, "flags=%lx\n", gt->reset.flags); in intel_engine_reset()
1132 GEM_BUG_ON(!test_bit(I915_RESET_ENGINE + engine->id, >->reset.flags)); in intel_engine_reset()
1134 if (!intel_engine_pm_get_if_awake(engine)) in intel_engine_reset()
1137 reset_prepare_engine(engine); in intel_engine_reset()
1140 drm_notice(&engine->i915->drm, in intel_engine_reset()
1141 "Resetting %s for %s\n", engine->name, msg); in intel_engine_reset()
1142 atomic_inc(&engine->i915->gpu_error.reset_engine_count[engine->uabi_class]); in intel_engine_reset()
1145 ret = intel_gt_reset_engine(engine); in intel_engine_reset()
1147 ret = intel_guc_reset_engine(&engine->gt->uc.guc, engine); in intel_engine_reset()
1151 uses_guc ? "GuC " : "", engine->name, ret); in intel_engine_reset()
1160 __intel_engine_reset(engine, true); in intel_engine_reset()
1163 * The engine and its registers (and workarounds in case of render) in intel_engine_reset()
1167 ret = intel_engine_resume(engine); in intel_engine_reset()
1170 intel_engine_cancel_stop_cs(engine); in intel_engine_reset()
1171 reset_finish_engine(engine); in intel_engine_reset()
1172 intel_engine_pm_put_async(engine); in intel_engine_reset()
1225 struct intel_engine_cs *engine; in intel_gt_handle_error() local
1258 * Try engine reset when available. We fall back to full reset if in intel_gt_handle_error()
1262 for_each_engine_masked(engine, gt, engine_mask, tmp) { in intel_gt_handle_error()
1264 if (test_and_set_bit(I915_RESET_ENGINE + engine->id, in intel_gt_handle_error()
1268 if (intel_engine_reset(engine, msg) == 0) in intel_gt_handle_error()
1269 engine_mask &= ~engine->mask; in intel_gt_handle_error()
1271 clear_and_wake_up_bit(I915_RESET_ENGINE + engine->id, in intel_gt_handle_error()
1289 /* Prevent any other reset-engine attempt. */ in intel_gt_handle_error()
1290 for_each_engine(engine, gt, tmp) { in intel_gt_handle_error()
1291 while (test_and_set_bit(I915_RESET_ENGINE + engine->id, in intel_gt_handle_error()
1294 I915_RESET_ENGINE + engine->id, in intel_gt_handle_error()
1300 for_each_engine(engine, gt, tmp) in intel_gt_handle_error()
1301 clear_bit_unlock(I915_RESET_ENGINE + engine->id, in intel_gt_handle_error()