1 // SPDX-License-Identifier: MIT
23 	struct intel_gt *gt = m->private;  in fw_domains_show()
24 	struct intel_uncore *uncore = gt->uncore;  in fw_domains_show()
29 		   uncore->user_forcewake_count);  in fw_domains_show()
33 			   intel_uncore_forcewake_domain_to_str(fw_domain->id),  in fw_domains_show()
34 			   READ_ONCE(fw_domain->wake_count));  in fw_domains_show()
44 	struct intel_gt *gt = m->private;  in print_rc6_res()
47 	with_intel_runtime_pm(gt->uncore->rpm, wakeref)  in print_rc6_res()
49 			   intel_uncore_read(gt->uncore, reg),  in print_rc6_res()
50 			   intel_rc6_residency_us(&gt->rc6, reg));  in print_rc6_res()
55 	struct intel_gt *gt = m->private;  in vlv_drpc()
56 	struct intel_uncore *uncore = gt->uncore;  in vlv_drpc()
62 	seq_printf(m, "RC6 Enabled: %s\n",  in vlv_drpc()
78 	struct intel_gt *gt = m->private;  in gen6_drpc()
79 	struct drm_i915_private *i915 = gt->i915;  in gen6_drpc()
80 	struct intel_uncore *uncore = gt->uncore;  in gen6_drpc()
98 	seq_printf(m, "RC1e Enabled: %s\n",  in gen6_drpc()
100 	seq_printf(m, "RC6 Enabled: %s\n",  in gen6_drpc()
103 		seq_printf(m, "Render Well Gating Enabled: %s\n",  in gen6_drpc()
105 		seq_printf(m, "Media Well Gating Enabled: %s\n",  in gen6_drpc()
108 	seq_printf(m, "Deep RC6 Enabled: %s\n",  in gen6_drpc()
110 	seq_printf(m, "Deepest RC6 Enabled: %s\n",  in gen6_drpc()
166 	struct intel_gt *gt = m->private;  in ilk_drpc()
167 	struct intel_uncore *uncore = gt->uncore;  in ilk_drpc()
179 	seq_printf(m, "HW control enabled: %s\n",  in ilk_drpc()
181 	seq_printf(m, "SW control enabled: %s\n",  in ilk_drpc()
187 	seq_printf(m, "Max P-state: P%d\n",  in ilk_drpc()
189 	seq_printf(m, "Min P-state: P%d\n", (rgvmodectl & MEMMODE_FMIN_MASK));  in ilk_drpc()
192 	seq_printf(m, "Render standby enabled: %s\n",  in ilk_drpc()
224 	struct intel_gt *gt = m->private;  in drpc_show()
225 	struct drm_i915_private *i915 = gt->i915;  in drpc_show()
227 	int err = -ENODEV;  in drpc_show()
229 	with_intel_runtime_pm(gt->uncore->rpm, wakeref) {  in drpc_show()
244 	struct intel_gt *gt = m->private;  in frequency_show()
245 	struct drm_i915_private *i915 = gt->i915;  in frequency_show()
246 	struct intel_uncore *uncore = gt->uncore;  in frequency_show()
247 	struct intel_rps *rps = &gt->rps;  in frequency_show()
250 	wakeref = intel_runtime_pm_get(uncore->rpm);  in frequency_show()
256 		seq_printf(m, "Requested P-state: %d\n", (rgvswctl >> 8) & 0xf);  in frequency_show()
260 		seq_printf(m, "Current P-state: %d\n",  in frequency_show()
268 		seq_printf(m, "HW control enabled: %s\n",  in frequency_show()
270 		seq_printf(m, "SW control enabled: %s\n",  in frequency_show()
279 		seq_printf(m, "DDR freq: %d MHz\n", i915->mem_freq);  in frequency_show()
285 			   intel_gpu_freq(rps, rps->cur_freq));  in frequency_show()
288 			   intel_gpu_freq(rps, rps->max_freq));  in frequency_show()
291 			   intel_gpu_freq(rps, rps->min_freq));  in frequency_show()
294 			   intel_gpu_freq(rps, rps->idle_freq));  in frequency_show()
297 			   intel_gpu_freq(rps, rps->efficient_freq));  in frequency_show()
380 		seq_printf(m, "HW control enabled: %s\n",  in frequency_show()
382 		seq_printf(m, "SW control enabled: %s\n",  in frequency_show()
392 			   rps->pm_intrmsk_mbz);  in frequency_show()
394 		seq_printf(m, "Render p-state ratio: %d\n",  in frequency_show()
396 		seq_printf(m, "Render p-state VID: %d\n",  in frequency_show()
398 		seq_printf(m, "Render p-state limit: %d\n",  in frequency_show()
414 			   rps->power.up_threshold);  in frequency_show()
430 			   rps->power.down_threshold);  in frequency_show()
453 		seq_printf(m, "Max non-overclocked (RP0) frequency: %dMHz\n",  in frequency_show()
456 			   intel_gpu_freq(rps, rps->max_freq));  in frequency_show()
459 			   intel_gpu_freq(rps, rps->cur_freq));  in frequency_show()
462 			   intel_gpu_freq(rps, rps->idle_freq));  in frequency_show()
464 			   intel_gpu_freq(rps, rps->min_freq));  in frequency_show()
466 			   intel_gpu_freq(rps, rps->boost_freq));  in frequency_show()
468 			   intel_gpu_freq(rps, rps->max_freq));  in frequency_show()
471 			   intel_gpu_freq(rps, rps->efficient_freq));  in frequency_show()
473 		seq_puts(m, "no P-state info available\n");  in frequency_show()
476 	seq_printf(m, "Current CD clock frequency: %d kHz\n", i915->cdclk.hw.cdclk);  in frequency_show()
477 	seq_printf(m, "Max CD clock frequency: %d kHz\n", i915->max_cdclk_freq);  in frequency_show()
478 	seq_printf(m, "Max pixel clock frequency: %d kHz\n", i915->max_dotclk_freq);  in frequency_show()
480 	intel_runtime_pm_put(uncore->rpm, wakeref);  in frequency_show()
488 	struct intel_gt *gt = m->private;  in llc_show()
489 	struct drm_i915_private *i915 = gt->i915;  in llc_show()
491 	struct intel_rps *rps = &gt->rps;  in llc_show()
498 		   i915->edram_size_mb);  in llc_show()
500 	min_gpu_freq = rps->min_freq;  in llc_show()
501 	max_gpu_freq = rps->max_freq;  in llc_show()
510 	wakeref = intel_runtime_pm_get(gt->uncore->rpm);  in llc_show()
525 	intel_runtime_pm_put(gt->uncore->rpm, wakeref);  in llc_show()
534 	return HAS_LLC(gt->i915);  in llc_eval()
541 	static const char * const strings[] = {  in rps_power_to_str()  local
547 	if (power >= ARRAY_SIZE(strings) || !strings[power])  in rps_power_to_str()
550 	return strings[power];  in rps_power_to_str()
555 	struct intel_gt *gt = m->private;  in rps_boost_show()
556 	struct drm_i915_private *i915 = gt->i915;  in rps_boost_show()
557 	struct intel_rps *rps = &gt->rps;  in rps_boost_show()
559 	seq_printf(m, "RPS enabled? %s\n", yesno(intel_rps_is_enabled(rps)));  in rps_boost_show()
561 	seq_printf(m, "GPU busy? %s\n", yesno(gt->awake));  in rps_boost_show()
563 		   atomic_read(&rps->num_waiters));  in rps_boost_show()
564 	seq_printf(m, "Interactive? %d\n", READ_ONCE(rps->power.interactive));  in rps_boost_show()
566 		   intel_gpu_freq(rps, rps->cur_freq),  in rps_boost_show()
569 		   intel_gpu_freq(rps, rps->min_freq),  in rps_boost_show()
570 		   intel_gpu_freq(rps, rps->min_freq_softlimit),  in rps_boost_show()
571 		   intel_gpu_freq(rps, rps->max_freq_softlimit),  in rps_boost_show()
572 		   intel_gpu_freq(rps, rps->max_freq));  in rps_boost_show()
574 		   intel_gpu_freq(rps, rps->idle_freq),  in rps_boost_show()
575 		   intel_gpu_freq(rps, rps->efficient_freq),  in rps_boost_show()
576 		   intel_gpu_freq(rps, rps->boost_freq));  in rps_boost_show()
578 	seq_printf(m, "Wait boosts: %d\n", atomic_read(&rps->boosts));  in rps_boost_show()
581 		struct intel_uncore *uncore = gt->uncore;  in rps_boost_show()
593 			   rps_power_to_str(rps->power.mode));  in rps_boost_show()
596 			   rps->power.up_threshold);  in rps_boost_show()
599 			   rps->power.down_threshold);  in rps_boost_show()
611 	return HAS_RPS(gt->i915);  in rps_eval()