Lines Matching +full:mode +full:- +full:xxx
78 struct drm_encoder *encoder = &intel_dsi->base.base; in vlv_dsi_wait_for_fifo_empty()
79 struct drm_device *dev = encoder->dev; in vlv_dsi_wait_for_fifo_empty()
88 drm_err(&dev_priv->drm, "DPI FIFOs are not empty\n"); in vlv_dsi_wait_for_fifo_empty()
100 for (j = 0; j < min_t(u32, len - i, 4); j++) in write_data()
116 for (j = 0; j < min_t(u32, len - i, 4); j++) in read_data()
125 struct drm_device *dev = intel_dsi_host->intel_dsi->base.base.dev; in intel_dsi_host_transfer()
127 enum port port = intel_dsi_host->port; in intel_dsi_host_transfer()
141 if (msg->flags & MIPI_DSI_MSG_USE_LPM) { in intel_dsi_host_transfer()
157 drm_err(&dev_priv->drm, in intel_dsi_host_transfer()
164 if (msg->rx_len) { in intel_dsi_host_transfer()
171 drm_err(&dev_priv->drm, in intel_dsi_host_transfer()
178 /* ->rx_len is set only for reads */ in intel_dsi_host_transfer()
179 if (msg->rx_len) { in intel_dsi_host_transfer()
183 drm_err(&dev_priv->drm, in intel_dsi_host_transfer()
186 read_data(dev_priv, data_reg, msg->rx_buf, msg->rx_len); in intel_dsi_host_transfer()
189 /* XXX: fix for reads and writes */ in intel_dsi_host_transfer()
212 * send a video mode command
214 * XXX: commands with data in MIPI_DPI_DATA?
219 struct drm_encoder *encoder = &intel_dsi->base.base; in dpi_send_cmd()
220 struct drm_device *dev = encoder->dev; in dpi_send_cmd()
224 /* XXX: pipe, hs */ in dpi_send_cmd()
233 /* XXX: old code skips write if control unchanged */ in dpi_send_cmd()
235 drm_dbg_kms(&dev_priv->drm, in dpi_send_cmd()
242 drm_err(&dev_priv->drm, in dpi_send_cmd()
243 "Video mode command 0x%08x send failed.\n", cmd); in dpi_send_cmd()
266 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); in intel_dsi_compute_config()
269 struct intel_connector *intel_connector = intel_dsi->attached_connector; in intel_dsi_compute_config()
270 const struct drm_display_mode *fixed_mode = intel_connector->panel.fixed_mode; in intel_dsi_compute_config()
271 struct drm_display_mode *adjusted_mode = &pipe_config->hw.adjusted_mode; in intel_dsi_compute_config()
274 drm_dbg_kms(&dev_priv->drm, "\n"); in intel_dsi_compute_config()
275 pipe_config->output_format = INTEL_OUTPUT_FORMAT_RGB; in intel_dsi_compute_config()
288 if (adjusted_mode->flags & DRM_MODE_FLAG_DBLSCAN) in intel_dsi_compute_config()
289 return -EINVAL; in intel_dsi_compute_config()
291 /* DSI uses short packets for sync events, so clear mode flags for DSI */ in intel_dsi_compute_config()
292 adjusted_mode->flags = 0; in intel_dsi_compute_config()
294 if (intel_dsi->pixel_format == MIPI_DSI_FMT_RGB888) in intel_dsi_compute_config()
295 pipe_config->pipe_bpp = 24; in intel_dsi_compute_config()
297 pipe_config->pipe_bpp = 18; in intel_dsi_compute_config()
301 pipe_config->mode_flags |= in intel_dsi_compute_config()
305 if (intel_dsi->ports == BIT(PORT_C)) in intel_dsi_compute_config()
306 pipe_config->cpu_transcoder = TRANSCODER_DSI_C; in intel_dsi_compute_config()
308 pipe_config->cpu_transcoder = TRANSCODER_DSI_A; in intel_dsi_compute_config()
312 return -EINVAL; in intel_dsi_compute_config()
316 return -EINVAL; in intel_dsi_compute_config()
319 pipe_config->clock_set = true; in intel_dsi_compute_config()
326 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); in glk_dsi_enable_io()
332 /* Set the MIPI mode in glk_dsi_enable_io()
336 for_each_dsi_port(port, intel_dsi->ports) { in glk_dsi_enable_io()
348 for_each_dsi_port(port, intel_dsi->ports) { in glk_dsi_enable_io()
358 for_each_dsi_port(port, intel_dsi->ports) { in glk_dsi_enable_io()
361 drm_err(&dev_priv->drm, "MIPIO port is powergated\n"); in glk_dsi_enable_io()
365 for_each_dsi_port(port, intel_dsi->ports) { in glk_dsi_enable_io()
375 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); in glk_dsi_device_ready()
381 for_each_dsi_port(port, intel_dsi->ports) { in glk_dsi_device_ready()
384 drm_err(&dev_priv->drm, "PHY is not ON\n"); in glk_dsi_device_ready()
393 for_each_dsi_port(port, intel_dsi->ports) { in glk_dsi_device_ready()
410 drm_err(&dev_priv->drm, "ULPS not active\n"); in glk_dsi_device_ready()
418 /* Enter Normal Mode */ in glk_dsi_device_ready()
431 for_each_dsi_port(port, intel_dsi->ports) { in glk_dsi_device_ready()
434 drm_err(&dev_priv->drm, in glk_dsi_device_ready()
439 for_each_dsi_port(port, intel_dsi->ports) { in glk_dsi_device_ready()
442 drm_err(&dev_priv->drm, in glk_dsi_device_ready()
443 "D-PHY not entering LP-11 state\n"); in glk_dsi_device_ready()
449 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); in bxt_dsi_device_ready()
454 drm_dbg_kms(&dev_priv->drm, "\n"); in bxt_dsi_device_ready()
457 for_each_dsi_port(port, intel_dsi->ports) { in bxt_dsi_device_ready()
465 for_each_dsi_port(port, intel_dsi->ports) { in bxt_dsi_device_ready()
477 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); in vlv_dsi_device_ready()
482 drm_dbg_kms(&dev_priv->drm, "\n"); in vlv_dsi_device_ready()
493 for_each_dsi_port(port, intel_dsi->ports) { in vlv_dsi_device_ready()
520 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); in intel_dsi_device_ready()
532 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); in glk_dsi_enter_low_power_mode()
538 for_each_dsi_port(port, intel_dsi->ports) { in glk_dsi_enter_low_power_mode()
546 for_each_dsi_port(port, intel_dsi->ports) { in glk_dsi_enter_low_power_mode()
549 drm_err(&dev_priv->drm, "PHY is not turning OFF\n"); in glk_dsi_enter_low_power_mode()
553 for_each_dsi_port(port, intel_dsi->ports) { in glk_dsi_enter_low_power_mode()
556 drm_err(&dev_priv->drm, in glk_dsi_enter_low_power_mode()
563 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); in glk_dsi_disable_mipi_io()
574 for_each_dsi_port(port, intel_dsi->ports) { in glk_dsi_disable_mipi_io()
577 drm_err(&dev_priv->drm, "PHY is not turning OFF\n"); in glk_dsi_disable_mipi_io()
580 /* Clear MIPI mode */ in glk_dsi_disable_mipi_io()
581 for_each_dsi_port(port, intel_dsi->ports) { in glk_dsi_disable_mipi_io()
596 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); in vlv_dsi_clear_device_ready()
600 drm_dbg_kms(&dev_priv->drm, "\n"); in vlv_dsi_clear_device_ready()
601 for_each_dsi_port(port, intel_dsi->ports) { in vlv_dsi_clear_device_ready()
620 * On VLV/CHV, wait till Clock lanes are in LP-00 state for MIPI in vlv_dsi_clear_device_ready()
626 drm_err(&dev_priv->drm, "DSI LP not going Low\n"); in vlv_dsi_clear_device_ready()
641 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); in intel_dsi_port_enable()
642 struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc); in intel_dsi_port_enable()
646 if (intel_dsi->dual_link == DSI_DUAL_LINK_FRONT_BACK) { in intel_dsi_port_enable()
649 for_each_dsi_port(port, intel_dsi->ports) { in intel_dsi_port_enable()
653 intel_dsi->pixel_overlap << in intel_dsi_port_enable()
661 intel_dsi->pixel_overlap << in intel_dsi_port_enable()
667 for_each_dsi_port(port, intel_dsi->ports) { in intel_dsi_port_enable()
677 if (intel_dsi->ports == (BIT(PORT_A) | BIT(PORT_C))) { in intel_dsi_port_enable()
678 temp |= (intel_dsi->dual_link - 1) in intel_dsi_port_enable()
683 temp |= crtc->pipe ? in intel_dsi_port_enable()
688 if (intel_dsi->pixel_format != MIPI_DSI_FMT_RGB888) in intel_dsi_port_enable()
699 struct drm_device *dev = encoder->base.dev; in intel_dsi_port_disable()
704 for_each_dsi_port(port, intel_dsi->ports) { in intel_dsi_port_disable()
709 /* de-assert ip_tg_enable signal */ in intel_dsi_port_disable()
731 * v2 video mode seq v3 video mode seq command mode seq
732 * - power on - MIPIPanelPowerOn - power on
733 * - wait t1+t2 - wait t1+t2
734 * - MIPIDeassertResetPin - MIPIDeassertResetPin - MIPIDeassertResetPin
735 * - io lines to lp-11 - io lines to lp-11 - io lines to lp-11
736 * - MIPISendInitialDcsCmds - MIPISendInitialDcsCmds - MIPISendInitialDcsCmds
737 * - MIPITearOn
738 * - MIPIDisplayOn
739 * - turn on DPI - turn on DPI - set pipe to dsr mode
740 * - MIPIDisplayOn - MIPIDisplayOn
741 * - wait t5 - wait t5
742 * - backlight on - MIPIBacklightOn - backlight on
744 * - backlight off - MIPIBacklightOff - backlight off
745 * - wait t6 - wait t6
746 * - MIPIDisplayOff
747 * - turn off DPI - turn off DPI - disable pipe dsr mode
748 * - MIPITearOff
749 * - MIPIDisplayOff - MIPIDisplayOff
750 * - io lines to lp-00 - io lines to lp-00 - io lines to lp-00
751 * - MIPIAssertResetPin - MIPIAssertResetPin - MIPIAssertResetPin
752 * - wait t3 - wait t3
753 * - power off - MIPIPanelPowerOff - power off
754 * - wait t4 - wait t4
767 struct drm_crtc *crtc = pipe_config->uapi.crtc; in intel_dsi_pre_enable()
768 struct drm_i915_private *dev_priv = to_i915(crtc->dev); in intel_dsi_pre_enable()
770 enum pipe pipe = intel_crtc->pipe; in intel_dsi_pre_enable()
775 drm_dbg_kms(&dev_priv->drm, "\n"); in intel_dsi_pre_enable()
815 intel_dsi_msleep(intel_dsi, intel_dsi->panel_on_delay); in intel_dsi_pre_enable()
828 /* Put device in ready state (LP-11) */ in intel_dsi_pre_enable()
835 /* Send initialization commands in LP mode */ in intel_dsi_pre_enable()
838 /* Enable port in pre-enable phase itself because as per hw team in intel_dsi_pre_enable()
841 for_each_dsi_port(port, intel_dsi->ports) in intel_dsi_pre_enable()
847 msleep(20); /* XXX */ in intel_dsi_pre_enable()
848 for_each_dsi_port(port, intel_dsi->ports) in intel_dsi_pre_enable()
866 drm_WARN_ON(state->base.dev, crtc_state->has_pch_encoder); in bxt_dsi_enable()
880 struct drm_i915_private *i915 = to_i915(encoder->base.dev); in intel_dsi_disable()
884 drm_dbg_kms(&i915->drm, "\n"); in intel_dsi_disable()
895 /* Send Shutdown command to the panel in LP mode */ in intel_dsi_disable()
896 for_each_dsi_port(port, intel_dsi->ports) in intel_dsi_disable()
904 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); in intel_dsi_clear_device_ready()
917 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); in intel_dsi_post_disable()
922 drm_dbg_kms(&dev_priv->drm, "\n"); in intel_dsi_post_disable()
931 for_each_dsi_port(port, intel_dsi->ports) in intel_dsi_post_disable()
948 /* Transition to LP-00 */ in intel_dsi_post_disable()
978 intel_dsi_msleep(intel_dsi, intel_dsi->panel_off_delay); in intel_dsi_post_disable()
985 intel_dsi_msleep(intel_dsi, intel_dsi->panel_pwr_cycle_delay); in intel_dsi_post_disable()
991 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); in intel_dsi_get_hw_state()
997 drm_dbg_kms(&dev_priv->drm, "\n"); in intel_dsi_get_hw_state()
1000 encoder->power_domain); in intel_dsi_get_hw_state()
1012 /* XXX: this only works for one DSI output */ in intel_dsi_get_hw_state()
1013 for_each_dsi_port(port, intel_dsi->ports) { in intel_dsi_get_hw_state()
1027 /* Try command mode if video mode not enabled */ in intel_dsi_get_hw_state()
1045 if (drm_WARN_ON(&dev_priv->drm, tmp > PIPE_C)) in intel_dsi_get_hw_state()
1058 intel_display_power_put(dev_priv, encoder->power_domain, wakeref); in intel_dsi_get_hw_state()
1066 struct drm_device *dev = encoder->base.dev; in bxt_dsi_get_pipe_config()
1069 &pipe_config->hw.adjusted_mode; in bxt_dsi_get_pipe_config()
1071 struct intel_crtc *crtc = to_intel_crtc(pipe_config->uapi.crtc); in bxt_dsi_get_pipe_config()
1073 unsigned int lane_count = intel_dsi->lane_count; in bxt_dsi_get_pipe_config()
1082 adjusted_mode_sw = &crtc->config->hw.adjusted_mode; in bxt_dsi_get_pipe_config()
1085 * Atleast one port is active as encoder->get_config called only if in bxt_dsi_get_pipe_config()
1086 * encoder->get_hw_state() returns true. in bxt_dsi_get_pipe_config()
1088 for_each_dsi_port(port, intel_dsi->ports) { in bxt_dsi_get_pipe_config()
1097 pipe_config->pipe_bpp = bdw_get_pipemisc_bpp(crtc); in bxt_dsi_get_pipe_config()
1100 pipe_config->mode_flags |= in bxt_dsi_get_pipe_config()
1104 adjusted_mode->crtc_hdisplay = in bxt_dsi_get_pipe_config()
1107 adjusted_mode->crtc_vdisplay = in bxt_dsi_get_pipe_config()
1110 adjusted_mode->crtc_vtotal = in bxt_dsi_get_pipe_config()
1114 hactive = adjusted_mode->crtc_hdisplay; in bxt_dsi_get_pipe_config()
1118 * Meaningful for video mode non-burst sync pulse mode only, in bxt_dsi_get_pipe_config()
1119 * can be zero for non-burst sync events and burst modes in bxt_dsi_get_pipe_config()
1126 intel_dsi->burst_mode_ratio); in bxt_dsi_get_pipe_config()
1128 intel_dsi->burst_mode_ratio); in bxt_dsi_get_pipe_config()
1130 intel_dsi->burst_mode_ratio); in bxt_dsi_get_pipe_config()
1132 if (intel_dsi->dual_link) { in bxt_dsi_get_pipe_config()
1143 adjusted_mode->crtc_htotal = hactive + hfp + hsync + hbp; in bxt_dsi_get_pipe_config()
1144 adjusted_mode->crtc_hsync_start = hfp + adjusted_mode->crtc_hdisplay; in bxt_dsi_get_pipe_config()
1145 adjusted_mode->crtc_hsync_end = hsync + adjusted_mode->crtc_hsync_start; in bxt_dsi_get_pipe_config()
1146 adjusted_mode->crtc_hblank_start = adjusted_mode->crtc_hdisplay; in bxt_dsi_get_pipe_config()
1147 adjusted_mode->crtc_hblank_end = adjusted_mode->crtc_htotal; in bxt_dsi_get_pipe_config()
1149 adjusted_mode->crtc_vsync_start = vfp + adjusted_mode->crtc_vdisplay; in bxt_dsi_get_pipe_config()
1150 adjusted_mode->crtc_vsync_end = vsync + adjusted_mode->crtc_vsync_start; in bxt_dsi_get_pipe_config()
1151 adjusted_mode->crtc_vblank_start = adjusted_mode->crtc_vdisplay; in bxt_dsi_get_pipe_config()
1152 adjusted_mode->crtc_vblank_end = adjusted_mode->crtc_vtotal; in bxt_dsi_get_pipe_config()
1166 hfp_sw = adjusted_mode_sw->crtc_hsync_start - in bxt_dsi_get_pipe_config()
1167 adjusted_mode_sw->crtc_hdisplay; in bxt_dsi_get_pipe_config()
1168 hsync_sw = adjusted_mode_sw->crtc_hsync_end - in bxt_dsi_get_pipe_config()
1169 adjusted_mode_sw->crtc_hsync_start; in bxt_dsi_get_pipe_config()
1170 hbp_sw = adjusted_mode_sw->crtc_htotal - in bxt_dsi_get_pipe_config()
1171 adjusted_mode_sw->crtc_hsync_end; in bxt_dsi_get_pipe_config()
1173 if (intel_dsi->dual_link) { in bxt_dsi_get_pipe_config()
1180 intel_dsi->burst_mode_ratio); in bxt_dsi_get_pipe_config()
1182 intel_dsi->burst_mode_ratio); in bxt_dsi_get_pipe_config()
1184 intel_dsi->burst_mode_ratio); in bxt_dsi_get_pipe_config()
1186 /* Reverse calculating the adjusted mode parameters from port reg vals*/ in bxt_dsi_get_pipe_config()
1188 intel_dsi->burst_mode_ratio); in bxt_dsi_get_pipe_config()
1190 intel_dsi->burst_mode_ratio); in bxt_dsi_get_pipe_config()
1192 intel_dsi->burst_mode_ratio); in bxt_dsi_get_pipe_config()
1194 if (intel_dsi->dual_link) { in bxt_dsi_get_pipe_config()
1200 crtc_htotal_sw = adjusted_mode_sw->crtc_hdisplay + hfp_sw + in bxt_dsi_get_pipe_config()
1202 crtc_hsync_start_sw = hfp_sw + adjusted_mode_sw->crtc_hdisplay; in bxt_dsi_get_pipe_config()
1204 crtc_hblank_start_sw = adjusted_mode_sw->crtc_hdisplay; in bxt_dsi_get_pipe_config()
1207 if (adjusted_mode->crtc_htotal == crtc_htotal_sw) in bxt_dsi_get_pipe_config()
1208 adjusted_mode->crtc_htotal = adjusted_mode_sw->crtc_htotal; in bxt_dsi_get_pipe_config()
1210 if (adjusted_mode->crtc_hsync_start == crtc_hsync_start_sw) in bxt_dsi_get_pipe_config()
1211 adjusted_mode->crtc_hsync_start = in bxt_dsi_get_pipe_config()
1212 adjusted_mode_sw->crtc_hsync_start; in bxt_dsi_get_pipe_config()
1214 if (adjusted_mode->crtc_hsync_end == crtc_hsync_end_sw) in bxt_dsi_get_pipe_config()
1215 adjusted_mode->crtc_hsync_end = in bxt_dsi_get_pipe_config()
1216 adjusted_mode_sw->crtc_hsync_end; in bxt_dsi_get_pipe_config()
1218 if (adjusted_mode->crtc_hblank_start == crtc_hblank_start_sw) in bxt_dsi_get_pipe_config()
1219 adjusted_mode->crtc_hblank_start = in bxt_dsi_get_pipe_config()
1220 adjusted_mode_sw->crtc_hblank_start; in bxt_dsi_get_pipe_config()
1222 if (adjusted_mode->crtc_hblank_end == crtc_hblank_end_sw) in bxt_dsi_get_pipe_config()
1223 adjusted_mode->crtc_hblank_end = in bxt_dsi_get_pipe_config()
1224 adjusted_mode_sw->crtc_hblank_end; in bxt_dsi_get_pipe_config()
1230 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); in intel_dsi_get_config()
1232 drm_dbg_kms(&dev_priv->drm, "\n"); in intel_dsi_get_config()
1234 pipe_config->output_types |= BIT(INTEL_OUTPUT_DSI); in intel_dsi_get_config()
1244 pipe_config->hw.adjusted_mode.crtc_clock = pclk; in intel_dsi_get_config()
1245 pipe_config->port_clock = pclk; in intel_dsi_get_config()
1266 struct drm_device *dev = encoder->dev; in set_dsi_timings()
1270 unsigned int bpp = mipi_dsi_pixel_format_to_bpp(intel_dsi->pixel_format); in set_dsi_timings()
1271 unsigned int lane_count = intel_dsi->lane_count; in set_dsi_timings()
1275 hactive = adjusted_mode->crtc_hdisplay; in set_dsi_timings()
1276 hfp = adjusted_mode->crtc_hsync_start - adjusted_mode->crtc_hdisplay; in set_dsi_timings()
1277 hsync = adjusted_mode->crtc_hsync_end - adjusted_mode->crtc_hsync_start; in set_dsi_timings()
1278 hbp = adjusted_mode->crtc_htotal - adjusted_mode->crtc_hsync_end; in set_dsi_timings()
1280 if (intel_dsi->dual_link) { in set_dsi_timings()
1282 if (intel_dsi->dual_link == DSI_DUAL_LINK_FRONT_BACK) in set_dsi_timings()
1283 hactive += intel_dsi->pixel_overlap; in set_dsi_timings()
1289 vfp = adjusted_mode->crtc_vsync_start - adjusted_mode->crtc_vdisplay; in set_dsi_timings()
1290 vsync = adjusted_mode->crtc_vsync_end - adjusted_mode->crtc_vsync_start; in set_dsi_timings()
1291 vbp = adjusted_mode->crtc_vtotal - adjusted_mode->crtc_vsync_end; in set_dsi_timings()
1295 intel_dsi->burst_mode_ratio); in set_dsi_timings()
1296 hfp = txbyteclkhs(hfp, bpp, lane_count, intel_dsi->burst_mode_ratio); in set_dsi_timings()
1298 intel_dsi->burst_mode_ratio); in set_dsi_timings()
1299 hbp = txbyteclkhs(hbp, bpp, lane_count, intel_dsi->burst_mode_ratio); in set_dsi_timings()
1301 for_each_dsi_port(port, intel_dsi->ports) { in set_dsi_timings()
1310 adjusted_mode->crtc_hdisplay); in set_dsi_timings()
1312 adjusted_mode->crtc_vdisplay); in set_dsi_timings()
1314 adjusted_mode->crtc_vtotal); in set_dsi_timings()
1321 /* meaningful for video mode non-burst sync pulse mode only, in set_dsi_timings()
1322 * can be zero for non-burst sync events and burst modes */ in set_dsi_timings()
1355 struct drm_encoder *encoder = &intel_encoder->base; in intel_dsi_prepare()
1356 struct drm_device *dev = encoder->dev; in intel_dsi_prepare()
1358 struct intel_crtc *intel_crtc = to_intel_crtc(pipe_config->uapi.crtc); in intel_dsi_prepare()
1360 const struct drm_display_mode *adjusted_mode = &pipe_config->hw.adjusted_mode; in intel_dsi_prepare()
1362 unsigned int bpp = mipi_dsi_pixel_format_to_bpp(intel_dsi->pixel_format); in intel_dsi_prepare()
1366 drm_dbg_kms(&dev_priv->drm, "pipe %c\n", pipe_name(intel_crtc->pipe)); in intel_dsi_prepare()
1368 mode_hdisplay = adjusted_mode->crtc_hdisplay; in intel_dsi_prepare()
1370 if (intel_dsi->dual_link) { in intel_dsi_prepare()
1372 if (intel_dsi->dual_link == DSI_DUAL_LINK_FRONT_BACK) in intel_dsi_prepare()
1373 mode_hdisplay += intel_dsi->pixel_overlap; in intel_dsi_prepare()
1376 for_each_dsi_port(port, intel_dsi->ports) { in intel_dsi_prepare()
1393 enum pipe pipe = intel_crtc->pipe; in intel_dsi_prepare()
1402 /* XXX: why here, why like this? handling in irq handler?! */ in intel_dsi_prepare()
1407 intel_dsi->dphy_reg); in intel_dsi_prepare()
1410 …adjusted_mode->crtc_vdisplay << VERTICAL_ADDRESS_SHIFT | mode_hdisplay << HORIZONTAL_ADDRESS_SHIFT… in intel_dsi_prepare()
1415 val = intel_dsi->lane_count << DATA_LANES_PRG_REG_SHIFT; in intel_dsi_prepare()
1417 val |= intel_dsi->channel << CMD_MODE_CHANNEL_NUMBER_SHIFT; in intel_dsi_prepare()
1418 val |= CMD_MODE_DATA_WIDTH_8_BIT; /* XXX */ in intel_dsi_prepare()
1420 val |= intel_dsi->channel << VID_MODE_CHANNEL_NUMBER_SHIFT; in intel_dsi_prepare()
1421 val |= pixel_format_to_reg(intel_dsi->pixel_format); in intel_dsi_prepare()
1425 if (intel_dsi->eotp_pkt == 0) in intel_dsi_prepare()
1427 if (intel_dsi->clock_stop) in intel_dsi_prepare()
1436 for_each_dsi_port(port, intel_dsi->ports) { in intel_dsi_prepare()
1443 * In burst mode, value greater than one DPI line Time in byte in intel_dsi_prepare()
1447 * In non-burst mode, Value greater than one DPI frame time in in intel_dsi_prepare()
1451 * In DBI only mode, value greater than one DBI frame time in in intel_dsi_prepare()
1457 intel_dsi->video_mode_format == VIDEO_MODE_BURST) { in intel_dsi_prepare()
1459 …txbyteclkhs(adjusted_mode->crtc_htotal, bpp, intel_dsi->lane_count, intel_dsi->burst_mode_ratio) +… in intel_dsi_prepare()
1462 …txbyteclkhs(adjusted_mode->crtc_vtotal * adjusted_mode->crtc_htotal, bpp, intel_dsi->lane_count, i… in intel_dsi_prepare()
1465 intel_dsi->lp_rx_timeout); in intel_dsi_prepare()
1467 intel_dsi->turn_arnd_val); in intel_dsi_prepare()
1469 intel_dsi->rst_timer_val); in intel_dsi_prepare()
1475 txclkesc(intel_dsi->escape_clk_div, 100)); in intel_dsi_prepare()
1477 if (IS_GEN9_LP(dev_priv) && (!intel_dsi->dual_link)) { in intel_dsi_prepare()
1482 * if not in dual link mode. in intel_dsi_prepare()
1486 intel_dsi->init_count); in intel_dsi_prepare()
1494 intel_dsi->init_count); in intel_dsi_prepare()
1499 * XXX: write MIPI_STOP_STATE_STALL? in intel_dsi_prepare()
1502 intel_dsi->hs_to_lp_count); in intel_dsi_prepare()
1504 /* XXX: low power clock equivalence in terms of byte clock. in intel_dsi_prepare()
1511 intel_dsi->lp_byte_clk); in intel_dsi_prepare()
1515 intel_dsi->lp_byte_clk); in intel_dsi_prepare()
1518 intel_dsi->dphy_reg); in intel_dsi_prepare()
1527 intel_dsi->bw_timer); in intel_dsi_prepare()
1530 …intel_dsi->clk_lp_to_hs_count << LP_HS_SSW_CNT_SHIFT | intel_dsi->clk_hs_to_lp_count << HS_LP_PWR_… in intel_dsi_prepare()
1537 …intel_dsi->video_frmt_cfg_bits | intel_dsi->video_mode_format | IP_TG_CONFIG | RANDOM_DPI_DISPLAY_… in intel_dsi_prepare()
1543 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); in intel_dsi_unprepare()
1551 for_each_dsi_port(port, intel_dsi->ports) { in intel_dsi_unprepare()
1601 struct drm_i915_private *dev_priv = to_i915(connector->base.dev); in vlv_dsi_add_properties()
1603 if (connector->panel.fixed_mode) { in vlv_dsi_add_properties()
1610 drm_connector_attach_scaling_mode_property(&connector->base, in vlv_dsi_add_properties()
1613 connector->base.state->scaling_mode = DRM_MODE_SCALE_ASPECT; in vlv_dsi_add_properties()
1616 &connector->base, in vlv_dsi_add_properties()
1618 connector->panel.fixed_mode->hdisplay, in vlv_dsi_add_properties()
1619 connector->panel.fixed_mode->vdisplay); in vlv_dsi_add_properties()
1632 struct drm_device *dev = intel_dsi->base.base.dev; in vlv_dphy_param_init()
1634 struct mipi_config *mipi_config = dev_priv->vbt.dsi.config; in vlv_dphy_param_init()
1645 switch (intel_dsi->lane_count) { in vlv_dphy_param_init()
1663 tclk_prepare_clkzero = mipi_config->tclk_prepare_clkzero; in vlv_dphy_param_init()
1664 ths_prepare_hszero = mipi_config->ths_prepare_hszero; in vlv_dphy_param_init()
1670 intel_dsi->lp_byte_clk = DIV_ROUND_UP(tlpx_ns * ui_den, 8 * ui_num); in vlv_dphy_param_init()
1682 ths_prepare_ns = max(mipi_config->ths_prepare, in vlv_dphy_param_init()
1683 mipi_config->tclk_prepare); in vlv_dphy_param_init()
1689 drm_dbg_kms(&dev_priv->drm, "prepare count too high %u\n", in vlv_dphy_param_init()
1696 (ths_prepare_hszero - ths_prepare_ns) * ui_den, in vlv_dphy_param_init()
1710 drm_dbg_kms(&dev_priv->drm, "exit zero count too high %u\n", in vlv_dphy_param_init()
1717 (tclk_prepare_clkzero - ths_prepare_ns) in vlv_dphy_param_init()
1721 drm_dbg_kms(&dev_priv->drm, "clock zero count too high %u\n", in vlv_dphy_param_init()
1727 tclk_trail_ns = max(mipi_config->tclk_trail, mipi_config->ths_trail); in vlv_dphy_param_init()
1731 drm_dbg_kms(&dev_priv->drm, "trail count too high %u\n", in vlv_dphy_param_init()
1737 intel_dsi->dphy_reg = exit_zero_cnt << 24 | trail_cnt << 16 | in vlv_dphy_param_init()
1744 * HS to LP switch count = THS-TRAIL + 2TLPX + Extra Byte Count in vlv_dphy_param_init()
1758 hs_to_lp_switch = DIV_ROUND_UP(mipi_config->ths_trail + 2 * tlpx_ui, 8); in vlv_dphy_param_init()
1760 intel_dsi->hs_to_lp_count = max(lp_to_hs_switch, hs_to_lp_switch); in vlv_dphy_param_init()
1761 intel_dsi->hs_to_lp_count += extra_byte_count; in vlv_dphy_param_init()
1764 /* LP -> HS for clock lanes in vlv_dphy_param_init()
1772 intel_dsi->clk_lp_to_hs_count = in vlv_dphy_param_init()
1778 intel_dsi->clk_lp_to_hs_count += extra_byte_count; in vlv_dphy_param_init()
1780 /* HS->LP for Clock Lanes in vlv_dphy_param_init()
1787 intel_dsi->clk_hs_to_lp_count = in vlv_dphy_param_init()
1790 intel_dsi->clk_hs_to_lp_count += extra_byte_count; in vlv_dphy_param_init()
1797 struct drm_device *dev = &dev_priv->drm; in vlv_dsi_init()
1807 drm_dbg_kms(&dev_priv->drm, "\n"); in vlv_dsi_init()
1814 dev_priv->mipi_mmio_base = BXT_MIPI_BASE; in vlv_dsi_init()
1816 dev_priv->mipi_mmio_base = VLV_MIPI_BASE; in vlv_dsi_init()
1828 intel_encoder = &intel_dsi->base; in vlv_dsi_init()
1829 encoder = &intel_encoder->base; in vlv_dsi_init()
1830 intel_dsi->attached_connector = intel_connector; in vlv_dsi_init()
1832 connector = &intel_connector->base; in vlv_dsi_init()
1837 intel_encoder->compute_config = intel_dsi_compute_config; in vlv_dsi_init()
1838 intel_encoder->pre_enable = intel_dsi_pre_enable; in vlv_dsi_init()
1840 intel_encoder->enable = bxt_dsi_enable; in vlv_dsi_init()
1841 intel_encoder->disable = intel_dsi_disable; in vlv_dsi_init()
1842 intel_encoder->post_disable = intel_dsi_post_disable; in vlv_dsi_init()
1843 intel_encoder->get_hw_state = intel_dsi_get_hw_state; in vlv_dsi_init()
1844 intel_encoder->get_config = intel_dsi_get_config; in vlv_dsi_init()
1845 intel_encoder->update_pipe = intel_panel_update_backlight; in vlv_dsi_init()
1847 intel_connector->get_hw_state = intel_connector_get_hw_state; in vlv_dsi_init()
1849 intel_encoder->port = port; in vlv_dsi_init()
1850 intel_encoder->type = INTEL_OUTPUT_DSI; in vlv_dsi_init()
1851 intel_encoder->power_domain = POWER_DOMAIN_PORT_DSI; in vlv_dsi_init()
1852 intel_encoder->cloneable = 0; in vlv_dsi_init()
1859 intel_encoder->pipe_mask = ~0; in vlv_dsi_init()
1861 intel_encoder->pipe_mask = BIT(PIPE_A); in vlv_dsi_init()
1863 intel_encoder->pipe_mask = BIT(PIPE_B); in vlv_dsi_init()
1865 if (dev_priv->vbt.dsi.config->dual_link) in vlv_dsi_init()
1866 intel_dsi->ports = BIT(PORT_A) | BIT(PORT_C); in vlv_dsi_init()
1868 intel_dsi->ports = BIT(port); in vlv_dsi_init()
1870 intel_dsi->dcs_backlight_ports = dev_priv->vbt.dsi.bl_ports; in vlv_dsi_init()
1871 intel_dsi->dcs_cabc_ports = dev_priv->vbt.dsi.cabc_ports; in vlv_dsi_init()
1874 for_each_dsi_port(port, intel_dsi->ports) { in vlv_dsi_init()
1882 intel_dsi->dsi_hosts[port] = host; in vlv_dsi_init()
1886 drm_dbg_kms(&dev_priv->drm, "no device found\n"); in vlv_dsi_init()
1890 /* Use clock read-back from current hw-state for fastboot */ in vlv_dsi_init()
1893 drm_dbg_kms(&dev_priv->drm, "Calculated pclk %d GOP %d\n", in vlv_dsi_init()
1894 intel_dsi->pclk, current_mode->clock); in vlv_dsi_init()
1895 if (intel_fuzzy_clock_check(intel_dsi->pclk, in vlv_dsi_init()
1896 current_mode->clock)) { in vlv_dsi_init()
1897 drm_dbg_kms(&dev_priv->drm, "Using GOP pclk\n"); in vlv_dsi_init()
1898 intel_dsi->pclk = current_mode->clock; in vlv_dsi_init()
1914 connector->display_info.subpixel_order = SubPixelHorizontalRGB; /*XXX*/ in vlv_dsi_init()
1915 connector->interlace_allowed = false; in vlv_dsi_init()
1916 connector->doublescan_allowed = false; in vlv_dsi_init()
1920 mutex_lock(&dev->mode_config.mutex); in vlv_dsi_init()
1922 mutex_unlock(&dev->mode_config.mutex); in vlv_dsi_init()
1925 drm_dbg_kms(&dev_priv->drm, "no fixed mode\n"); in vlv_dsi_init()
1929 intel_panel_init(&intel_connector->panel, fixed_mode, NULL); in vlv_dsi_init()
1937 drm_connector_cleanup(&intel_connector->base); in vlv_dsi_init()
1939 drm_encoder_cleanup(&intel_encoder->base); in vlv_dsi_init()