Lines Matching full:dpll
70 /* Copy shared dpll state */ in intel_atomic_duplicate_dpll_state()
71 for (i = 0; i < dev_priv->dpll.num_shared_dpll; i++) { in intel_atomic_duplicate_dpll_state()
72 struct intel_shared_dpll *pll = &dev_priv->dpll.shared_dplls[i]; in intel_atomic_duplicate_dpll_state()
96 * intel_get_shared_dpll_by_id - get a DPLL given its id
101 * A pointer to the DPLL with @id
107 return &dev_priv->dpll.shared_dplls[id]; in intel_get_shared_dpll_by_id()
111 * intel_get_shared_dpll_id - get the id of a DPLL
113 * @pll: the DPLL
122 long pll_idx = pll - dev_priv->dpll.shared_dplls; in intel_get_shared_dpll_id()
126 pll_idx >= dev_priv->dpll.num_shared_dpll)) in intel_get_shared_dpll_id()
141 "asserting DPLL %s with no DPLL\n", onoff(state))) in assert_shared_dpll()
163 * intel_prepare_shared_dpll - call a dpll's prepare hook
164 * @crtc_state: CRTC, and its state, which has a shared dpll
178 mutex_lock(&dev_priv->dpll.lock); in intel_prepare_shared_dpll()
187 mutex_unlock(&dev_priv->dpll.lock); in intel_prepare_shared_dpll()
191 * intel_enable_shared_dpll - enable a CRTC's shared DPLL
192 * @crtc_state: CRTC, and its state, which has a shared DPLL
194 * Enable the shared DPLL used by @crtc.
207 mutex_lock(&dev_priv->dpll.lock); in intel_enable_shared_dpll()
233 mutex_unlock(&dev_priv->dpll.lock); in intel_enable_shared_dpll()
237 * intel_disable_shared_dpll - disable a CRTC's shared DPLL
238 * @crtc_state: CRTC, and its state, which has a shared DPLL
240 * Disable the shared DPLL used by @crtc.
256 mutex_lock(&dev_priv->dpll.lock); in intel_disable_shared_dpll()
277 mutex_unlock(&dev_priv->dpll.lock); in intel_disable_shared_dpll()
296 pll = &dev_priv->dpll.shared_dplls[i]; in intel_find_shared_dpll()
377 * intel_shared_dpll_swap_state - make atomic DPLL configuration effective
380 * This is the dpll version of drm_atomic_helper_swap_state() since the
396 for (i = 0; i < dev_priv->dpll.num_shared_dpll; i++) { in intel_shared_dpll_swap_state()
398 &dev_priv->dpll.shared_dplls[i]; in intel_shared_dpll_swap_state()
418 hw_state->dpll = val; in ibx_pch_dpll_get_hw_state()
457 intel_de_write(dev_priv, PCH_DPLL(id), pll->state.hw_state.dpll); in ibx_pch_dpll_enable()
464 * DPLL is enabled and the clocks are stable. in ibx_pch_dpll_enable()
468 intel_de_write(dev_priv, PCH_DPLL(id), pll->state.hw_state.dpll); in ibx_pch_dpll_enable()
496 pll = &dev_priv->dpll.shared_dplls[i]; in ibx_get_dpll()
525 "dpll_hw_state: dpll: 0x%x, dpll_md: 0x%x, " in ibx_dump_hw_state()
527 hw_state->dpll, in ibx_dump_hw_state()
541 { "PCH DPLL A", &ibx_pch_dpll_funcs, DPLL_ID_PCH_PLL_A, 0 },
542 { "PCH DPLL B", &ibx_pch_dpll_funcs, DPLL_ID_PCH_PLL_B, 0 },
904 refclk = dev_priv->dpll.ref_clks.nssc; in hsw_ddi_wrpll_get_freq()
914 refclk = dev_priv->dpll.ref_clks.ssc; in hsw_ddi_wrpll_get_freq()
1060 i915->dpll.ref_clks.ssc = 135000; in hsw_update_dpll_ref_clks()
1063 i915->dpll.ref_clks.nssc = 24000; in hsw_update_dpll_ref_clks()
1065 i915->dpll.ref_clks.nssc = 135000; in hsw_update_dpll_ref_clks()
1138 /* DPLL 0 */
1140 /* DPLL 0 doesn't support HDMI mode */
1143 /* DPLL 1 */
1149 /* DPLL 2 */
1155 /* DPLL 3 */
1197 drm_err(&dev_priv->drm, "DPLL %d not locked\n", id); in skl_ddi_pll_enable()
1549 * as the DPLL id in this function. in skl_ddi_hdmi_pll_dividers()
1556 i915->dpll.ref_clks.nssc, in skl_ddi_hdmi_pll_dividers()
1583 int ref_clock = i915->dpll.ref_clks.nssc; in skl_ddi_wrpll_get_freq()
1644 * as the DPLL id in this function. in skl_ddi_dp_set_dpll_hw_state()
1732 "Could not set DP dpll HW state.\n"); in skl_get_dpll()
1776 i915->dpll.ref_clks.nssc = i915->cdclk.hw.ref; in skl_update_dpll_ref_clks()
1804 { "DPLL 0", &skl_ddi_dpll0_funcs, DPLL_ID_SKL_DPLL0, INTEL_DPLL_ALWAYS_ON },
1805 { "DPLL 1", &skl_ddi_pll_funcs, DPLL_ID_SKL_DPLL1, 0 },
1806 { "DPLL 2", &skl_ddi_pll_funcs, DPLL_ID_SKL_DPLL2, 0 },
1807 { "DPLL 3", &skl_ddi_pll_funcs, DPLL_ID_SKL_DPLL3, 0 },
2073 struct dpll best_clock; in bxt_ddi_hdmi_pll_dividers()
2211 struct dpll clock; in bxt_ddi_pll_get_freq()
2221 return chv_calc_dpll_params(i915->dpll.ref_clks.nssc, &clock); in bxt_ddi_pll_get_freq()
2259 i915->dpll.ref_clks.ssc = 100000; in bxt_update_dpll_ref_clks()
2260 i915->dpll.ref_clks.nssc = 100000; in bxt_update_dpll_ref_clks()
2311 /* 1. Enable DPLL power in DPLL_ENABLE. */ in cnl_ddi_pll_enable()
2316 /* 2. Wait for DPLL power state enabled in DPLL_ENABLE. */ in cnl_ddi_pll_enable()
2349 /* 6. Enable DPLL in DPLL_ENABLE. */ in cnl_ddi_pll_enable()
2368 * 9. turn on the clock for the DDI and map the DPLL to the DDI in cnl_ddi_pll_enable()
2393 /* 3. Disable DPLL through DPLL_ENABLE. */ in cnl_ddi_pll_disable()
2411 /* 6. Disable DPLL power in DPLL_ENABLE. */ in cnl_ddi_pll_disable()
2416 /* 7. Wait for DPLL power state disabled in DPLL_ENABLE. */ in cnl_ddi_pll_disable()
2595 i915->dpll.ref_clks.nssc); in cnl_ddi_calculate_wrpll()
2684 return __cnl_ddi_wrpll_get_freq(i915, pll, i915->dpll.ref_clks.nssc); in cnl_ddi_wrpll_get_freq()
2791 "Could not set DP dpll HW state.\n"); in cnl_get_dpll()
2796 "Skip DPLL setup for output_types 0x%x\n", in cnl_get_dpll()
2831 i915->dpll.ref_clks.nssc = i915->cdclk.hw.ref; in cnl_update_dpll_ref_clks()
2851 { "DPLL 0", &cnl_ddi_pll_funcs, DPLL_ID_SKL_DPLL0, 0 },
2852 { "DPLL 1", &cnl_ddi_pll_funcs, DPLL_ID_SKL_DPLL1, 0 },
2853 { "DPLL 2", &cnl_ddi_pll_funcs, DPLL_ID_SKL_DPLL2, 0 },
2966 dev_priv->dpll.ref_clks.nssc == 24000 ? in icl_calc_dp_combo_pll()
2989 switch (dev_priv->dpll.ref_clks.nssc) { in icl_calc_tbt_pll()
2991 MISSING_CASE(dev_priv->dpll.ref_clks.nssc); in icl_calc_tbt_pll()
3004 switch (dev_priv->dpll.ref_clks.nssc) { in icl_calc_tbt_pll()
3006 MISSING_CASE(dev_priv->dpll.ref_clks.nssc); in icl_calc_tbt_pll()
3035 int ref_clock = i915->dpll.ref_clks.nssc; in icl_wrpll_ref_clock()
3039 * use 19.2 because the DPLL automatically divides that by 2. in icl_wrpll_ref_clock()
3178 int refclk_khz = dev_priv->dpll.ref_clks.nssc; in icl_calc_mg_pll_state()
3386 ref_clock = dev_priv->dpll.ref_clks.nssc; in icl_ddi_mg_pll_get_freq()
3452 * icl_set_active_port_dpll - select the active port DPLL for a given CRTC
3453 * @crtc_state: state for the CRTC to select the DPLL for
3713 if (dev_priv->dpll.ref_clks.nssc == 38400) { in mg_pll_get_hw_state()
4061 * We need to disable DC states when this DPLL is enabled. in combo_pll_enable()
4194 i915->dpll.ref_clks.nssc = i915->cdclk.hw.ref; in icl_update_dpll_ref_clks()
4242 { "DPLL 0", &combo_pll_funcs, DPLL_ID_ICL_DPLL0, 0 },
4243 { "DPLL 1", &combo_pll_funcs, DPLL_ID_ICL_DPLL1, 0 },
4262 { "DPLL 0", &combo_pll_funcs, DPLL_ID_ICL_DPLL0, 0 },
4263 { "DPLL 1", &combo_pll_funcs, DPLL_ID_ICL_DPLL1, 0 },
4264 { "DPLL 4", &combo_pll_funcs, DPLL_ID_EHL_DPLL4, 0 },
4284 { "DPLL 0", &combo_pll_funcs, DPLL_ID_ICL_DPLL0, 0 },
4285 { "DPLL 1", &combo_pll_funcs, DPLL_ID_ICL_DPLL1, 0 },
4306 { "DPLL 0", &combo_pll_funcs, DPLL_ID_ICL_DPLL0, 0 },
4307 { "DPLL 1", &combo_pll_funcs, DPLL_ID_ICL_DPLL1, 0 },
4308 { "DPLL 4", &combo_pll_funcs, DPLL_ID_EHL_DPLL4, 0 },
4353 dev_priv->dpll.num_shared_dpll = 0; in intel_shared_dpll_init()
4361 dev_priv->dpll.shared_dplls[i].info = &dpll_info[i]; in intel_shared_dpll_init()
4364 dev_priv->dpll.mgr = dpll_mgr; in intel_shared_dpll_init()
4365 dev_priv->dpll.num_shared_dpll = i; in intel_shared_dpll_init()
4366 mutex_init(&dev_priv->dpll.lock); in intel_shared_dpll_init()
4368 BUG_ON(dev_priv->dpll.num_shared_dpll > I915_NUM_PLLS); in intel_shared_dpll_init()
4395 const struct intel_dpll_mgr *dpll_mgr = dev_priv->dpll.mgr; in intel_reserve_shared_dplls()
4418 const struct intel_dpll_mgr *dpll_mgr = dev_priv->dpll.mgr; in intel_release_shared_dplls()
4423 * the shared DPLL framework and intel_reserve_shared_dplls() is not in intel_release_shared_dplls()
4433 * intel_update_active_dpll - update the active DPLL for a CRTC/encoder
4435 * @crtc: the CRTC for which to update the active DPLL
4436 * @encoder: encoder determining the type of port DPLL
4438 * Update the active DPLL for the given @crtc/@encoder in @crtc's atomic state,
4440 * DPLL selected will be based on the current mode of the encoder's port.
4447 const struct intel_dpll_mgr *dpll_mgr = dev_priv->dpll.mgr; in intel_update_active_dpll()
4456 * intel_dpll_get_freq - calculate the DPLL's output frequency
4458 * @pll: DPLL for which to calculate the output frequency
4504 if (i915->dpll.mgr && i915->dpll.mgr->update_ref_clks) in intel_dpll_readout_hw_state()
4505 i915->dpll.mgr->update_ref_clks(i915); in intel_dpll_readout_hw_state()
4507 for (i = 0; i < i915->dpll.num_shared_dpll; i++) in intel_dpll_readout_hw_state()
4508 readout_dpll_hw_state(i915, &i915->dpll.shared_dplls[i]); in intel_dpll_readout_hw_state()
4529 for (i = 0; i < i915->dpll.num_shared_dpll; i++) in intel_dpll_sanitize_state()
4530 sanitize_dpll_state(i915, &i915->dpll.shared_dplls[i]); in intel_dpll_sanitize_state()
4543 if (dev_priv->dpll.mgr) { in intel_dpll_dump_hw_state()
4544 dev_priv->dpll.mgr->dump_hw_state(dev_priv, hw_state); in intel_dpll_dump_hw_state()
4546 /* fallback for platforms that don't use the shared dpll in intel_dpll_dump_hw_state()
4550 "dpll_hw_state: dpll: 0x%x, dpll_md: 0x%x, " in intel_dpll_dump_hw_state()
4552 hw_state->dpll, in intel_dpll_dump_hw_state()