189 		 "Use count on power well %s is already zero",  in intel_power_well_put()
243  * threads can't disable the power well while the caller tries to read a few
265  * Starting with Haswell, we have a "Power Down Well" that can be turned off
266  * when not needed anymore. We have 4 registers that can request the power well
339 		drm_dbg_kms(&dev_priv->drm, "%s power well enable timeout\n",  in hsw_wait_for_power_well_enable()
374 	 * - a KVMR request on any power well via the KVMR request register  in hsw_wait_for_power_well_disable()
415 		 * before enabling the power well and PW1/PG1's own fuse  in hsw_power_well_enable()
690  * We should only use the power well if we explicitly asked the hardware to
731 		      "Power well 2 on.\n");  in assert_can_enable_dc9()
979 	 * the first power well and hope the WARN gets reported so we can fix  in lookup_power_well()
983 		 "Power well %d not defined for this platform\n",  in lookup_power_well()
993  * This function set the "DC off" power well target_dc_state,
994  * based upon this target_dc_stste, "DC off" power well will
1018 	 * If DC off power well is disabled, need to enable and disable the  in intel_display_power_set_target_dc_state()
1019 	 * DC off power well to effect target DC state.  in intel_display_power_set_target_dc_state()
1304 			"timeout setting power well state %08x (%08x)\n",  in vlv_set_power_well()
1527 	 * reset (ie. the power well has been disabled at  in assert_chv_phy_status()
1728 	 * reset (ie. the power well has been disabled at  in assert_chv_phy_powergate()
1902 			"timeout setting power well state %08x (%08x)\n",  in chv_set_pipe_power_well()
2233 	 * power well disabling.  in release_async_put_domains()
2963  * - top-level GTC (DDI-level GTC is in the well associated with the DDI)
3206 		 * Pipe A power well is the new disp2d well. Pipe B and C
3207 		 * power wells don't actually exist. Pipe A power well is
3255 		.name = "power well 1",
3268 		.name = "MISC IO power well",
3286 		.name = "power well 2",
3299 		.name = "DDI A/E IO power well",
3309 		.name = "DDI B IO power well",
3319 		.name = "DDI C IO power well",
3329 		.name = "DDI D IO power well",
3349 		.name = "power well 1",
3368 		.name = "power well 2",
3409 		.name = "power well 1",
3428 		.name = "power well 2",
3498 		.name = "DDI A IO power well",
3508 		.name = "DDI B IO power well",
3518 		.name = "DDI C IO power well",
3538 		.name = "power well 1",
3597 		.name = "power well 2",
3610 		.name = "DDI A IO power well",
3620 		.name = "DDI B IO power well",
3630 		.name = "DDI C IO power well",
3640 		.name = "DDI D IO power well",
3650 		.name = "DDI F IO power well",
3699 		.name = "power well 1",
3718 		.name = "power well 2",
3729 		.name = "power well 3",
3910 		.name = "power well 4",
4017 		.name = "power well 1",
4036 		.name = "power well 2",
4047 		.name = "power well 3",
4318 		.name = "power well 4",
4330 		.name = "power well 5",
4352 		.name = "power well 1",
4371 		.name = "power well 3",
4384 		.name = "power well 4",
4777 	 * expect us to program the abox_ctl0 register as well, even though  in icl_mbus_init()
4817 			"Display power well on\n");  in assert_can_disable_lcpll()
4982  * well is disabled and most interrupts are disabled, and these are also
5058 	struct i915_power_well *well;  in skl_display_core_init()  local
5068 	well = lookup_power_well(dev_priv, SKL_DISP_PW_1);  in skl_display_core_init()
5069 	intel_power_well_enable(dev_priv, well);  in skl_display_core_init()
5071 	well = lookup_power_well(dev_priv, SKL_DISP_PW_MISC_IO);  in skl_display_core_init()
5072 	intel_power_well_enable(dev_priv, well);  in skl_display_core_init()
5087 	struct i915_power_well *well;  in skl_display_core_uninit()  local
5101 	 * BSpec says to keep the MISC IO power well enabled here, only  in skl_display_core_uninit()
5102 	 * remove our request for power well 1.  in skl_display_core_uninit()
5103 	 * Note that even though the driver's request is removed power well 1  in skl_display_core_uninit()
5106 	well = lookup_power_well(dev_priv, SKL_DISP_PW_1);  in skl_display_core_uninit()
5107 	intel_power_well_disable(dev_priv, well);  in skl_display_core_uninit()
5117 	struct i915_power_well *well;  in bxt_display_core_init()  local
5132 	well = lookup_power_well(dev_priv, SKL_DISP_PW_1);  in bxt_display_core_init()
5133 	intel_power_well_enable(dev_priv, well);  in bxt_display_core_init()
5148 	struct i915_power_well *well;  in bxt_display_core_uninit()  local
5160 	 * Note that even though the driver's request is removed power well 1  in bxt_display_core_uninit()
5165 	well = lookup_power_well(dev_priv, SKL_DISP_PW_1);  in bxt_display_core_uninit()
5166 	intel_power_well_disable(dev_priv, well);  in bxt_display_core_uninit()
5176 	struct i915_power_well *well;  in cnl_display_core_init()  local
5187 	 * 4. Enable Power Well 1 (PG1).  in cnl_display_core_init()
5191 	well = lookup_power_well(dev_priv, SKL_DISP_PW_1);  in cnl_display_core_init()
5192 	intel_power_well_enable(dev_priv, well);  in cnl_display_core_init()
5208 	struct i915_power_well *well;  in cnl_display_core_uninit()  local
5221 	 * 4. Disable Power Well 1 (PG1).  in cnl_display_core_uninit()
5226 	well = lookup_power_well(dev_priv, SKL_DISP_PW_1);  in cnl_display_core_uninit()
5227 	intel_power_well_disable(dev_priv, well);  in cnl_display_core_uninit()
5300 	struct i915_power_well *well;  in icl_display_core_init()  local
5318 	 * 3. Enable Power Well 1 (PG1).  in icl_display_core_init()
5322 	well = lookup_power_well(dev_priv, SKL_DISP_PW_1);  in icl_display_core_init()
5323 	intel_power_well_enable(dev_priv, well);  in icl_display_core_init()
5353 	struct i915_power_well *well;  in icl_display_core_uninit()  local
5366 	 * 4. Disable Power Well 1 (PG1).  in icl_display_core_uninit()
5371 	well = lookup_power_well(dev_priv, SKL_DISP_PW_1);  in icl_display_core_uninit()
5372 	intel_power_well_disable(dev_priv, well);  in icl_display_core_uninit()
5390 	 * power well state and lane status to reconstruct the  in chv_phy_control_init()
5536  * power well must match its HW enabled state, see
5608 	/* Remove the refcount we took to keep power well support disabled. */  in intel_power_domains_driver_remove()
5616 	/* Keep the power well enabled, but cancel its rpm wakeref. */  in intel_power_domains_driver_remove()
5695 	 * Even if power well support was disabled we still want to disable  in intel_power_domains_suspend()
5766  * Verify if the reference count of each power well matches its HW enabled
5792 				"power well %s state mismatch (refcount %d/enabled %d)",  in intel_power_domains_verify_state()
5802 				"power well %s refcount/domain refcount mismatch "  in intel_power_domains_verify_state()