Lines Matching full:dpll
578 static int pnv_calc_dpll_params(int refclk, struct dpll *clock) in pnv_calc_dpll_params()
590 static u32 i9xx_dpll_compute_m(struct dpll *dpll) in i9xx_dpll_compute_m() argument
592 return 5 * (dpll->m1 + 2) + (dpll->m2 + 2); in i9xx_dpll_compute_m()
595 static int i9xx_calc_dpll_params(int refclk, struct dpll *clock) in i9xx_calc_dpll_params()
607 static int vlv_calc_dpll_params(int refclk, struct dpll *clock) in vlv_calc_dpll_params()
619 int chv_calc_dpll_params(int refclk, struct dpll *clock) in chv_calc_dpll_params()
638 const struct dpll *clock) in intel_pll_is_valid()
711 int target, int refclk, struct dpll *match_clock, in i9xx_find_best_dpll()
712 struct dpll *best_clock) in i9xx_find_best_dpll()
715 struct dpll clock; in i9xx_find_best_dpll()
769 int target, int refclk, struct dpll *match_clock, in pnv_find_best_dpll()
770 struct dpll *best_clock) in pnv_find_best_dpll()
773 struct dpll clock; in pnv_find_best_dpll()
825 int target, int refclk, struct dpll *match_clock, in g4x_find_best_dpll()
826 struct dpll *best_clock) in g4x_find_best_dpll()
829 struct dpll clock; in g4x_find_best_dpll()
876 const struct dpll *calculated_clock, in vlv_PLL_is_optimal()
877 const struct dpll *best_clock, in vlv_PLL_is_optimal()
919 int target, int refclk, struct dpll *match_clock, in vlv_find_best_dpll()
920 struct dpll *best_clock) in vlv_find_best_dpll()
924 struct dpll clock; in vlv_find_best_dpll()
979 int target, int refclk, struct dpll *match_clock, in chv_find_best_dpll()
980 struct dpll *best_clock) in chv_find_best_dpll()
985 struct dpll clock; in chv_find_best_dpll()
1035 struct dpll *best_clock) in bxt_find_best_dpll()
1113 val = intel_de_read(dev_priv, DPLL(pipe)); in assert_pll()
1404 intel_de_write(dev_priv, DPLL(pipe), pipe_config->dpll_hw_state.dpll); in _vlv_enable_pll()
1405 intel_de_posting_read(dev_priv, DPLL(pipe)); in _vlv_enable_pll()
1408 if (intel_de_wait_for_set(dev_priv, DPLL(pipe), DPLL_LOCK_VLV, 1)) in _vlv_enable_pll()
1409 drm_err(&dev_priv->drm, "DPLL %d failed to lock\n", pipe); in _vlv_enable_pll()
1423 if (pipe_config->dpll_hw_state.dpll & DPLL_VCO_ENABLE) in vlv_enable_pll()
1455 intel_de_write(dev_priv, DPLL(pipe), pipe_config->dpll_hw_state.dpll); in _chv_enable_pll()
1458 if (intel_de_wait_for_set(dev_priv, DPLL(pipe), DPLL_LOCK_VLV, 1)) in _chv_enable_pll()
1473 if (pipe_config->dpll_hw_state.dpll & DPLL_VCO_ENABLE) in chv_enable_pll()
1494 (intel_de_read(dev_priv, DPLL(PIPE_B)) & in chv_enable_pll()
1515 i915_reg_t reg = DPLL(crtc->pipe); in i9xx_enable_pll()
1516 u32 dpll = crtc_state->dpll_hw_state.dpll; in i9xx_enable_pll() local
1527 * the P1/P2 dividers. Otherwise the DPLL will keep using the old in i9xx_enable_pll()
1530 intel_de_write(dev_priv, reg, dpll & ~DPLL_VGA_MODE_DIS); in i9xx_enable_pll()
1531 intel_de_write(dev_priv, reg, dpll); in i9xx_enable_pll()
1542 * DPLL is enabled and the clocks are stable. in i9xx_enable_pll()
1546 intel_de_write(dev_priv, reg, dpll); in i9xx_enable_pll()
1551 intel_de_write(dev_priv, reg, dpll); in i9xx_enable_pll()
1570 intel_de_write(dev_priv, DPLL(pipe), DPLL_VGA_MODE_DIS); in i9xx_disable_pll()
1571 intel_de_posting_read(dev_priv, DPLL(pipe)); in i9xx_disable_pll()
1586 intel_de_write(dev_priv, DPLL(pipe), val); in vlv_disable_pll()
1587 intel_de_posting_read(dev_priv, DPLL(pipe)); in vlv_disable_pll()
1603 intel_de_write(dev_priv, DPLL(pipe), val); in chv_disable_pll()
1604 intel_de_posting_read(dev_priv, DPLL(pipe)); in chv_disable_pll()
1626 dpll_reg = DPLL(0); in vlv_wait_port_ready()
1630 dpll_reg = DPLL(0); in vlv_wait_port_ready()
1658 /* Make sure PCH DPLL is enabled */ in ilk_enable_pch_transcoder()
5886 * mutliplier into the DPLL. */ in ilk_pch_enable()
8233 static u32 pnv_dpll_compute_fp(struct dpll *dpll) in pnv_dpll_compute_fp() argument
8235 return (1 << dpll->n) << 16 | dpll->m2; in pnv_dpll_compute_fp()
8238 static u32 i9xx_dpll_compute_fp(struct dpll *dpll) in i9xx_dpll_compute_fp() argument
8240 return dpll->n << 16 | dpll->m1 << 8 | dpll->m2; in i9xx_dpll_compute_fp()
8245 struct dpll *reduced_clock) in i9xx_update_pll_dividers()
8251 fp = pnv_dpll_compute_fp(&crtc_state->dpll); in i9xx_update_pll_dividers()
8255 fp = i9xx_dpll_compute_fp(&crtc_state->dpll); in i9xx_update_pll_dividers()
8397 pipe_config->dpll_hw_state.dpll = DPLL_INTEGRATED_REF_CLK_VLV | in vlv_compute_dpll()
8400 pipe_config->dpll_hw_state.dpll |= DPLL_INTEGRATED_CRI_CLK_VLV; in vlv_compute_dpll()
8402 /* DPLL not used with DSI, but still need the rest set up */ in vlv_compute_dpll()
8404 pipe_config->dpll_hw_state.dpll |= DPLL_VCO_ENABLE | in vlv_compute_dpll()
8414 pipe_config->dpll_hw_state.dpll = DPLL_SSC_REF_CLK_CHV | in chv_compute_dpll()
8417 pipe_config->dpll_hw_state.dpll |= DPLL_INTEGRATED_CRI_CLK_VLV; in chv_compute_dpll()
8419 /* DPLL not used with DSI, but still need the rest set up */ in chv_compute_dpll()
8421 pipe_config->dpll_hw_state.dpll |= DPLL_VCO_ENABLE; in chv_compute_dpll()
8438 intel_de_write(dev_priv, DPLL(pipe), in vlv_prepare_pll()
8439 pipe_config->dpll_hw_state.dpll & ~(DPLL_VCO_ENABLE | DPLL_EXT_BUFFER_ENABLE_VLV)); in vlv_prepare_pll()
8441 /* No need to actually set up the DPLL with DSI */ in vlv_prepare_pll()
8442 if ((pipe_config->dpll_hw_state.dpll & DPLL_VCO_ENABLE) == 0) in vlv_prepare_pll()
8447 bestn = pipe_config->dpll.n; in vlv_prepare_pll()
8448 bestm1 = pipe_config->dpll.m1; in vlv_prepare_pll()
8449 bestm2 = pipe_config->dpll.m2; in vlv_prepare_pll()
8450 bestp1 = pipe_config->dpll.p1; in vlv_prepare_pll()
8451 bestp2 = pipe_config->dpll.p2; in vlv_prepare_pll()
8539 intel_de_write(dev_priv, DPLL(pipe), in chv_prepare_pll()
8540 pipe_config->dpll_hw_state.dpll & ~DPLL_VCO_ENABLE); in chv_prepare_pll()
8542 /* No need to actually set up the DPLL with DSI */ in chv_prepare_pll()
8543 if ((pipe_config->dpll_hw_state.dpll & DPLL_VCO_ENABLE) == 0) in chv_prepare_pll()
8546 bestn = pipe_config->dpll.n; in chv_prepare_pll()
8547 bestm2_frac = pipe_config->dpll.m2 & 0x3fffff; in chv_prepare_pll()
8548 bestm1 = pipe_config->dpll.m1; in chv_prepare_pll()
8549 bestm2 = pipe_config->dpll.m2 >> 22; in chv_prepare_pll()
8550 bestp1 = pipe_config->dpll.p1; in chv_prepare_pll()
8551 bestp2 = pipe_config->dpll.p2; in chv_prepare_pll()
8552 vco = pipe_config->dpll.vco; in chv_prepare_pll()
8635 * @dpll: PLL configuration
8637 * Enable the PLL for @pipe using the supplied @dpll config. To be used
8642 const struct dpll *dpll) in vlv_force_pll_on() argument
8653 pipe_config->dpll = *dpll; in vlv_force_pll_on()
8688 struct dpll *reduced_clock) in i9xx_compute_dpll()
8691 u32 dpll; in i9xx_compute_dpll() local
8692 struct dpll *clock = &crtc_state->dpll; in i9xx_compute_dpll()
8696 dpll = DPLL_VGA_MODE_DIS; in i9xx_compute_dpll()
8699 dpll |= DPLLB_MODE_LVDS; in i9xx_compute_dpll()
8701 dpll |= DPLLB_MODE_DAC_SERIAL; in i9xx_compute_dpll()
8705 dpll |= (crtc_state->pixel_multiplier - 1) in i9xx_compute_dpll()
8711 dpll |= DPLL_SDVO_HIGH_SPEED; in i9xx_compute_dpll()
8714 dpll |= DPLL_SDVO_HIGH_SPEED; in i9xx_compute_dpll()
8718 dpll |= (1 << (clock->p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT_PINEVIEW; in i9xx_compute_dpll()
8720 dpll |= (1 << (clock->p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT; in i9xx_compute_dpll()
8722 dpll |= (1 << (reduced_clock->p1 - 1)) << DPLL_FPA1_P1_POST_DIV_SHIFT; in i9xx_compute_dpll()
8726 dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_5; in i9xx_compute_dpll()
8729 dpll |= DPLLB_LVDS_P2_CLOCK_DIV_7; in i9xx_compute_dpll()
8732 dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_10; in i9xx_compute_dpll()
8735 dpll |= DPLLB_LVDS_P2_CLOCK_DIV_14; in i9xx_compute_dpll()
8739 dpll |= (6 << PLL_LOAD_PULSE_PHASE_SHIFT); in i9xx_compute_dpll()
8742 dpll |= PLL_REF_INPUT_TVCLKINBC; in i9xx_compute_dpll()
8745 dpll |= PLLB_REF_INPUT_SPREADSPECTRUMIN; in i9xx_compute_dpll()
8747 dpll |= PLL_REF_INPUT_DREFCLK; in i9xx_compute_dpll()
8749 dpll |= DPLL_VCO_ENABLE; in i9xx_compute_dpll()
8750 crtc_state->dpll_hw_state.dpll = dpll; in i9xx_compute_dpll()
8761 struct dpll *reduced_clock) in i8xx_compute_dpll()
8765 u32 dpll; in i8xx_compute_dpll() local
8766 struct dpll *clock = &crtc_state->dpll; in i8xx_compute_dpll()
8770 dpll = DPLL_VGA_MODE_DIS; in i8xx_compute_dpll()
8773 dpll |= (1 << (clock->p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT; in i8xx_compute_dpll()
8776 dpll |= PLL_P1_DIVIDE_BY_TWO; in i8xx_compute_dpll()
8778 dpll |= (clock->p1 - 2) << DPLL_FPA01_P1_POST_DIV_SHIFT; in i8xx_compute_dpll()
8780 dpll |= PLL_P2_DIVIDE_BY_4; in i8xx_compute_dpll()
8787 * GTRDYB/DVI_Clk): Bit 31 (DPLL VCO Enable) and Bit 30 (2X Clock in i8xx_compute_dpll()
8788 * Enable) must be set to “1” in both the DPLL A Control Register in i8xx_compute_dpll()
8789 * (06014h-06017h) and DPLL B Control Register (06018h-0601Bh)." in i8xx_compute_dpll()
8797 dpll |= DPLL_DVO_2X_MODE; in i8xx_compute_dpll()
8801 dpll |= PLLB_REF_INPUT_SPREADSPECTRUMIN; in i8xx_compute_dpll()
8803 dpll |= PLL_REF_INPUT_DREFCLK; in i8xx_compute_dpll()
8805 dpll |= DPLL_VCO_ENABLE; in i8xx_compute_dpll()
8806 crtc_state->dpll_hw_state.dpll = dpll; in i8xx_compute_dpll()
9065 refclk, NULL, &crtc_state->dpll)) { in i8xx_crtc_compute_clock()
9110 refclk, NULL, &crtc_state->dpll)) { in g4x_crtc_compute_clock()
9147 refclk, NULL, &crtc_state->dpll)) { in pnv_crtc_compute_clock()
9184 refclk, NULL, &crtc_state->dpll)) { in i9xx_crtc_compute_clock()
9207 refclk, NULL, &crtc_state->dpll)) { in chv_crtc_compute_clock()
9229 refclk, NULL, &crtc_state->dpll)) { in vlv_crtc_compute_clock()
9281 struct dpll clock; in vlv_crtc_clock_get()
9285 /* In case of DSI, DPLL will not be used */ in vlv_crtc_clock_get()
9286 if ((pipe_config->dpll_hw_state.dpll & DPLL_VCO_ENABLE) == 0) in vlv_crtc_clock_get()
9395 struct dpll clock; in chv_crtc_clock_get()
9399 /* In case of DSI, DPLL will not be used */ in chv_crtc_clock_get()
9400 if ((pipe_config->dpll_hw_state.dpll & DPLL_VCO_ENABLE) == 0) in chv_crtc_clock_get()
9536 tmp = intel_de_read(dev_priv, DPLL(crtc->pipe)); in i9xx_get_pipe_config()
9546 pipe_config->dpll_hw_state.dpll = intel_de_read(dev_priv, in i9xx_get_pipe_config()
9547 DPLL(crtc->pipe)); in i9xx_get_pipe_config()
9555 pipe_config->dpll_hw_state.dpll &= ~(DPLL_LOCK_VLV | in i9xx_get_pipe_config()
9621 for (i = 0; i < dev_priv->dpll.num_shared_dpll; i++) { in ilk_init_pch_refclk()
9638 /* Ironlake: try to setup display ref clock before DPLL in ilk_init_pch_refclk()
10248 static bool ilk_needs_fb_cb_tune(struct dpll *dpll, int factor) in ilk_needs_fb_cb_tune() argument
10250 return i9xx_dpll_compute_m(dpll) < factor * dpll->n; in ilk_needs_fb_cb_tune()
10255 struct dpll *reduced_clock) in ilk_compute_dpll()
10258 u32 dpll, fp, fp2; in ilk_compute_dpll() local
10273 fp = i9xx_dpll_compute_fp(&crtc_state->dpll); in ilk_compute_dpll()
10275 if (ilk_needs_fb_cb_tune(&crtc_state->dpll, factor)) in ilk_compute_dpll()
10287 dpll = 0; in ilk_compute_dpll()
10290 dpll |= DPLLB_MODE_LVDS; in ilk_compute_dpll()
10292 dpll |= DPLLB_MODE_DAC_SERIAL; in ilk_compute_dpll()
10294 dpll |= (crtc_state->pixel_multiplier - 1) in ilk_compute_dpll()
10299 dpll |= DPLL_SDVO_HIGH_SPEED; in ilk_compute_dpll()
10302 dpll |= DPLL_SDVO_HIGH_SPEED; in ilk_compute_dpll()
10307 * possible to share the DPLL between CRT and HDMI. Enabling in ilk_compute_dpll()
10312 * DPLLs and so DPLL sharing is the only way to get three pipes in ilk_compute_dpll()
10314 * and potentially avoid enabling the second DPLL, but it's not in ilk_compute_dpll()
10316 * this on ILK at all since it has a fixed DPLL<->pipe mapping. in ilk_compute_dpll()
10320 dpll |= DPLL_SDVO_HIGH_SPEED; in ilk_compute_dpll()
10323 dpll |= (1 << (crtc_state->dpll.p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT; in ilk_compute_dpll()
10325 dpll |= (1 << (crtc_state->dpll.p1 - 1)) << DPLL_FPA1_P1_POST_DIV_SHIFT; in ilk_compute_dpll()
10327 switch (crtc_state->dpll.p2) { in ilk_compute_dpll()
10329 dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_5; in ilk_compute_dpll()
10332 dpll |= DPLLB_LVDS_P2_CLOCK_DIV_7; in ilk_compute_dpll()
10335 dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_10; in ilk_compute_dpll()
10338 dpll |= DPLLB_LVDS_P2_CLOCK_DIV_14; in ilk_compute_dpll()
10344 dpll |= PLLB_REF_INPUT_SPREADSPECTRUMIN; in ilk_compute_dpll()
10346 dpll |= PLL_REF_INPUT_DREFCLK; in ilk_compute_dpll()
10348 dpll |= DPLL_VCO_ENABLE; in ilk_compute_dpll()
10350 crtc_state->dpll_hw_state.dpll = dpll; in ilk_compute_dpll()
10396 refclk, NULL, &crtc_state->dpll)) { in ilk_crtc_compute_clock()
10794 tmp = pipe_config->dpll_hw_state.dpll; in ilk_get_pipe_config()
12122 u32 dpll = pipe_config->dpll_hw_state.dpll; in i9xx_pll_refclk() local
12124 if ((dpll & PLL_REF_INPUT_MASK) == PLLB_REF_INPUT_SPREADSPECTRUMIN) in i9xx_pll_refclk()
12141 u32 dpll = pipe_config->dpll_hw_state.dpll; in i9xx_crtc_clock_get() local
12143 struct dpll clock; in i9xx_crtc_clock_get()
12147 if ((dpll & DISPLAY_RATE_SELECT_FPA1) == 0) in i9xx_crtc_clock_get()
12163 clock.p1 = ffs((dpll & DPLL_FPA01_P1_POST_DIV_MASK_PINEVIEW) >> in i9xx_crtc_clock_get()
12166 clock.p1 = ffs((dpll & DPLL_FPA01_P1_POST_DIV_MASK) >> in i9xx_crtc_clock_get()
12169 switch (dpll & DPLL_MODE_MASK) { in i9xx_crtc_clock_get()
12171 clock.p2 = dpll & DPLL_DAC_SERIAL_P2_CLOCK_DIV_5 ? in i9xx_crtc_clock_get()
12175 clock.p2 = dpll & DPLLB_LVDS_P2_CLOCK_DIV_7 ? in i9xx_crtc_clock_get()
12180 "Unknown DPLL mode %08x in programmed " in i9xx_crtc_clock_get()
12181 "mode\n", (int)(dpll & DPLL_MODE_MASK)); in i9xx_crtc_clock_get()
12195 clock.p1 = ffs((dpll & DPLL_FPA01_P1_POST_DIV_MASK_I830_LVDS) >> in i9xx_crtc_clock_get()
12203 if (dpll & PLL_P1_DIVIDE_BY_TWO) in i9xx_crtc_clock_get()
12206 clock.p1 = ((dpll & DPLL_FPA01_P1_POST_DIV_MASK_I830) >> in i9xx_crtc_clock_get()
12209 if (dpll & PLL_P2_DIVIDE_BY_4) in i9xx_crtc_clock_get()
12250 /* read out port_clock from the DPLL */ in ilk_pch_clock_get()
13989 PIPE_CONF_CHECK_X(dpll_hw_state.dpll); in intel_pipe_config_compare()
14486 for (i = 0; i < dev_priv->dpll.num_shared_dpll; i++) in verify_disabled_dpll_state()
14488 &dev_priv->dpll.shared_dplls[i], in verify_disabled_dpll_state()
18065 struct dpll clock = { in i830_enable_pipe()
18072 u32 dpll, fp; in i830_enable_pipe() local
18083 dpll = DPLL_DVO_2X_MODE | in i830_enable_pipe()
18103 * the P1/P2 dividers. Otherwise the DPLL will keep using the old in i830_enable_pipe()
18106 intel_de_write(dev_priv, DPLL(pipe), dpll & ~DPLL_VGA_MODE_DIS); in i830_enable_pipe()
18107 intel_de_write(dev_priv, DPLL(pipe), dpll); in i830_enable_pipe()
18110 intel_de_posting_read(dev_priv, DPLL(pipe)); in i830_enable_pipe()
18114 * DPLL is enabled and the clocks are stable. in i830_enable_pipe()
18118 intel_de_write(dev_priv, DPLL(pipe), dpll); in i830_enable_pipe()
18122 intel_de_write(dev_priv, DPLL(pipe), dpll); in i830_enable_pipe()
18123 intel_de_posting_read(dev_priv, DPLL(pipe)); in i830_enable_pipe()
18160 intel_de_write(dev_priv, DPLL(pipe), DPLL_VGA_MODE_DIS); in i830_disable_pipe()
18161 intel_de_posting_read(dev_priv, DPLL(pipe)); in i830_disable_pipe()
18345 * the hardware when a high res displays plugged in. DPLL P in has_bogus_dpll_config()