Lines Matching +full:vco +full:- +full:offset
2 * Copyright © 2006-2017 Intel Corporation
63 cdclk_config->cdclk = 133333; in fixed_133mhz_get_cdclk()
69 cdclk_config->cdclk = 200000; in fixed_200mhz_get_cdclk()
75 cdclk_config->cdclk = 266667; in fixed_266mhz_get_cdclk()
81 cdclk_config->cdclk = 333333; in fixed_333mhz_get_cdclk()
87 cdclk_config->cdclk = 400000; in fixed_400mhz_get_cdclk()
93 cdclk_config->cdclk = 450000; in fixed_450mhz_get_cdclk()
99 struct pci_dev *pdev = dev_priv->drm.pdev; in i85x_get_cdclk()
107 if (pdev->revision == 0x1) { in i85x_get_cdclk()
108 cdclk_config->cdclk = 133333; in i85x_get_cdclk()
112 pci_bus_read_config_word(pdev->bus, in i85x_get_cdclk()
122 cdclk_config->cdclk = 200000; in i85x_get_cdclk()
125 cdclk_config->cdclk = 250000; in i85x_get_cdclk()
128 cdclk_config->cdclk = 133333; in i85x_get_cdclk()
133 cdclk_config->cdclk = 266667; in i85x_get_cdclk()
141 struct pci_dev *pdev = dev_priv->drm.pdev; in i915gm_get_cdclk()
147 cdclk_config->cdclk = 133333; in i915gm_get_cdclk()
153 cdclk_config->cdclk = 333333; in i915gm_get_cdclk()
157 cdclk_config->cdclk = 190000; in i915gm_get_cdclk()
165 struct pci_dev *pdev = dev_priv->drm.pdev; in i945gm_get_cdclk()
171 cdclk_config->cdclk = 133333; in i945gm_get_cdclk()
177 cdclk_config->cdclk = 320000; in i945gm_get_cdclk()
181 cdclk_config->cdclk = 200000; in i945gm_get_cdclk()
226 unsigned int vco; in intel_hpll_vco() local
246 vco = vco_table[tmp & 0x7]; in intel_hpll_vco()
247 if (vco == 0) in intel_hpll_vco()
248 drm_err(&dev_priv->drm, "Bad HPLL VCO (HPLLVCO=0x%02x)\n", in intel_hpll_vco()
251 drm_dbg_kms(&dev_priv->drm, "HPLL VCO %u kHz\n", vco); in intel_hpll_vco()
253 return vco; in intel_hpll_vco()
259 struct pci_dev *pdev = dev_priv->drm.pdev; in g33_get_cdclk()
268 cdclk_config->vco = intel_hpll_vco(dev_priv); in g33_get_cdclk()
277 switch (cdclk_config->vco) { in g33_get_cdclk()
294 cdclk_config->cdclk = DIV_ROUND_CLOSEST(cdclk_config->vco, in g33_get_cdclk()
299 drm_err(&dev_priv->drm, in g33_get_cdclk()
300 "Unable to determine CDCLK. HPLL VCO=%u kHz, CFGC=0x%08x\n", in g33_get_cdclk()
301 cdclk_config->vco, tmp); in g33_get_cdclk()
302 cdclk_config->cdclk = 190476; in g33_get_cdclk()
308 struct pci_dev *pdev = dev_priv->drm.pdev; in pnv_get_cdclk()
315 cdclk_config->cdclk = 266667; in pnv_get_cdclk()
318 cdclk_config->cdclk = 333333; in pnv_get_cdclk()
321 cdclk_config->cdclk = 444444; in pnv_get_cdclk()
324 cdclk_config->cdclk = 200000; in pnv_get_cdclk()
327 drm_err(&dev_priv->drm, in pnv_get_cdclk()
331 cdclk_config->cdclk = 133333; in pnv_get_cdclk()
334 cdclk_config->cdclk = 166667; in pnv_get_cdclk()
342 struct pci_dev *pdev = dev_priv->drm.pdev; in i965gm_get_cdclk()
350 cdclk_config->vco = intel_hpll_vco(dev_priv); in i965gm_get_cdclk()
354 cdclk_sel = ((tmp >> 8) & 0x1f) - 1; in i965gm_get_cdclk()
359 switch (cdclk_config->vco) { in i965gm_get_cdclk()
373 cdclk_config->cdclk = DIV_ROUND_CLOSEST(cdclk_config->vco, in i965gm_get_cdclk()
378 drm_err(&dev_priv->drm, in i965gm_get_cdclk()
379 "Unable to determine CDCLK. HPLL VCO=%u kHz, CFGC=0x%04x\n", in i965gm_get_cdclk()
380 cdclk_config->vco, tmp); in i965gm_get_cdclk()
381 cdclk_config->cdclk = 200000; in i965gm_get_cdclk()
387 struct pci_dev *pdev = dev_priv->drm.pdev; in gm45_get_cdclk()
391 cdclk_config->vco = intel_hpll_vco(dev_priv); in gm45_get_cdclk()
397 switch (cdclk_config->vco) { in gm45_get_cdclk()
401 cdclk_config->cdclk = cdclk_sel ? 333333 : 222222; in gm45_get_cdclk()
404 cdclk_config->cdclk = cdclk_sel ? 320000 : 228571; in gm45_get_cdclk()
407 drm_err(&dev_priv->drm, in gm45_get_cdclk()
408 "Unable to determine CDCLK. HPLL VCO=%u, CFGC=0x%04x\n", in gm45_get_cdclk()
409 cdclk_config->vco, tmp); in gm45_get_cdclk()
410 cdclk_config->cdclk = 222222; in gm45_get_cdclk()
422 cdclk_config->cdclk = 800000; in hsw_get_cdclk()
424 cdclk_config->cdclk = 450000; in hsw_get_cdclk()
426 cdclk_config->cdclk = 450000; in hsw_get_cdclk()
428 cdclk_config->cdclk = 337500; in hsw_get_cdclk()
430 cdclk_config->cdclk = 540000; in hsw_get_cdclk()
435 int freq_320 = (dev_priv->hpll_freq << 1) % 320000 != 0 ? in vlv_calc_cdclk()
468 return DIV_ROUND_CLOSEST(dev_priv->hpll_freq << 1, cdclk) - 1; in vlv_calc_voltage_level()
480 cdclk_config->vco = vlv_get_hpll_vco(dev_priv); in vlv_get_cdclk()
481 cdclk_config->cdclk = vlv_get_cck_clock(dev_priv, "cdclk", in vlv_get_cdclk()
483 cdclk_config->vco); in vlv_get_cdclk()
491 cdclk_config->voltage_level = (val & DSPFREQGUAR_MASK) >> in vlv_get_cdclk()
494 cdclk_config->voltage_level = (val & DSPFREQGUAR_MASK_CHV) >> in vlv_get_cdclk()
507 if (dev_priv->cdclk.hw.cdclk >= dev_priv->czclk_freq) { in vlv_program_pfi_credits()
518 * WA - write default credits before re-programming in vlv_program_pfi_credits()
531 drm_WARN_ON(&dev_priv->drm, in vlv_program_pfi_credits()
539 int cdclk = cdclk_config->cdclk; in vlv_set_cdclk()
540 u32 val, cmd = cdclk_config->voltage_level; in vlv_set_cdclk()
575 drm_err(&dev_priv->drm, in vlv_set_cdclk()
582 divider = DIV_ROUND_CLOSEST(dev_priv->hpll_freq << 1, in vlv_set_cdclk()
583 cdclk) - 1; in vlv_set_cdclk()
594 drm_err(&dev_priv->drm, in vlv_set_cdclk()
598 /* adjust self-refresh exit latency value */ in vlv_set_cdclk()
628 int cdclk = cdclk_config->cdclk; in chv_set_cdclk()
629 u32 val, cmd = cdclk_config->voltage_level; in chv_set_cdclk()
659 drm_err(&dev_priv->drm, in chv_set_cdclk()
706 cdclk_config->cdclk = 800000; in bdw_get_cdclk()
708 cdclk_config->cdclk = 450000; in bdw_get_cdclk()
710 cdclk_config->cdclk = 450000; in bdw_get_cdclk()
712 cdclk_config->cdclk = 540000; in bdw_get_cdclk()
714 cdclk_config->cdclk = 337500; in bdw_get_cdclk()
716 cdclk_config->cdclk = 675000; in bdw_get_cdclk()
722 cdclk_config->voltage_level = in bdw_get_cdclk()
723 bdw_calc_voltage_level(cdclk_config->cdclk); in bdw_get_cdclk()
730 int cdclk = cdclk_config->cdclk; in bdw_set_cdclk()
734 if (drm_WARN(&dev_priv->drm, in bdw_set_cdclk()
746 drm_err(&dev_priv->drm, in bdw_set_cdclk()
761 drm_err(&dev_priv->drm, "Switching to FCLK failed\n"); in bdw_set_cdclk()
792 drm_err(&dev_priv->drm, "Switching back to LCPLL failed\n"); in bdw_set_cdclk()
795 cdclk_config->voltage_level); in bdw_set_cdclk()
798 DIV_ROUND_CLOSEST(cdclk, 1000) - 1); in bdw_set_cdclk()
803 static int skl_calc_cdclk(int min_cdclk, int vco) in skl_calc_cdclk() argument
805 if (vco == 8640000) { in skl_calc_cdclk()
843 cdclk_config->ref = 24000; in skl_dpll0_update()
844 cdclk_config->vco = 0; in skl_dpll0_update()
850 if (drm_WARN_ON(&dev_priv->drm, (val & LCPLL_PLL_LOCK) == 0)) in skl_dpll0_update()
855 if (drm_WARN_ON(&dev_priv->drm, in skl_dpll0_update()
867 cdclk_config->vco = 8100000; in skl_dpll0_update()
871 cdclk_config->vco = 8640000; in skl_dpll0_update()
886 cdclk_config->cdclk = cdclk_config->bypass = cdclk_config->ref; in skl_get_cdclk()
888 if (cdclk_config->vco == 0) in skl_get_cdclk()
893 if (cdclk_config->vco == 8640000) { in skl_get_cdclk()
896 cdclk_config->cdclk = 432000; in skl_get_cdclk()
899 cdclk_config->cdclk = 308571; in skl_get_cdclk()
902 cdclk_config->cdclk = 540000; in skl_get_cdclk()
905 cdclk_config->cdclk = 617143; in skl_get_cdclk()
914 cdclk_config->cdclk = 450000; in skl_get_cdclk()
917 cdclk_config->cdclk = 337500; in skl_get_cdclk()
920 cdclk_config->cdclk = 540000; in skl_get_cdclk()
923 cdclk_config->cdclk = 675000; in skl_get_cdclk()
936 cdclk_config->voltage_level = in skl_get_cdclk()
937 skl_calc_voltage_level(cdclk_config->cdclk); in skl_get_cdclk()
940 /* convert from kHz to .1 fixpoint MHz with -1MHz offset */
943 return DIV_ROUND_CLOSEST(cdclk - 1000, 500); in skl_cdclk_decimal()
947 int vco) in skl_set_preferred_cdclk_vco() argument
949 bool changed = dev_priv->skl_preferred_vco_freq != vco; in skl_set_preferred_cdclk_vco()
951 dev_priv->skl_preferred_vco_freq = vco; in skl_set_preferred_cdclk_vco()
957 static void skl_dpll0_enable(struct drm_i915_private *dev_priv, int vco) in skl_dpll0_enable() argument
961 drm_WARN_ON(&dev_priv->drm, vco != 8100000 && vco != 8640000); in skl_dpll0_enable()
965 * taking into account the VCO required to operate the eDP panel at the in skl_dpll0_enable()
966 * desired frequency. The usual DP link rates operate with a VCO of in skl_dpll0_enable()
967 * 8100 while the eDP 1.4 alternate link rates need a VCO of 8640. in skl_dpll0_enable()
970 * works with vco. in skl_dpll0_enable()
977 if (vco == 8640000) in skl_dpll0_enable()
991 drm_err(&dev_priv->drm, "DPLL0 not locked\n"); in skl_dpll0_enable()
993 dev_priv->cdclk.hw.vco = vco; in skl_dpll0_enable()
995 /* We'll want to keep using the current vco from now on. */ in skl_dpll0_enable()
996 skl_set_preferred_cdclk_vco(dev_priv, vco); in skl_dpll0_enable()
1004 drm_err(&dev_priv->drm, "Couldn't disable DPLL0\n"); in skl_dpll0_disable()
1006 dev_priv->cdclk.hw.vco = 0; in skl_dpll0_disable()
1013 int cdclk = cdclk_config->cdclk; in skl_set_cdclk()
1014 int vco = cdclk_config->vco; in skl_set_cdclk() local
1023 * use the corresponding VCO freq as that always leads to using the in skl_set_cdclk()
1026 drm_WARN_ON_ONCE(&dev_priv->drm, in skl_set_cdclk()
1027 IS_SKYLAKE(dev_priv) && vco == 8640000); in skl_set_cdclk()
1034 drm_err(&dev_priv->drm, in skl_set_cdclk()
1042 drm_WARN_ON(&dev_priv->drm, in skl_set_cdclk()
1043 cdclk != dev_priv->cdclk.hw.bypass); in skl_set_cdclk()
1044 drm_WARN_ON(&dev_priv->drm, vco != 0); in skl_set_cdclk()
1063 if (dev_priv->cdclk.hw.vco != 0 && in skl_set_cdclk()
1064 dev_priv->cdclk.hw.vco != vco) in skl_set_cdclk()
1069 if (dev_priv->cdclk.hw.vco != vco) { in skl_set_cdclk()
1081 if (dev_priv->cdclk.hw.vco != vco) in skl_set_cdclk()
1082 skl_dpll0_enable(dev_priv, vco); in skl_set_cdclk()
1098 cdclk_config->voltage_level); in skl_set_cdclk()
1108 * check if the pre-os initialized the display in skl_sanitize_cdclk()
1110 * pre-os which can be used by the OS drivers to check the status in skl_sanitize_cdclk()
1116 intel_dump_cdclk_config(&dev_priv->cdclk.hw, "Current CDCLK"); in skl_sanitize_cdclk()
1119 if (dev_priv->cdclk.hw.vco == 0 || in skl_sanitize_cdclk()
1120 dev_priv->cdclk.hw.cdclk == dev_priv->cdclk.hw.bypass) in skl_sanitize_cdclk()
1126 * decimal part is programmed wrong from BIOS where pre-os does not in skl_sanitize_cdclk()
1131 skl_cdclk_decimal(dev_priv->cdclk.hw.cdclk); in skl_sanitize_cdclk()
1137 drm_dbg_kms(&dev_priv->drm, "Sanitizing cdclk programmed by pre-os\n"); in skl_sanitize_cdclk()
1140 dev_priv->cdclk.hw.cdclk = 0; in skl_sanitize_cdclk()
1142 dev_priv->cdclk.hw.vco = -1; in skl_sanitize_cdclk()
1151 if (dev_priv->cdclk.hw.cdclk != 0 && in skl_cdclk_init_hw()
1152 dev_priv->cdclk.hw.vco != 0) { in skl_cdclk_init_hw()
1154 * Use the current vco as our initial in skl_cdclk_init_hw()
1155 * guess as to what the preferred vco is. in skl_cdclk_init_hw()
1157 if (dev_priv->skl_preferred_vco_freq == 0) in skl_cdclk_init_hw()
1159 dev_priv->cdclk.hw.vco); in skl_cdclk_init_hw()
1163 cdclk_config = dev_priv->cdclk.hw; in skl_cdclk_init_hw()
1165 cdclk_config.vco = dev_priv->skl_preferred_vco_freq; in skl_cdclk_init_hw()
1166 if (cdclk_config.vco == 0) in skl_cdclk_init_hw()
1167 cdclk_config.vco = 8100000; in skl_cdclk_init_hw()
1168 cdclk_config.cdclk = skl_calc_cdclk(0, cdclk_config.vco); in skl_cdclk_init_hw()
1176 struct intel_cdclk_config cdclk_config = dev_priv->cdclk.hw; in skl_cdclk_uninit_hw()
1179 cdclk_config.vco = 0; in skl_cdclk_uninit_hw()
1238 const struct intel_cdclk_vals *table = dev_priv->cdclk.table; in bxt_calc_cdclk()
1242 if (table[i].refclk == dev_priv->cdclk.hw.ref && in bxt_calc_cdclk()
1246 drm_WARN(&dev_priv->drm, 1, in bxt_calc_cdclk()
1248 min_cdclk, dev_priv->cdclk.hw.ref); in bxt_calc_cdclk()
1254 const struct intel_cdclk_vals *table = dev_priv->cdclk.table; in bxt_calc_cdclk_pll_vco()
1257 if (cdclk == dev_priv->cdclk.hw.bypass) in bxt_calc_cdclk_pll_vco()
1261 if (table[i].refclk == dev_priv->cdclk.hw.ref && in bxt_calc_cdclk_pll_vco()
1263 return dev_priv->cdclk.hw.ref * table[i].ratio; in bxt_calc_cdclk_pll_vco()
1265 drm_WARN(&dev_priv->drm, 1, "cdclk %d not valid for refclk %u\n", in bxt_calc_cdclk_pll_vco()
1266 cdclk, dev_priv->cdclk.hw.ref); in bxt_calc_cdclk_pll_vco()
1323 cdclk_config->ref = 24000; in cnl_readout_refclk()
1325 cdclk_config->ref = 19200; in cnl_readout_refclk()
1338 cdclk_config->ref = 24000; in icl_readout_refclk()
1341 cdclk_config->ref = 19200; in icl_readout_refclk()
1344 cdclk_config->ref = 38400; in icl_readout_refclk()
1359 cdclk_config->ref = 19200; in bxt_de_pll_readout()
1365 * CDCLK PLL is disabled, the VCO/ratio doesn't matter, but in bxt_de_pll_readout()
1368 cdclk_config->vco = 0; in bxt_de_pll_readout()
1381 cdclk_config->vco = ratio * cdclk_config->ref; in bxt_de_pll_readout()
1393 cdclk_config->bypass = cdclk_config->ref / 2; in bxt_get_cdclk()
1395 cdclk_config->bypass = 50000; in bxt_get_cdclk()
1397 cdclk_config->bypass = cdclk_config->ref; in bxt_get_cdclk()
1399 if (cdclk_config->vco == 0) { in bxt_get_cdclk()
1400 cdclk_config->cdclk = cdclk_config->bypass; in bxt_get_cdclk()
1411 drm_WARN(&dev_priv->drm, in bxt_get_cdclk()
1420 drm_WARN(&dev_priv->drm, INTEL_GEN(dev_priv) >= 10, in bxt_get_cdclk()
1429 cdclk_config->cdclk = DIV_ROUND_CLOSEST(cdclk_config->vco, div); in bxt_get_cdclk()
1436 cdclk_config->voltage_level = in bxt_get_cdclk()
1437 dev_priv->display.calc_voltage_level(cdclk_config->cdclk); in bxt_get_cdclk()
1447 drm_err(&dev_priv->drm, "timeout waiting for DE PLL unlock\n"); in bxt_de_pll_disable()
1449 dev_priv->cdclk.hw.vco = 0; in bxt_de_pll_disable()
1452 static void bxt_de_pll_enable(struct drm_i915_private *dev_priv, int vco) in bxt_de_pll_enable() argument
1454 int ratio = DIV_ROUND_CLOSEST(vco, dev_priv->cdclk.hw.ref); in bxt_de_pll_enable()
1467 drm_err(&dev_priv->drm, "timeout waiting for DE PLL lock\n"); in bxt_de_pll_enable()
1469 dev_priv->cdclk.hw.vco = vco; in bxt_de_pll_enable()
1482 drm_err(&dev_priv->drm, in cnl_cdclk_pll_disable()
1485 dev_priv->cdclk.hw.vco = 0; in cnl_cdclk_pll_disable()
1488 static void cnl_cdclk_pll_enable(struct drm_i915_private *dev_priv, int vco) in cnl_cdclk_pll_enable() argument
1490 int ratio = DIV_ROUND_CLOSEST(vco, dev_priv->cdclk.hw.ref); in cnl_cdclk_pll_enable()
1501 drm_err(&dev_priv->drm, in cnl_cdclk_pll_enable()
1504 dev_priv->cdclk.hw.vco = vco; in cnl_cdclk_pll_enable()
1531 int cdclk = cdclk_config->cdclk; in bxt_set_cdclk()
1532 int vco = cdclk_config->vco; in bxt_set_cdclk() local
1552 drm_err(&dev_priv->drm, in bxt_set_cdclk()
1558 /* cdclk = vco / 2 / div{1,1.5,2,4} */ in bxt_set_cdclk()
1559 switch (DIV_ROUND_CLOSEST(vco, cdclk)) { in bxt_set_cdclk()
1561 drm_WARN_ON(&dev_priv->drm, in bxt_set_cdclk()
1562 cdclk != dev_priv->cdclk.hw.bypass); in bxt_set_cdclk()
1563 drm_WARN_ON(&dev_priv->drm, vco != 0); in bxt_set_cdclk()
1569 drm_WARN(&dev_priv->drm, in bxt_set_cdclk()
1578 drm_WARN(&dev_priv->drm, INTEL_GEN(dev_priv) >= 10, in bxt_set_cdclk()
1585 if (dev_priv->cdclk.hw.vco != 0 && in bxt_set_cdclk()
1586 dev_priv->cdclk.hw.vco != vco) in bxt_set_cdclk()
1589 if (dev_priv->cdclk.hw.vco != vco) in bxt_set_cdclk()
1590 cnl_cdclk_pll_enable(dev_priv, vco); in bxt_set_cdclk()
1593 if (dev_priv->cdclk.hw.vco != 0 && in bxt_set_cdclk()
1594 dev_priv->cdclk.hw.vco != vco) in bxt_set_cdclk()
1597 if (dev_priv->cdclk.hw.vco != vco) in bxt_set_cdclk()
1598 bxt_de_pll_enable(dev_priv, vco); in bxt_set_cdclk()
1617 cdclk_config->voltage_level); in bxt_set_cdclk()
1627 cdclk_config->voltage_level, in bxt_set_cdclk()
1632 drm_err(&dev_priv->drm, in bxt_set_cdclk()
1645 dev_priv->cdclk.hw.voltage_level = cdclk_config->voltage_level; in bxt_set_cdclk()
1651 int cdclk, vco; in bxt_sanitize_cdclk() local
1654 intel_dump_cdclk_config(&dev_priv->cdclk.hw, "Current CDCLK"); in bxt_sanitize_cdclk()
1656 if (dev_priv->cdclk.hw.vco == 0 || in bxt_sanitize_cdclk()
1657 dev_priv->cdclk.hw.cdclk == dev_priv->cdclk.hw.bypass) in bxt_sanitize_cdclk()
1675 cdclk = bxt_calc_cdclk(dev_priv, dev_priv->cdclk.hw.cdclk); in bxt_sanitize_cdclk()
1676 if (cdclk != dev_priv->cdclk.hw.cdclk) in bxt_sanitize_cdclk()
1679 /* Make sure the VCO is correct for the cdclk */ in bxt_sanitize_cdclk()
1680 vco = bxt_calc_cdclk_pll_vco(dev_priv, cdclk); in bxt_sanitize_cdclk()
1681 if (vco != dev_priv->cdclk.hw.vco) in bxt_sanitize_cdclk()
1687 switch (DIV_ROUND_CLOSEST(dev_priv->cdclk.hw.vco, in bxt_sanitize_cdclk()
1688 dev_priv->cdclk.hw.cdclk)) { in bxt_sanitize_cdclk()
1709 if (IS_GEN9_LP(dev_priv) && dev_priv->cdclk.hw.cdclk >= 500000) in bxt_sanitize_cdclk()
1717 drm_dbg_kms(&dev_priv->drm, "Sanitizing cdclk programmed by pre-os\n"); in bxt_sanitize_cdclk()
1720 dev_priv->cdclk.hw.cdclk = 0; in bxt_sanitize_cdclk()
1723 dev_priv->cdclk.hw.vco = -1; in bxt_sanitize_cdclk()
1732 if (dev_priv->cdclk.hw.cdclk != 0 && in bxt_cdclk_init_hw()
1733 dev_priv->cdclk.hw.vco != 0) in bxt_cdclk_init_hw()
1736 cdclk_config = dev_priv->cdclk.hw; in bxt_cdclk_init_hw()
1740 * - The initial CDCLK needs to be read from VBT. in bxt_cdclk_init_hw()
1744 cdclk_config.vco = bxt_calc_cdclk_pll_vco(dev_priv, cdclk_config.cdclk); in bxt_cdclk_init_hw()
1746 dev_priv->display.calc_voltage_level(cdclk_config.cdclk); in bxt_cdclk_init_hw()
1753 struct intel_cdclk_config cdclk_config = dev_priv->cdclk.hw; in bxt_cdclk_uninit_hw()
1756 cdclk_config.vco = 0; in bxt_cdclk_uninit_hw()
1758 dev_priv->display.calc_voltage_level(cdclk_config.cdclk); in bxt_cdclk_uninit_hw()
1764 * intel_cdclk_init_hw - Initialize CDCLK hardware
1767 * Initialize CDCLK. This consists mainly of initializing dev_priv->cdclk.hw and
1781 * intel_cdclk_uninit_hw - Uninitialize CDCLK hardware
1796 * intel_cdclk_needs_modeset - Determine if changong between the CDCLK
1808 return a->cdclk != b->cdclk || in intel_cdclk_needs_modeset()
1809 a->vco != b->vco || in intel_cdclk_needs_modeset()
1810 a->ref != b->ref; in intel_cdclk_needs_modeset()
1814 * intel_cdclk_can_cd2x_update - Determine if changing between the two CDCLK
1832 return a->cdclk != b->cdclk && in intel_cdclk_can_cd2x_update()
1833 a->vco == b->vco && in intel_cdclk_can_cd2x_update()
1834 a->ref == b->ref; in intel_cdclk_can_cd2x_update()
1838 * intel_cdclk_changed - Determine if two CDCLK configurations are different
1849 a->voltage_level != b->voltage_level; in intel_cdclk_changed()
1855 DRM_DEBUG_DRIVER("%s %d kHz, VCO %d kHz, ref %d kHz, bypass %d kHz, voltage level %d\n", in intel_dump_cdclk_config()
1856 context, cdclk_config->cdclk, cdclk_config->vco, in intel_dump_cdclk_config()
1857 cdclk_config->ref, cdclk_config->bypass, in intel_dump_cdclk_config()
1858 cdclk_config->voltage_level); in intel_dump_cdclk_config()
1862 * intel_set_cdclk - Push the CDCLK configuration to the hardware
1876 if (!intel_cdclk_changed(&dev_priv->cdclk.hw, cdclk_config)) in intel_set_cdclk()
1879 if (drm_WARN_ON_ONCE(&dev_priv->drm, !dev_priv->display.set_cdclk)) in intel_set_cdclk()
1889 mutex_lock(&dev_priv->gmbus_mutex); in intel_set_cdclk()
1890 for_each_intel_dp(&dev_priv->drm, encoder) { in intel_set_cdclk()
1893 mutex_lock_nest_lock(&intel_dp->aux.hw_mutex, in intel_set_cdclk()
1894 &dev_priv->gmbus_mutex); in intel_set_cdclk()
1897 dev_priv->display.set_cdclk(dev_priv, cdclk_config, pipe); in intel_set_cdclk()
1899 for_each_intel_dp(&dev_priv->drm, encoder) { in intel_set_cdclk()
1902 mutex_unlock(&intel_dp->aux.hw_mutex); in intel_set_cdclk()
1904 mutex_unlock(&dev_priv->gmbus_mutex); in intel_set_cdclk()
1906 if (drm_WARN(&dev_priv->drm, in intel_set_cdclk()
1907 intel_cdclk_changed(&dev_priv->cdclk.hw, cdclk_config), in intel_set_cdclk()
1909 intel_dump_cdclk_config(&dev_priv->cdclk.hw, "[hw state]"); in intel_set_cdclk()
1915 * intel_set_cdclk_pre_plane_update - Push the CDCLK state to the hardware
1924 struct drm_i915_private *dev_priv = to_i915(state->base.dev); in intel_set_cdclk_pre_plane_update()
1929 enum pipe pipe = new_cdclk_state->pipe; in intel_set_cdclk_pre_plane_update()
1931 if (!intel_cdclk_changed(&old_cdclk_state->actual, in intel_set_cdclk_pre_plane_update()
1932 &new_cdclk_state->actual)) in intel_set_cdclk_pre_plane_update()
1936 old_cdclk_state->actual.cdclk <= new_cdclk_state->actual.cdclk) { in intel_set_cdclk_pre_plane_update()
1937 drm_WARN_ON(&dev_priv->drm, !new_cdclk_state->base.changed); in intel_set_cdclk_pre_plane_update()
1939 intel_set_cdclk(dev_priv, &new_cdclk_state->actual, pipe); in intel_set_cdclk_pre_plane_update()
1944 * intel_set_cdclk_post_plane_update - Push the CDCLK state to the hardware
1953 struct drm_i915_private *dev_priv = to_i915(state->base.dev); in intel_set_cdclk_post_plane_update()
1958 enum pipe pipe = new_cdclk_state->pipe; in intel_set_cdclk_post_plane_update()
1960 if (!intel_cdclk_changed(&old_cdclk_state->actual, in intel_set_cdclk_post_plane_update()
1961 &new_cdclk_state->actual)) in intel_set_cdclk_post_plane_update()
1965 old_cdclk_state->actual.cdclk > new_cdclk_state->actual.cdclk) { in intel_set_cdclk_post_plane_update()
1966 drm_WARN_ON(&dev_priv->drm, !new_cdclk_state->base.changed); in intel_set_cdclk_post_plane_update()
1968 intel_set_cdclk(dev_priv, &new_cdclk_state->actual, pipe); in intel_set_cdclk_post_plane_update()
1974 struct drm_i915_private *dev_priv = to_i915(crtc_state->uapi.crtc->dev); in intel_pixel_rate_to_cdclk()
1975 int pixel_rate = crtc_state->pixel_rate; in intel_pixel_rate_to_cdclk()
1984 else if (crtc_state->double_wide) in intel_pixel_rate_to_cdclk()
1992 struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc); in intel_planes_min_cdclk()
1993 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); in intel_planes_min_cdclk()
1997 for_each_intel_plane_on_crtc(&dev_priv->drm, crtc, plane) in intel_planes_min_cdclk()
1998 min_cdclk = max(crtc_state->min_cdclk[plane->id], min_cdclk); in intel_planes_min_cdclk()
2006 to_i915(crtc_state->uapi.crtc->dev); in intel_crtc_compute_min_cdclk()
2009 if (!crtc_state->hw.enable) in intel_crtc_compute_min_cdclk()
2024 crtc_state->has_audio && in intel_crtc_compute_min_cdclk()
2025 crtc_state->port_clock >= 540000 && in intel_crtc_compute_min_cdclk()
2026 crtc_state->lane_count == 4) { in intel_crtc_compute_min_cdclk()
2040 if (crtc_state->has_audio && INTEL_GEN(dev_priv) >= 9) in intel_crtc_compute_min_cdclk()
2051 intel_crtc_has_dp_encoder(crtc_state) && crtc_state->has_audio) in intel_crtc_compute_min_cdclk()
2052 min_cdclk = max(crtc_state->port_clock, min_cdclk); in intel_crtc_compute_min_cdclk()
2089 min_t(int, crtc_state->pixel_rate, in intel_crtc_compute_min_cdclk()
2090 dev_priv->max_cdclk_freq)); in intel_crtc_compute_min_cdclk()
2093 if (min_cdclk > dev_priv->max_cdclk_freq) { in intel_crtc_compute_min_cdclk()
2094 drm_dbg_kms(&dev_priv->drm, in intel_crtc_compute_min_cdclk()
2096 min_cdclk, dev_priv->max_cdclk_freq); in intel_crtc_compute_min_cdclk()
2097 return -EINVAL; in intel_crtc_compute_min_cdclk()
2105 struct intel_atomic_state *state = cdclk_state->base.state; in intel_compute_min_cdclk()
2106 struct drm_i915_private *dev_priv = to_i915(state->base.dev); in intel_compute_min_cdclk()
2124 if (cdclk_state->min_cdclk[i] == min_cdclk) in intel_compute_min_cdclk()
2127 cdclk_state->min_cdclk[i] = min_cdclk; in intel_compute_min_cdclk()
2129 ret = intel_atomic_lock_global_state(&cdclk_state->base); in intel_compute_min_cdclk()
2134 min_cdclk = cdclk_state->force_min_cdclk; in intel_compute_min_cdclk()
2136 min_cdclk = max(cdclk_state->min_cdclk[pipe], min_cdclk); in intel_compute_min_cdclk()
2141 min_cdclk = max(bw_state->min_cdclk, min_cdclk); in intel_compute_min_cdclk()
2162 struct intel_atomic_state *state = cdclk_state->base.state; in bxt_compute_min_voltage_level()
2163 struct drm_i915_private *dev_priv = to_i915(state->base.dev); in bxt_compute_min_voltage_level()
2173 if (crtc_state->hw.enable) in bxt_compute_min_voltage_level()
2174 min_voltage_level = crtc_state->min_voltage_level; in bxt_compute_min_voltage_level()
2178 if (cdclk_state->min_voltage_level[i] == min_voltage_level) in bxt_compute_min_voltage_level()
2181 cdclk_state->min_voltage_level[i] = min_voltage_level; in bxt_compute_min_voltage_level()
2183 ret = intel_atomic_lock_global_state(&cdclk_state->base); in bxt_compute_min_voltage_level()
2190 min_voltage_level = max(cdclk_state->min_voltage_level[pipe], in bxt_compute_min_voltage_level()
2198 struct intel_atomic_state *state = cdclk_state->base.state; in vlv_modeset_calc_cdclk()
2199 struct drm_i915_private *dev_priv = to_i915(state->base.dev); in vlv_modeset_calc_cdclk()
2208 cdclk_state->logical.cdclk = cdclk; in vlv_modeset_calc_cdclk()
2209 cdclk_state->logical.voltage_level = in vlv_modeset_calc_cdclk()
2212 if (!cdclk_state->active_pipes) { in vlv_modeset_calc_cdclk()
2213 cdclk = vlv_calc_cdclk(dev_priv, cdclk_state->force_min_cdclk); in vlv_modeset_calc_cdclk()
2215 cdclk_state->actual.cdclk = cdclk; in vlv_modeset_calc_cdclk()
2216 cdclk_state->actual.voltage_level = in vlv_modeset_calc_cdclk()
2219 cdclk_state->actual = cdclk_state->logical; in vlv_modeset_calc_cdclk()
2239 cdclk_state->logical.cdclk = cdclk; in bdw_modeset_calc_cdclk()
2240 cdclk_state->logical.voltage_level = in bdw_modeset_calc_cdclk()
2243 if (!cdclk_state->active_pipes) { in bdw_modeset_calc_cdclk()
2244 cdclk = bdw_calc_cdclk(cdclk_state->force_min_cdclk); in bdw_modeset_calc_cdclk()
2246 cdclk_state->actual.cdclk = cdclk; in bdw_modeset_calc_cdclk()
2247 cdclk_state->actual.voltage_level = in bdw_modeset_calc_cdclk()
2250 cdclk_state->actual = cdclk_state->logical; in bdw_modeset_calc_cdclk()
2258 struct intel_atomic_state *state = cdclk_state->base.state; in skl_dpll0_vco()
2259 struct drm_i915_private *dev_priv = to_i915(state->base.dev); in skl_dpll0_vco()
2262 int vco, i; in skl_dpll0_vco() local
2264 vco = cdclk_state->logical.vco; in skl_dpll0_vco()
2265 if (!vco) in skl_dpll0_vco()
2266 vco = dev_priv->skl_preferred_vco_freq; in skl_dpll0_vco()
2269 if (!crtc_state->hw.enable) in skl_dpll0_vco()
2276 * DPLL0 VCO may need to be adjusted to get the correct in skl_dpll0_vco()
2279 switch (crtc_state->port_clock / 2) { in skl_dpll0_vco()
2282 vco = 8640000; in skl_dpll0_vco()
2285 vco = 8100000; in skl_dpll0_vco()
2290 return vco; in skl_dpll0_vco()
2295 int min_cdclk, cdclk, vco; in skl_modeset_calc_cdclk() local
2301 vco = skl_dpll0_vco(cdclk_state); in skl_modeset_calc_cdclk()
2307 cdclk = skl_calc_cdclk(min_cdclk, vco); in skl_modeset_calc_cdclk()
2309 cdclk_state->logical.vco = vco; in skl_modeset_calc_cdclk()
2310 cdclk_state->logical.cdclk = cdclk; in skl_modeset_calc_cdclk()
2311 cdclk_state->logical.voltage_level = in skl_modeset_calc_cdclk()
2314 if (!cdclk_state->active_pipes) { in skl_modeset_calc_cdclk()
2315 cdclk = skl_calc_cdclk(cdclk_state->force_min_cdclk, vco); in skl_modeset_calc_cdclk()
2317 cdclk_state->actual.vco = vco; in skl_modeset_calc_cdclk()
2318 cdclk_state->actual.cdclk = cdclk; in skl_modeset_calc_cdclk()
2319 cdclk_state->actual.voltage_level = in skl_modeset_calc_cdclk()
2322 cdclk_state->actual = cdclk_state->logical; in skl_modeset_calc_cdclk()
2330 struct intel_atomic_state *state = cdclk_state->base.state; in bxt_modeset_calc_cdclk()
2331 struct drm_i915_private *dev_priv = to_i915(state->base.dev); in bxt_modeset_calc_cdclk()
2332 int min_cdclk, min_voltage_level, cdclk, vco; in bxt_modeset_calc_cdclk() local
2343 vco = bxt_calc_cdclk_pll_vco(dev_priv, cdclk); in bxt_modeset_calc_cdclk()
2345 cdclk_state->logical.vco = vco; in bxt_modeset_calc_cdclk()
2346 cdclk_state->logical.cdclk = cdclk; in bxt_modeset_calc_cdclk()
2347 cdclk_state->logical.voltage_level = in bxt_modeset_calc_cdclk()
2349 dev_priv->display.calc_voltage_level(cdclk)); in bxt_modeset_calc_cdclk()
2351 if (!cdclk_state->active_pipes) { in bxt_modeset_calc_cdclk()
2352 cdclk = bxt_calc_cdclk(dev_priv, cdclk_state->force_min_cdclk); in bxt_modeset_calc_cdclk()
2353 vco = bxt_calc_cdclk_pll_vco(dev_priv, cdclk); in bxt_modeset_calc_cdclk()
2355 cdclk_state->actual.vco = vco; in bxt_modeset_calc_cdclk()
2356 cdclk_state->actual.cdclk = cdclk; in bxt_modeset_calc_cdclk()
2357 cdclk_state->actual.voltage_level = in bxt_modeset_calc_cdclk()
2358 dev_priv->display.calc_voltage_level(cdclk); in bxt_modeset_calc_cdclk()
2360 cdclk_state->actual = cdclk_state->logical; in bxt_modeset_calc_cdclk()
2368 struct drm_i915_private *dev_priv = to_i915(state->base.dev); in intel_modeset_all_pipes()
2375 for_each_intel_crtc(&dev_priv->drm, crtc) { in intel_modeset_all_pipes()
2379 crtc_state = intel_atomic_get_crtc_state(&state->base, crtc); in intel_modeset_all_pipes()
2383 if (!crtc_state->hw.active || in intel_modeset_all_pipes()
2384 drm_atomic_crtc_needs_modeset(&crtc_state->uapi)) in intel_modeset_all_pipes()
2387 crtc_state->uapi.mode_changed = true; in intel_modeset_all_pipes()
2389 ret = drm_atomic_add_affected_connectors(&state->base, in intel_modeset_all_pipes()
2390 &crtc->base); in intel_modeset_all_pipes()
2394 ret = drm_atomic_add_affected_planes(&state->base, in intel_modeset_all_pipes()
2395 &crtc->base); in intel_modeset_all_pipes()
2399 crtc_state->update_planes |= crtc_state->active_planes; in intel_modeset_all_pipes()
2425 cdclk_state = kmemdup(obj->state, sizeof(*cdclk_state), GFP_KERNEL); in intel_cdclk_duplicate_state()
2429 cdclk_state->pipe = INVALID_PIPE; in intel_cdclk_duplicate_state()
2431 return &cdclk_state->base; in intel_cdclk_duplicate_state()
2448 struct drm_i915_private *dev_priv = to_i915(state->base.dev); in intel_atomic_get_cdclk_state()
2451 cdclk_state = intel_atomic_get_global_obj_state(state, &dev_priv->cdclk.obj); in intel_atomic_get_cdclk_state()
2464 return -ENOMEM; in intel_cdclk_init()
2466 intel_atomic_global_obj_init(dev_priv, &dev_priv->cdclk.obj, in intel_cdclk_init()
2467 &cdclk_state->base, &intel_cdclk_funcs); in intel_cdclk_init()
2474 struct drm_i915_private *dev_priv = to_i915(state->base.dev); in intel_modeset_calc_cdclk()
2486 new_cdclk_state->active_pipes = in intel_modeset_calc_cdclk()
2487 intel_calc_active_pipes(state, old_cdclk_state->active_pipes); in intel_modeset_calc_cdclk()
2489 ret = dev_priv->display.modeset_calc_cdclk(new_cdclk_state); in intel_modeset_calc_cdclk()
2493 if (intel_cdclk_changed(&old_cdclk_state->actual, in intel_modeset_calc_cdclk()
2494 &new_cdclk_state->actual)) { in intel_modeset_calc_cdclk()
2499 ret = intel_atomic_serialize_global_state(&new_cdclk_state->base); in intel_modeset_calc_cdclk()
2502 } else if (old_cdclk_state->active_pipes != new_cdclk_state->active_pipes || in intel_modeset_calc_cdclk()
2503 old_cdclk_state->force_min_cdclk != new_cdclk_state->force_min_cdclk || in intel_modeset_calc_cdclk()
2504 intel_cdclk_changed(&old_cdclk_state->logical, in intel_modeset_calc_cdclk()
2505 &new_cdclk_state->logical)) { in intel_modeset_calc_cdclk()
2506 ret = intel_atomic_lock_global_state(&new_cdclk_state->base); in intel_modeset_calc_cdclk()
2513 if (is_power_of_2(new_cdclk_state->active_pipes) && in intel_modeset_calc_cdclk()
2515 &old_cdclk_state->actual, in intel_modeset_calc_cdclk()
2516 &new_cdclk_state->actual)) { in intel_modeset_calc_cdclk()
2520 pipe = ilog2(new_cdclk_state->active_pipes); in intel_modeset_calc_cdclk()
2523 crtc_state = intel_atomic_get_crtc_state(&state->base, crtc); in intel_modeset_calc_cdclk()
2527 if (drm_atomic_crtc_needs_modeset(&crtc_state->uapi)) in intel_modeset_calc_cdclk()
2534 new_cdclk_state->pipe = pipe; in intel_modeset_calc_cdclk()
2536 drm_dbg_kms(&dev_priv->drm, in intel_modeset_calc_cdclk()
2539 } else if (intel_cdclk_needs_modeset(&old_cdclk_state->actual, in intel_modeset_calc_cdclk()
2540 &new_cdclk_state->actual)) { in intel_modeset_calc_cdclk()
2546 new_cdclk_state->pipe = INVALID_PIPE; in intel_modeset_calc_cdclk()
2548 drm_dbg_kms(&dev_priv->drm, in intel_modeset_calc_cdclk()
2552 drm_dbg_kms(&dev_priv->drm, in intel_modeset_calc_cdclk()
2554 new_cdclk_state->logical.cdclk, in intel_modeset_calc_cdclk()
2555 new_cdclk_state->actual.cdclk); in intel_modeset_calc_cdclk()
2556 drm_dbg_kms(&dev_priv->drm, in intel_modeset_calc_cdclk()
2558 new_cdclk_state->logical.voltage_level, in intel_modeset_calc_cdclk()
2559 new_cdclk_state->actual.voltage_level); in intel_modeset_calc_cdclk()
2566 int max_cdclk_freq = dev_priv->max_cdclk_freq; in intel_compute_max_dotclk()
2582 * intel_update_max_cdclk - Determine the maximum support CDCLK frequency
2592 if (dev_priv->cdclk.hw.ref == 24000) in intel_update_max_cdclk()
2593 dev_priv->max_cdclk_freq = 552000; in intel_update_max_cdclk()
2595 dev_priv->max_cdclk_freq = 556800; in intel_update_max_cdclk()
2597 if (dev_priv->cdclk.hw.ref == 24000) in intel_update_max_cdclk()
2598 dev_priv->max_cdclk_freq = 648000; in intel_update_max_cdclk()
2600 dev_priv->max_cdclk_freq = 652800; in intel_update_max_cdclk()
2602 dev_priv->max_cdclk_freq = 528000; in intel_update_max_cdclk()
2605 int max_cdclk, vco; in intel_update_max_cdclk() local
2607 vco = dev_priv->skl_preferred_vco_freq; in intel_update_max_cdclk()
2608 drm_WARN_ON(&dev_priv->drm, vco != 8100000 && vco != 8640000); in intel_update_max_cdclk()
2611 * Use the lower (vco 8640) cdclk values as a in intel_update_max_cdclk()
2613 * if the preferred vco is 8100 instead. in intel_update_max_cdclk()
2624 dev_priv->max_cdclk_freq = skl_calc_cdclk(max_cdclk, vco); in intel_update_max_cdclk()
2626 dev_priv->max_cdclk_freq = 316800; in intel_update_max_cdclk()
2628 dev_priv->max_cdclk_freq = 624000; in intel_update_max_cdclk()
2637 dev_priv->max_cdclk_freq = 450000; in intel_update_max_cdclk()
2639 dev_priv->max_cdclk_freq = 450000; in intel_update_max_cdclk()
2641 dev_priv->max_cdclk_freq = 540000; in intel_update_max_cdclk()
2643 dev_priv->max_cdclk_freq = 675000; in intel_update_max_cdclk()
2645 dev_priv->max_cdclk_freq = 320000; in intel_update_max_cdclk()
2647 dev_priv->max_cdclk_freq = 400000; in intel_update_max_cdclk()
2650 dev_priv->max_cdclk_freq = dev_priv->cdclk.hw.cdclk; in intel_update_max_cdclk()
2653 dev_priv->max_dotclk_freq = intel_compute_max_dotclk(dev_priv); in intel_update_max_cdclk()
2655 drm_dbg(&dev_priv->drm, "Max CD clock rate: %d kHz\n", in intel_update_max_cdclk()
2656 dev_priv->max_cdclk_freq); in intel_update_max_cdclk()
2658 drm_dbg(&dev_priv->drm, "Max dotclock rate: %d kHz\n", in intel_update_max_cdclk()
2659 dev_priv->max_dotclk_freq); in intel_update_max_cdclk()
2663 * intel_update_cdclk - Determine the current CDCLK frequency
2670 dev_priv->display.get_cdclk(dev_priv, &dev_priv->cdclk.hw); in intel_update_cdclk()
2680 DIV_ROUND_UP(dev_priv->cdclk.hw.cdclk, 1000)); in intel_update_cdclk()
2703 fraction) - 1); in cnp_rawclk()
2781 * intel_read_rawclk - Determine the current RAWCLK frequency
2807 * intel_init_cdclk_hooks - Initialize CDCLK related modesetting hooks
2813 dev_priv->display.set_cdclk = bxt_set_cdclk; in intel_init_cdclk_hooks()
2814 dev_priv->display.bw_calc_min_cdclk = skl_bw_calc_min_cdclk; in intel_init_cdclk_hooks()
2815 dev_priv->display.modeset_calc_cdclk = bxt_modeset_calc_cdclk; in intel_init_cdclk_hooks()
2816 dev_priv->display.calc_voltage_level = tgl_calc_voltage_level; in intel_init_cdclk_hooks()
2817 dev_priv->cdclk.table = icl_cdclk_table; in intel_init_cdclk_hooks()
2819 dev_priv->display.set_cdclk = bxt_set_cdclk; in intel_init_cdclk_hooks()
2820 dev_priv->display.bw_calc_min_cdclk = skl_bw_calc_min_cdclk; in intel_init_cdclk_hooks()
2821 dev_priv->display.modeset_calc_cdclk = bxt_modeset_calc_cdclk; in intel_init_cdclk_hooks()
2822 dev_priv->display.calc_voltage_level = ehl_calc_voltage_level; in intel_init_cdclk_hooks()
2823 dev_priv->cdclk.table = icl_cdclk_table; in intel_init_cdclk_hooks()
2825 dev_priv->display.set_cdclk = bxt_set_cdclk; in intel_init_cdclk_hooks()
2826 dev_priv->display.bw_calc_min_cdclk = skl_bw_calc_min_cdclk; in intel_init_cdclk_hooks()
2827 dev_priv->display.modeset_calc_cdclk = bxt_modeset_calc_cdclk; in intel_init_cdclk_hooks()
2828 dev_priv->display.calc_voltage_level = icl_calc_voltage_level; in intel_init_cdclk_hooks()
2829 dev_priv->cdclk.table = icl_cdclk_table; in intel_init_cdclk_hooks()
2831 dev_priv->display.bw_calc_min_cdclk = skl_bw_calc_min_cdclk; in intel_init_cdclk_hooks()
2832 dev_priv->display.set_cdclk = bxt_set_cdclk; in intel_init_cdclk_hooks()
2833 dev_priv->display.modeset_calc_cdclk = bxt_modeset_calc_cdclk; in intel_init_cdclk_hooks()
2834 dev_priv->display.calc_voltage_level = cnl_calc_voltage_level; in intel_init_cdclk_hooks()
2835 dev_priv->cdclk.table = cnl_cdclk_table; in intel_init_cdclk_hooks()
2837 dev_priv->display.bw_calc_min_cdclk = skl_bw_calc_min_cdclk; in intel_init_cdclk_hooks()
2838 dev_priv->display.set_cdclk = bxt_set_cdclk; in intel_init_cdclk_hooks()
2839 dev_priv->display.modeset_calc_cdclk = bxt_modeset_calc_cdclk; in intel_init_cdclk_hooks()
2840 dev_priv->display.calc_voltage_level = bxt_calc_voltage_level; in intel_init_cdclk_hooks()
2842 dev_priv->cdclk.table = glk_cdclk_table; in intel_init_cdclk_hooks()
2844 dev_priv->cdclk.table = bxt_cdclk_table; in intel_init_cdclk_hooks()
2846 dev_priv->display.bw_calc_min_cdclk = skl_bw_calc_min_cdclk; in intel_init_cdclk_hooks()
2847 dev_priv->display.set_cdclk = skl_set_cdclk; in intel_init_cdclk_hooks()
2848 dev_priv->display.modeset_calc_cdclk = skl_modeset_calc_cdclk; in intel_init_cdclk_hooks()
2850 dev_priv->display.bw_calc_min_cdclk = intel_bw_calc_min_cdclk; in intel_init_cdclk_hooks()
2851 dev_priv->display.set_cdclk = bdw_set_cdclk; in intel_init_cdclk_hooks()
2852 dev_priv->display.modeset_calc_cdclk = bdw_modeset_calc_cdclk; in intel_init_cdclk_hooks()
2854 dev_priv->display.bw_calc_min_cdclk = intel_bw_calc_min_cdclk; in intel_init_cdclk_hooks()
2855 dev_priv->display.set_cdclk = chv_set_cdclk; in intel_init_cdclk_hooks()
2856 dev_priv->display.modeset_calc_cdclk = vlv_modeset_calc_cdclk; in intel_init_cdclk_hooks()
2858 dev_priv->display.bw_calc_min_cdclk = intel_bw_calc_min_cdclk; in intel_init_cdclk_hooks()
2859 dev_priv->display.set_cdclk = vlv_set_cdclk; in intel_init_cdclk_hooks()
2860 dev_priv->display.modeset_calc_cdclk = vlv_modeset_calc_cdclk; in intel_init_cdclk_hooks()
2862 dev_priv->display.bw_calc_min_cdclk = intel_bw_calc_min_cdclk; in intel_init_cdclk_hooks()
2863 dev_priv->display.modeset_calc_cdclk = fixed_modeset_calc_cdclk; in intel_init_cdclk_hooks()
2867 dev_priv->display.get_cdclk = bxt_get_cdclk; in intel_init_cdclk_hooks()
2869 dev_priv->display.get_cdclk = skl_get_cdclk; in intel_init_cdclk_hooks()
2871 dev_priv->display.get_cdclk = bdw_get_cdclk; in intel_init_cdclk_hooks()
2873 dev_priv->display.get_cdclk = hsw_get_cdclk; in intel_init_cdclk_hooks()
2875 dev_priv->display.get_cdclk = vlv_get_cdclk; in intel_init_cdclk_hooks()
2877 dev_priv->display.get_cdclk = fixed_400mhz_get_cdclk; in intel_init_cdclk_hooks()
2879 dev_priv->display.get_cdclk = fixed_450mhz_get_cdclk; in intel_init_cdclk_hooks()
2881 dev_priv->display.get_cdclk = gm45_get_cdclk; in intel_init_cdclk_hooks()
2883 dev_priv->display.get_cdclk = g33_get_cdclk; in intel_init_cdclk_hooks()
2885 dev_priv->display.get_cdclk = i965gm_get_cdclk; in intel_init_cdclk_hooks()
2887 dev_priv->display.get_cdclk = fixed_400mhz_get_cdclk; in intel_init_cdclk_hooks()
2889 dev_priv->display.get_cdclk = pnv_get_cdclk; in intel_init_cdclk_hooks()
2891 dev_priv->display.get_cdclk = g33_get_cdclk; in intel_init_cdclk_hooks()
2893 dev_priv->display.get_cdclk = i945gm_get_cdclk; in intel_init_cdclk_hooks()
2895 dev_priv->display.get_cdclk = fixed_400mhz_get_cdclk; in intel_init_cdclk_hooks()
2897 dev_priv->display.get_cdclk = i915gm_get_cdclk; in intel_init_cdclk_hooks()
2899 dev_priv->display.get_cdclk = fixed_333mhz_get_cdclk; in intel_init_cdclk_hooks()
2901 dev_priv->display.get_cdclk = fixed_266mhz_get_cdclk; in intel_init_cdclk_hooks()
2903 dev_priv->display.get_cdclk = i85x_get_cdclk; in intel_init_cdclk_hooks()
2905 dev_priv->display.get_cdclk = fixed_200mhz_get_cdclk; in intel_init_cdclk_hooks()
2907 dev_priv->display.get_cdclk = fixed_133mhz_get_cdclk; in intel_init_cdclk_hooks()
2909 if (drm_WARN(&dev_priv->drm, !dev_priv->display.get_cdclk, in intel_init_cdclk_hooks()
2911 dev_priv->display.get_cdclk = fixed_133mhz_get_cdclk; in intel_init_cdclk_hooks()