36  * are two main clocks involved that aren't directly related to the actual
37  * pixel clock or any symbol/bit clock of the actual output port. These
464 		 * Specs are full of misinformation, but testing on actual  in vlv_calc_voltage_level()
1931 	if (!intel_cdclk_changed(&old_cdclk_state->actual,  in intel_set_cdclk_pre_plane_update()
1932 				 &new_cdclk_state->actual))  in intel_set_cdclk_pre_plane_update()
1936 	    old_cdclk_state->actual.cdclk <= new_cdclk_state->actual.cdclk) {  in intel_set_cdclk_pre_plane_update()
1939 		intel_set_cdclk(dev_priv, &new_cdclk_state->actual, pipe);  in intel_set_cdclk_pre_plane_update()
1960 	if (!intel_cdclk_changed(&old_cdclk_state->actual,  in intel_set_cdclk_post_plane_update()
1961 				 &new_cdclk_state->actual))  in intel_set_cdclk_post_plane_update()
1965 	    old_cdclk_state->actual.cdclk > new_cdclk_state->actual.cdclk) {  in intel_set_cdclk_post_plane_update()
1968 		intel_set_cdclk(dev_priv, &new_cdclk_state->actual, pipe);  in intel_set_cdclk_post_plane_update()
2215 		cdclk_state->actual.cdclk = cdclk;  in vlv_modeset_calc_cdclk()
2216 		cdclk_state->actual.voltage_level =  in vlv_modeset_calc_cdclk()
2219 		cdclk_state->actual = cdclk_state->logical;  in vlv_modeset_calc_cdclk()
2246 		cdclk_state->actual.cdclk = cdclk;  in bdw_modeset_calc_cdclk()
2247 		cdclk_state->actual.voltage_level =  in bdw_modeset_calc_cdclk()
2250 		cdclk_state->actual = cdclk_state->logical;  in bdw_modeset_calc_cdclk()
2317 		cdclk_state->actual.vco = vco;  in skl_modeset_calc_cdclk()
2318 		cdclk_state->actual.cdclk = cdclk;  in skl_modeset_calc_cdclk()
2319 		cdclk_state->actual.voltage_level =  in skl_modeset_calc_cdclk()
2322 		cdclk_state->actual = cdclk_state->logical;  in skl_modeset_calc_cdclk()
2355 		cdclk_state->actual.vco = vco;  in bxt_modeset_calc_cdclk()
2356 		cdclk_state->actual.cdclk = cdclk;  in bxt_modeset_calc_cdclk()
2357 		cdclk_state->actual.voltage_level =  in bxt_modeset_calc_cdclk()
2360 		cdclk_state->actual = cdclk_state->logical;  in bxt_modeset_calc_cdclk()
2412 	 * the actual cdclk frequency.  in fixed_modeset_calc_cdclk()
2493 	if (intel_cdclk_changed(&old_cdclk_state->actual,  in intel_modeset_calc_cdclk()
2494 				&new_cdclk_state->actual)) {  in intel_modeset_calc_cdclk()
2497 		 * if the actual hw needs to be poked.  in intel_modeset_calc_cdclk()
2515 					&old_cdclk_state->actual,  in intel_modeset_calc_cdclk()
2516 					&new_cdclk_state->actual)) {  in intel_modeset_calc_cdclk()
2539 	} else if (intel_cdclk_needs_modeset(&old_cdclk_state->actual,  in intel_modeset_calc_cdclk()
2540 					     &new_cdclk_state->actual)) {  in intel_modeset_calc_cdclk()
2553 		    "New cdclk calculated to be logical %u kHz, actual %u kHz\n",  in intel_modeset_calc_cdclk()
2555 		    new_cdclk_state->actual.cdclk);  in intel_modeset_calc_cdclk()
2557 		    "New voltage level calculated to be logical %u, actual %u\n",  in intel_modeset_calc_cdclk()
2559 		    new_cdclk_state->actual.voltage_level);  in intel_modeset_calc_cdclk()
2732 	 * straps, not the actual FSB frequency. Some BIOSen  in i9xx_hrawclk()
2734 	 * read out the actual FSB frequency but sadly we  in i9xx_hrawclk()