105 	u32 dpll = 0, fp = 0, dspcntr, pipeconf;  in psb_intel_crtc_mode_set()  local
152 	dpll = DPLL_VGA_MODE_DIS;  in psb_intel_crtc_mode_set()
154 		dpll |= DPLLB_MODE_LVDS;  in psb_intel_crtc_mode_set()
155 		dpll |= DPLL_DVO_HIGH_SPEED;  in psb_intel_crtc_mode_set()
157 		dpll |= DPLLB_MODE_DAC_SERIAL;  in psb_intel_crtc_mode_set()
161 		dpll |= DPLL_DVO_HIGH_SPEED;  in psb_intel_crtc_mode_set()
162 		dpll |=  in psb_intel_crtc_mode_set()
167 	dpll |= (1 << (clock.p1 - 1)) << 16;  in psb_intel_crtc_mode_set()
170 		dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_5;  in psb_intel_crtc_mode_set()
173 		dpll |= DPLLB_LVDS_P2_CLOCK_DIV_7;  in psb_intel_crtc_mode_set()
176 		dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_10;  in psb_intel_crtc_mode_set()
179 		dpll |= DPLLB_LVDS_P2_CLOCK_DIV_14;  in psb_intel_crtc_mode_set()
185 /*	dpll |= PLL_REF_INPUT_TVCLKINBC; */  in psb_intel_crtc_mode_set()
186 		dpll |= 3;  in psb_intel_crtc_mode_set()
188 	dpll |= PLL_REF_INPUT_DREFCLK;  in psb_intel_crtc_mode_set()
203 	dpll |= DPLL_VCO_ENABLE;  in psb_intel_crtc_mode_set()
212 	if (dpll & DPLL_VCO_ENABLE) {  in psb_intel_crtc_mode_set()
214 		REG_WRITE(map->dpll, dpll & ~DPLL_VCO_ENABLE);  in psb_intel_crtc_mode_set()
215 		REG_READ(map->dpll);  in psb_intel_crtc_mode_set()
249 	REG_WRITE(map->dpll, dpll);  in psb_intel_crtc_mode_set()
250 	REG_READ(map->dpll);  in psb_intel_crtc_mode_set()
255 	REG_WRITE(map->dpll, dpll);  in psb_intel_crtc_mode_set()
257 	REG_READ(map->dpll);  in psb_intel_crtc_mode_set()
304 	u32 dpll;  in psb_intel_crtc_clock_get()  local
311 		dpll = REG_READ(map->dpll);  in psb_intel_crtc_clock_get()
312 		if ((dpll & DISPLAY_RATE_SELECT_FPA1) == 0)  in psb_intel_crtc_clock_get()
319 		dpll = p->dpll;  in psb_intel_crtc_clock_get()
321 		if ((dpll & DISPLAY_RATE_SELECT_FPA1) == 0)  in psb_intel_crtc_clock_get()
336 		    ffs((dpll &  in psb_intel_crtc_clock_get()
341 		if ((dpll & PLL_REF_INPUT_MASK) ==  in psb_intel_crtc_clock_get()
348 		if (dpll & PLL_P1_DIVIDE_BY_TWO)  in psb_intel_crtc_clock_get()
352 			    ((dpll &  in psb_intel_crtc_clock_get()
356 		if (dpll & PLL_P2_DIVIDE_BY_4)  in psb_intel_crtc_clock_get()