282 	u32 dspcntr, pipeconf, dpll, temp;  in oaktrail_crtc_hdmi_mode_set()  local
291 	/* Disable dpll if necessary */  in oaktrail_crtc_hdmi_mode_set()
292 	dpll = REG_READ(DPLL_CTRL);  in oaktrail_crtc_hdmi_mode_set()
293 	if ((dpll & DPLL_PWRDN) == 0) {  in oaktrail_crtc_hdmi_mode_set()
294 		REG_WRITE(DPLL_CTRL, dpll | (DPLL_PWRDN | DPLL_RESET));  in oaktrail_crtc_hdmi_mode_set()
303 	/* program and enable dpll */  in oaktrail_crtc_hdmi_mode_set()
307 	/* Set the DPLL */  in oaktrail_crtc_hdmi_mode_set()
308 	dpll = REG_READ(DPLL_CTRL);  in oaktrail_crtc_hdmi_mode_set()
309 	dpll &= ~DPLL_PDIV_MASK;  in oaktrail_crtc_hdmi_mode_set()
310 	dpll &= ~(DPLL_PWRDN | DPLL_RESET);  in oaktrail_crtc_hdmi_mode_set()
314 	REG_WRITE(DPLL_CTRL, (dpll | (clock.np << DPLL_PDIV_SHIFT) | DPLL_ENSTAT | DPLL_DITHEN));  in oaktrail_crtc_hdmi_mode_set()
418 		/* Disable dpll */  in oaktrail_crtc_hdmi_dpms()
425 		/* wait for dpll off */  in oaktrail_crtc_hdmi_dpms()
432 		/* Enable dpll */  in oaktrail_crtc_hdmi_dpms()
440 		/* wait for dpll warm up */  in oaktrail_crtc_hdmi_dpms()
744 	/* dpll */  in oaktrail_hdmi_save()
797 	/* dpll */  in oaktrail_hdmi_restore()