37 	struct drm_display_mode *mode;  in tmd_vid_get_config_mode()  local
38 	struct drm_psb_private *dev_priv = dev->dev_private;  in tmd_vid_get_config_mode()
39 	struct oaktrail_timing_info *ti = &dev_priv->gct_data.DTD;  in tmd_vid_get_config_mode()
42 	mode = kzalloc(sizeof(*mode), GFP_KERNEL);  in tmd_vid_get_config_mode()
43 	if (!mode)  in tmd_vid_get_config_mode()
47 		mode->hdisplay = (ti->hactive_hi << 8) | ti->hactive_lo;  in tmd_vid_get_config_mode()
48 		mode->vdisplay = (ti->vactive_hi << 8) | ti->vactive_lo;  in tmd_vid_get_config_mode()
49 		mode->hsync_start = mode->hdisplay + \  in tmd_vid_get_config_mode()
50 				((ti->hsync_offset_hi << 8) | \  in tmd_vid_get_config_mode()
51 				ti->hsync_offset_lo);  in tmd_vid_get_config_mode()
52 		mode->hsync_end = mode->hsync_start + \  in tmd_vid_get_config_mode()
53 				((ti->hsync_pulse_width_hi << 8) | \  in tmd_vid_get_config_mode()
54 				ti->hsync_pulse_width_lo);  in tmd_vid_get_config_mode()
55 		mode->htotal = mode->hdisplay + ((ti->hblank_hi << 8) | \  in tmd_vid_get_config_mode()
56 								ti->hblank_lo);  in tmd_vid_get_config_mode()
57 		mode->vsync_start = \  in tmd_vid_get_config_mode()
58 			mode->vdisplay + ((ti->vsync_offset_hi << 8) | \  in tmd_vid_get_config_mode()
59 						ti->vsync_offset_lo);  in tmd_vid_get_config_mode()
60 		mode->vsync_end = \  in tmd_vid_get_config_mode()
61 			mode->vsync_start + ((ti->vsync_pulse_width_hi << 8) | \  in tmd_vid_get_config_mode()
62 						ti->vsync_pulse_width_lo);  in tmd_vid_get_config_mode()
63 		mode->vtotal = mode->vdisplay + \  in tmd_vid_get_config_mode()
64 				((ti->vblank_hi << 8) | ti->vblank_lo);  in tmd_vid_get_config_mode()
65 		mode->clock = ti->pixel_clock * 10;  in tmd_vid_get_config_mode()
67 		dev_dbg(dev->dev, "hdisplay is %d\n", mode->hdisplay);  in tmd_vid_get_config_mode()
68 		dev_dbg(dev->dev, "vdisplay is %d\n", mode->vdisplay);  in tmd_vid_get_config_mode()
69 		dev_dbg(dev->dev, "HSS is %d\n", mode->hsync_start);  in tmd_vid_get_config_mode()
70 		dev_dbg(dev->dev, "HSE is %d\n", mode->hsync_end);  in tmd_vid_get_config_mode()
71 		dev_dbg(dev->dev, "htotal is %d\n", mode->htotal);  in tmd_vid_get_config_mode()
72 		dev_dbg(dev->dev, "VSS is %d\n", mode->vsync_start);  in tmd_vid_get_config_mode()
73 		dev_dbg(dev->dev, "VSE is %d\n", mode->vsync_end);  in tmd_vid_get_config_mode()
74 		dev_dbg(dev->dev, "vtotal is %d\n", mode->vtotal);  in tmd_vid_get_config_mode()
75 		dev_dbg(dev->dev, "clock is %d\n", mode->clock);  in tmd_vid_get_config_mode()
77 		mode->hdisplay = 480;  in tmd_vid_get_config_mode()
78 		mode->vdisplay = 854;  in tmd_vid_get_config_mode()
79 		mode->hsync_start = 487;  in tmd_vid_get_config_mode()
80 		mode->hsync_end = 490;  in tmd_vid_get_config_mode()
81 		mode->htotal = 499;  in tmd_vid_get_config_mode()
82 		mode->vsync_start = 861;  in tmd_vid_get_config_mode()
83 		mode->vsync_end = 865;  in tmd_vid_get_config_mode()
84 		mode->vtotal = 873;  in tmd_vid_get_config_mode()
85 		mode->clock = 33264;  in tmd_vid_get_config_mode()
88 	drm_mode_set_name(mode);  in tmd_vid_get_config_mode()
89 	drm_mode_set_crtcinfo(mode, 0);  in tmd_vid_get_config_mode()
91 	mode->type |= DRM_MODE_TYPE_PREFERRED;  in tmd_vid_get_config_mode()
93 	return mode;  in tmd_vid_get_config_mode()
101 		return -EINVAL;  in tmd_vid_get_panel_info()
103 	pi->width_mm = TMD_PANEL_WIDTH;  in tmd_vid_get_panel_info()
104 	pi->height_mm = TMD_PANEL_HEIGHT;  in tmd_vid_get_panel_info()
146 	if (dsi_config->dvr_ic_inited)  in mdfld_dsi_tmd_drv_ic_init()
178 	dsi_config->dvr_ic_inited = 1;  in mdfld_dsi_tmd_drv_ic_init()