243 	temp = REG_READ(map->dpll);  in mdfld_disable_crtc()
249 			REG_WRITE(map->dpll, temp);  in mdfld_disable_crtc()
250 			REG_READ(map->dpll);  in mdfld_disable_crtc()
256 				/* gating power of DPLL */  in mdfld_disable_crtc()
257 				REG_WRITE(map->dpll, temp | MDFLD_PWR_GATE_EN);  in mdfld_disable_crtc()
298 		/* Enable the DPLL */  in mdfld_crtc_dpms()
299 		temp = REG_READ(map->dpll);  in mdfld_crtc_dpms()
302 			/* When ungating power of DPLL, needs to wait 0.5us  in mdfld_crtc_dpms()
306 				REG_WRITE(map->dpll, temp);  in mdfld_crtc_dpms()
311 			REG_WRITE(map->dpll, temp);  in mdfld_crtc_dpms()
312 			REG_READ(map->dpll);  in mdfld_crtc_dpms()
316 			REG_WRITE(map->dpll, temp | DPLL_VCO_ENABLE);  in mdfld_crtc_dpms()
317 			REG_READ(map->dpll);  in mdfld_crtc_dpms()
429 		temp = REG_READ(map->dpll);  in mdfld_crtc_dpms()
435 				REG_WRITE(map->dpll, temp);  in mdfld_crtc_dpms()
436 				REG_READ(map->dpll);  in mdfld_crtc_dpms()
649 	u32 dpll = 0, fp = 0;  in mdfld_crtc_mode_set()  local
882 		dpll = REG_READ(map->dpll);  in mdfld_crtc_mode_set()
884 		if (dpll & DPLL_VCO_ENABLE) {  in mdfld_crtc_mode_set()
885 			dpll &= ~DPLL_VCO_ENABLE;  in mdfld_crtc_mode_set()
886 			REG_WRITE(map->dpll, dpll);  in mdfld_crtc_mode_set()
887 			REG_READ(map->dpll);  in mdfld_crtc_mode_set()
889 			/* FIXME jliu7 check the DPLL lock bit PIPEACONF[29] */  in mdfld_crtc_mode_set()
895 			dpll &= ~MDFLD_P1_MASK;  in mdfld_crtc_mode_set()
896 			REG_WRITE(map->dpll, dpll);  in mdfld_crtc_mode_set()
901 		/* When ungating power of DPLL, needs to wait 0.5us before  in mdfld_crtc_mode_set()
903 		if (dpll & MDFLD_PWR_GATE_EN) {  in mdfld_crtc_mode_set()
904 			dpll &= ~MDFLD_PWR_GATE_EN;  in mdfld_crtc_mode_set()
905 			REG_WRITE(map->dpll, dpll);  in mdfld_crtc_mode_set()
909 		dpll = 0;  in mdfld_crtc_mode_set()
912 			dpll |= MDFLD_VCO_SEL;  in mdfld_crtc_mode_set()
918 		dpll |= (1 << (clock.p1 - 2)) << 17;  in mdfld_crtc_mode_set()
921 		dpll = 0x00800000;  in mdfld_crtc_mode_set()
926 	REG_WRITE(map->dpll, dpll);  in mdfld_crtc_mode_set()
930 	dpll |= DPLL_VCO_ENABLE;  in mdfld_crtc_mode_set()
931 	REG_WRITE(map->dpll, dpll);  in mdfld_crtc_mode_set()
932 	REG_READ(map->dpll);  in mdfld_crtc_mode_set()