Lines Matching full:pipe
39 int pipe);
41 static void mdfld_wait_for_HS_DATA_FIFO(struct drm_device *dev, u32 pipe) in mdfld_wait_for_HS_DATA_FIFO() argument
43 u32 gen_fifo_stat_reg = MIPI_GEN_FIFO_STAT_REG(pipe); in mdfld_wait_for_HS_DATA_FIFO()
59 static void mdfld_wait_for_HS_CTRL_FIFO(struct drm_device *dev, u32 pipe) in mdfld_wait_for_HS_CTRL_FIFO() argument
61 u32 gen_fifo_stat_reg = MIPI_GEN_FIFO_STAT_REG(pipe); in mdfld_wait_for_HS_CTRL_FIFO()
76 static void mdfld_wait_for_DPI_CTRL_FIFO(struct drm_device *dev, u32 pipe) in mdfld_wait_for_DPI_CTRL_FIFO() argument
78 u32 gen_fifo_stat_reg = MIPI_GEN_FIFO_STAT_REG(pipe); in mdfld_wait_for_DPI_CTRL_FIFO()
94 static void mdfld_wait_for_SPL_PKG_SENT(struct drm_device *dev, u32 pipe) in mdfld_wait_for_SPL_PKG_SENT() argument
96 u32 intr_stat_reg = MIPI_INTR_STAT_REG(pipe); in mdfld_wait_for_SPL_PKG_SENT()
115 int pipe) in dsi_set_device_ready_state() argument
117 REG_FLD_MOD(MIPI_DEVICE_READY_REG(pipe), !!state, 0, 0); in dsi_set_device_ready_state()
121 int state, int pipe) in dsi_set_pipe_plane_enable_state() argument
127 u32 dspcntr = dev_priv->dspcntr[pipe]; in dsi_set_pipe_plane_enable_state()
130 if (pipe) { in dsi_set_pipe_plane_enable_state()
137 /*Set up pipe */ in dsi_set_pipe_plane_enable_state()
141 dev_err(&dev->pdev->dev, "%s: Pipe enable timeout\n", in dsi_set_pipe_plane_enable_state()
147 u32 dspbase_reg = pipe ? MDFLD_DSPCBASE : MRST_DSPABASE; in dsi_set_pipe_plane_enable_state()
149 /* Put DSI lanes to ULPS to disable pipe */ in dsi_set_pipe_plane_enable_state()
150 REG_FLD_MOD(MIPI_DEVICE_READY_REG(pipe), 2, 2, 1); in dsi_set_pipe_plane_enable_state()
151 REG_READ(MIPI_DEVICE_READY_REG(pipe)); /* posted write? */ in dsi_set_pipe_plane_enable_state()
154 REG_FLD_MOD(MIPI_PORT_CONTROL(pipe), 0, 16, 16); in dsi_set_pipe_plane_enable_state()
155 REG_READ(MIPI_PORT_CONTROL(pipe)); /* posted write? */ in dsi_set_pipe_plane_enable_state()
164 /* Disable PIPE */ in dsi_set_pipe_plane_enable_state()
168 dev_err(&dev->pdev->dev, "%s: Pipe disable timeout\n", in dsi_set_pipe_plane_enable_state()
171 if (REG_BIT_WAIT(MIPI_GEN_FIFO_STAT_REG(pipe), 1, 28)) in dsi_set_pipe_plane_enable_state()
178 int pipe) in mdfld_dsi_configure_down() argument
187 if (!dev_priv->dpi_panel_on[pipe]) { in mdfld_dsi_configure_down()
193 dsi_set_pipe_plane_enable_state(dev, 0, pipe); in mdfld_dsi_configure_down()
194 mdfld_dsi_dpi_shut_down(dpi_output, pipe); in mdfld_dsi_configure_down()
195 dsi_set_device_ready_state(dev, 0, pipe); in mdfld_dsi_configure_down()
199 int pipe) in mdfld_dsi_configure_up() argument
208 if (dev_priv->dpi_panel_on[pipe]) { in mdfld_dsi_configure_up()
214 mdfld_dsi_dpi_shut_down(dpi_output, pipe); in mdfld_dsi_configure_up()
215 dsi_set_device_ready_state(dev, 0, pipe); in mdfld_dsi_configure_up()
217 dsi_set_device_ready_state(dev, 1, pipe); in mdfld_dsi_configure_up()
220 mdfld_dsi_dpi_turn_on(dpi_output, pipe); /* Send turn on command */ in mdfld_dsi_configure_up()
221 dsi_set_pipe_plane_enable_state(dev, 1, pipe); in mdfld_dsi_configure_up()
233 static void mdfld_dsi_tpo_ic_init(struct mdfld_dsi_config *dsi_config, u32 pipe) in mdfld_dsi_tpo_ic_init() argument
237 u32 gen_data_reg = MIPI_HS_GEN_DATA_REG(pipe); in mdfld_dsi_tpo_ic_init()
238 u32 gen_ctrl_reg = MIPI_HS_GEN_CTRL_REG(pipe); in mdfld_dsi_tpo_ic_init()
246 mdfld_wait_for_HS_DATA_FIFO(dev, pipe); in mdfld_dsi_tpo_ic_init()
248 mdfld_wait_for_HS_CTRL_FIFO(dev, pipe); in mdfld_dsi_tpo_ic_init()
252 mdfld_wait_for_HS_DATA_FIFO(dev, pipe); in mdfld_dsi_tpo_ic_init()
254 mdfld_wait_for_HS_CTRL_FIFO(dev, pipe); in mdfld_dsi_tpo_ic_init()
258 mdfld_wait_for_HS_DATA_FIFO(dev, pipe); in mdfld_dsi_tpo_ic_init()
260 mdfld_wait_for_HS_CTRL_FIFO(dev, pipe); in mdfld_dsi_tpo_ic_init()
264 mdfld_wait_for_HS_DATA_FIFO(dev, pipe); in mdfld_dsi_tpo_ic_init()
266 mdfld_wait_for_HS_CTRL_FIFO(dev, pipe); in mdfld_dsi_tpo_ic_init()
270 mdfld_wait_for_HS_DATA_FIFO(dev, pipe); in mdfld_dsi_tpo_ic_init()
272 mdfld_wait_for_HS_DATA_FIFO(dev, pipe); in mdfld_dsi_tpo_ic_init()
274 mdfld_wait_for_HS_CTRL_FIFO(dev, pipe); in mdfld_dsi_tpo_ic_init()
278 mdfld_wait_for_HS_DATA_FIFO(dev, pipe); in mdfld_dsi_tpo_ic_init()
280 mdfld_wait_for_HS_CTRL_FIFO(dev, pipe); in mdfld_dsi_tpo_ic_init()
284 mdfld_wait_for_HS_DATA_FIFO(dev, pipe); in mdfld_dsi_tpo_ic_init()
286 mdfld_wait_for_HS_DATA_FIFO(dev, pipe); in mdfld_dsi_tpo_ic_init()
288 mdfld_wait_for_HS_DATA_FIFO(dev, pipe); in mdfld_dsi_tpo_ic_init()
290 mdfld_wait_for_HS_CTRL_FIFO(dev, pipe); in mdfld_dsi_tpo_ic_init()
294 mdfld_wait_for_HS_DATA_FIFO(dev, pipe); in mdfld_dsi_tpo_ic_init()
296 mdfld_wait_for_HS_DATA_FIFO(dev, pipe); in mdfld_dsi_tpo_ic_init()
298 mdfld_wait_for_HS_DATA_FIFO(dev, pipe); in mdfld_dsi_tpo_ic_init()
300 mdfld_wait_for_HS_DATA_FIFO(dev, pipe); in mdfld_dsi_tpo_ic_init()
302 mdfld_wait_for_HS_CTRL_FIFO(dev, pipe); in mdfld_dsi_tpo_ic_init()
306 mdfld_wait_for_HS_DATA_FIFO(dev, pipe); in mdfld_dsi_tpo_ic_init()
308 mdfld_wait_for_HS_DATA_FIFO(dev, pipe); in mdfld_dsi_tpo_ic_init()
310 mdfld_wait_for_HS_CTRL_FIFO(dev, pipe); in mdfld_dsi_tpo_ic_init()
314 mdfld_wait_for_HS_DATA_FIFO(dev, pipe); in mdfld_dsi_tpo_ic_init()
316 mdfld_wait_for_HS_CTRL_FIFO(dev, pipe); in mdfld_dsi_tpo_ic_init()
320 mdfld_wait_for_HS_DATA_FIFO(dev, pipe); in mdfld_dsi_tpo_ic_init()
322 mdfld_wait_for_HS_DATA_FIFO(dev, pipe); in mdfld_dsi_tpo_ic_init()
324 mdfld_wait_for_HS_DATA_FIFO(dev, pipe); in mdfld_dsi_tpo_ic_init()
326 mdfld_wait_for_HS_DATA_FIFO(dev, pipe); in mdfld_dsi_tpo_ic_init()
328 mdfld_wait_for_HS_DATA_FIFO(dev, pipe); in mdfld_dsi_tpo_ic_init()
330 mdfld_wait_for_HS_CTRL_FIFO(dev, pipe); in mdfld_dsi_tpo_ic_init()
334 mdfld_wait_for_HS_DATA_FIFO(dev, pipe); in mdfld_dsi_tpo_ic_init()
336 mdfld_wait_for_HS_DATA_FIFO(dev, pipe); in mdfld_dsi_tpo_ic_init()
338 mdfld_wait_for_HS_DATA_FIFO(dev, pipe); in mdfld_dsi_tpo_ic_init()
340 mdfld_wait_for_HS_CTRL_FIFO(dev, pipe); in mdfld_dsi_tpo_ic_init()
344 mdfld_wait_for_HS_DATA_FIFO(dev, pipe); in mdfld_dsi_tpo_ic_init()
346 mdfld_wait_for_HS_DATA_FIFO(dev, pipe); in mdfld_dsi_tpo_ic_init()
348 mdfld_wait_for_HS_DATA_FIFO(dev, pipe); in mdfld_dsi_tpo_ic_init()
350 mdfld_wait_for_HS_CTRL_FIFO(dev, pipe); in mdfld_dsi_tpo_ic_init()
354 mdfld_wait_for_HS_DATA_FIFO(dev, pipe); in mdfld_dsi_tpo_ic_init()
356 mdfld_wait_for_HS_DATA_FIFO(dev, pipe); in mdfld_dsi_tpo_ic_init()
358 mdfld_wait_for_HS_DATA_FIFO(dev, pipe); in mdfld_dsi_tpo_ic_init()
360 mdfld_wait_for_HS_DATA_FIFO(dev, pipe); in mdfld_dsi_tpo_ic_init()
362 mdfld_wait_for_HS_DATA_FIFO(dev, pipe); in mdfld_dsi_tpo_ic_init()
364 mdfld_wait_for_HS_DATA_FIFO(dev, pipe); in mdfld_dsi_tpo_ic_init()
366 mdfld_wait_for_HS_DATA_FIFO(dev, pipe); in mdfld_dsi_tpo_ic_init()
368 mdfld_wait_for_HS_DATA_FIFO(dev, pipe); in mdfld_dsi_tpo_ic_init()
370 mdfld_wait_for_HS_DATA_FIFO(dev, pipe); in mdfld_dsi_tpo_ic_init()
372 mdfld_wait_for_HS_DATA_FIFO(dev, pipe); in mdfld_dsi_tpo_ic_init()
374 mdfld_wait_for_HS_DATA_FIFO(dev, pipe); in mdfld_dsi_tpo_ic_init()
376 mdfld_wait_for_HS_DATA_FIFO(dev, pipe); in mdfld_dsi_tpo_ic_init()
378 mdfld_wait_for_HS_DATA_FIFO(dev, pipe); in mdfld_dsi_tpo_ic_init()
380 mdfld_wait_for_HS_CTRL_FIFO(dev, pipe); in mdfld_dsi_tpo_ic_init()
384 mdfld_wait_for_HS_DATA_FIFO(dev, pipe); in mdfld_dsi_tpo_ic_init()
386 mdfld_wait_for_HS_DATA_FIFO(dev, pipe); in mdfld_dsi_tpo_ic_init()
388 mdfld_wait_for_HS_DATA_FIFO(dev, pipe); in mdfld_dsi_tpo_ic_init()
390 mdfld_wait_for_HS_DATA_FIFO(dev, pipe); in mdfld_dsi_tpo_ic_init()
392 mdfld_wait_for_HS_DATA_FIFO(dev, pipe); in mdfld_dsi_tpo_ic_init()
394 mdfld_wait_for_HS_DATA_FIFO(dev, pipe); in mdfld_dsi_tpo_ic_init()
396 mdfld_wait_for_HS_DATA_FIFO(dev, pipe); in mdfld_dsi_tpo_ic_init()
398 mdfld_wait_for_HS_DATA_FIFO(dev, pipe); in mdfld_dsi_tpo_ic_init()
400 mdfld_wait_for_HS_DATA_FIFO(dev, pipe); in mdfld_dsi_tpo_ic_init()
402 mdfld_wait_for_HS_DATA_FIFO(dev, pipe); in mdfld_dsi_tpo_ic_init()
404 mdfld_wait_for_HS_DATA_FIFO(dev, pipe); in mdfld_dsi_tpo_ic_init()
406 mdfld_wait_for_HS_DATA_FIFO(dev, pipe); in mdfld_dsi_tpo_ic_init()
408 mdfld_wait_for_HS_DATA_FIFO(dev, pipe); in mdfld_dsi_tpo_ic_init()
410 mdfld_wait_for_HS_CTRL_FIFO(dev, pipe); in mdfld_dsi_tpo_ic_init()
414 mdfld_wait_for_HS_DATA_FIFO(dev, pipe); in mdfld_dsi_tpo_ic_init()
416 mdfld_wait_for_HS_CTRL_FIFO(dev, pipe); in mdfld_dsi_tpo_ic_init()
471 int pipe) in mdfld_dsi_dpi_controller_init() argument
480 REG_FLD_MOD(MIPI_DEVICE_READY_REG(pipe), 0, 0, 0); in mdfld_dsi_dpi_controller_init()
483 REG_WRITE(MIPI_CTRL_REG(pipe), 0x00000018); in mdfld_dsi_dpi_controller_init()
486 REG_WRITE(MIPI_INTR_EN_REG(pipe), 0xffffffff); in mdfld_dsi_dpi_controller_init()
506 REG_WRITE(MIPI_DSI_FUNC_PRG_REG(pipe), val); in mdfld_dsi_dpi_controller_init()
508 REG_WRITE(MIPI_HS_TX_TIMEOUT_REG(pipe), in mdfld_dsi_dpi_controller_init()
511 REG_WRITE(MIPI_LP_RX_TIMEOUT_REG(pipe), in mdfld_dsi_dpi_controller_init()
515 REG_WRITE(MIPI_TURN_AROUND_TIMEOUT_REG(pipe), in mdfld_dsi_dpi_controller_init()
519 REG_WRITE(MIPI_DEVICE_RESET_TIMER_REG(pipe), in mdfld_dsi_dpi_controller_init()
522 REG_WRITE(MIPI_DPI_RESOLUTION_REG(pipe), in mdfld_dsi_dpi_controller_init()
529 REG_WRITE(MIPI_HSYNC_COUNT_REG(pipe), in mdfld_dsi_dpi_controller_init()
531 REG_WRITE(MIPI_HBP_COUNT_REG(pipe), in mdfld_dsi_dpi_controller_init()
533 REG_WRITE(MIPI_HFP_COUNT_REG(pipe), in mdfld_dsi_dpi_controller_init()
535 REG_WRITE(MIPI_HACTIVE_COUNT_REG(pipe), in mdfld_dsi_dpi_controller_init()
537 REG_WRITE(MIPI_VSYNC_COUNT_REG(pipe), in mdfld_dsi_dpi_controller_init()
539 REG_WRITE(MIPI_VBP_COUNT_REG(pipe), in mdfld_dsi_dpi_controller_init()
541 REG_WRITE(MIPI_VFP_COUNT_REG(pipe), in mdfld_dsi_dpi_controller_init()
544 REG_WRITE(MIPI_HIGH_LOW_SWITCH_COUNT_REG(pipe), 0x46); in mdfld_dsi_dpi_controller_init()
547 REG_WRITE(MIPI_INIT_COUNT_REG(pipe), 0x000007d0); in mdfld_dsi_dpi_controller_init()
551 REG_WRITE(MIPI_VIDEO_MODE_FORMAT_REG(pipe), val); in mdfld_dsi_dpi_controller_init()
553 REG_WRITE(MIPI_EOT_DISABLE_REG(pipe), 0x00000000); in mdfld_dsi_dpi_controller_init()
555 REG_WRITE(MIPI_LP_BYTECLK_REG(pipe), 0x00000004); in mdfld_dsi_dpi_controller_init()
558 if (mdfld_get_panel_type(dev, pipe) == TC35876X) in mdfld_dsi_dpi_controller_init()
559 REG_WRITE(MIPI_DPHY_PARAM_REG(pipe), 0x2A0c6008); in mdfld_dsi_dpi_controller_init()
561 REG_WRITE(MIPI_DPHY_PARAM_REG(pipe), 0x150c3408); in mdfld_dsi_dpi_controller_init()
563 REG_WRITE(MIPI_CLK_LANE_SWITCH_TIME_CNT_REG(pipe), (0xa << 16) | 0x14); in mdfld_dsi_dpi_controller_init()
565 if (mdfld_get_panel_type(dev, pipe) == TC35876X) in mdfld_dsi_dpi_controller_init()
569 REG_FLD_MOD(MIPI_DEVICE_READY_REG(pipe), 1, 0, 0); in mdfld_dsi_dpi_controller_init()
572 void mdfld_dsi_dpi_turn_on(struct mdfld_dsi_dpi_output *output, int pipe) in mdfld_dsi_dpi_turn_on() argument
577 if (REG_READ(MIPI_INTR_STAT_REG(pipe)) & DSI_INTR_STATE_SPL_PKG_SENT) in mdfld_dsi_dpi_turn_on()
578 REG_WRITE(MIPI_INTR_STAT_REG(pipe), in mdfld_dsi_dpi_turn_on()
582 REG_WRITE(MIPI_DPI_CONTROL_REG(pipe), DSI_DPI_CTRL_HS_TURN_ON); in mdfld_dsi_dpi_turn_on()
585 mdfld_wait_for_SPL_PKG_SENT(dev, pipe); in mdfld_dsi_dpi_turn_on()
587 if (REG_READ(MIPI_INTR_STAT_REG(pipe)) & DSI_INTR_STATE_SPL_PKG_SENT) in mdfld_dsi_dpi_turn_on()
588 REG_WRITE(MIPI_INTR_STAT_REG(pipe), in mdfld_dsi_dpi_turn_on()
595 if (pipe == 2) in mdfld_dsi_dpi_turn_on()
597 else if (pipe == 0) in mdfld_dsi_dpi_turn_on()
602 int pipe) in mdfld_dsi_dpi_shut_down() argument
613 mdfld_wait_for_DPI_CTRL_FIFO(dev, pipe); in mdfld_dsi_dpi_shut_down()
616 if (REG_READ(MIPI_INTR_STAT_REG(pipe)) & DSI_INTR_STATE_SPL_PKG_SENT) in mdfld_dsi_dpi_shut_down()
617 REG_WRITE(MIPI_INTR_STAT_REG(pipe), in mdfld_dsi_dpi_shut_down()
620 if (REG_READ(MIPI_DPI_CONTROL_REG(pipe)) == DSI_DPI_CTRL_HS_SHUTDOWN) in mdfld_dsi_dpi_shut_down()
623 REG_WRITE(MIPI_DPI_CONTROL_REG(pipe), DSI_DPI_CTRL_HS_SHUTDOWN); in mdfld_dsi_dpi_shut_down()
631 if (pipe == 2) in mdfld_dsi_dpi_shut_down()
633 else if (pipe == 0) in mdfld_dsi_dpi_shut_down()
644 int pipe = mdfld_dsi_encoder_get_pipe(dsi_encoder); in mdfld_dsi_dpi_set_power() local
653 if (mdfld_get_panel_type(dev, pipe) == TMD_VID) in mdfld_dsi_dpi_set_power()
654 mdfld_dsi_dpi_turn_on(dpi_output, pipe); in mdfld_dsi_dpi_set_power()
655 else if (mdfld_get_panel_type(dev, pipe) == TC35876X) in mdfld_dsi_dpi_set_power()
656 mdfld_dsi_configure_up(dsi_encoder, pipe); in mdfld_dsi_dpi_set_power()
659 REG_WRITE(MIPI_PORT_CONTROL(pipe), in mdfld_dsi_dpi_set_power()
660 REG_READ(MIPI_PORT_CONTROL(pipe)) | BIT(31)); in mdfld_dsi_dpi_set_power()
661 REG_READ(MIPI_PORT_CONTROL(pipe)); in mdfld_dsi_dpi_set_power()
663 mdfld_dsi_dpi_turn_on(dpi_output, pipe); in mdfld_dsi_dpi_set_power()
664 mdfld_dsi_tpo_ic_init(dsi_config, pipe); in mdfld_dsi_dpi_set_power()
666 dev_priv->dpi_panel_on[pipe] = true; in mdfld_dsi_dpi_set_power()
668 if (mdfld_get_panel_type(dev, pipe) == TMD_VID) in mdfld_dsi_dpi_set_power()
669 mdfld_dsi_dpi_shut_down(dpi_output, pipe); in mdfld_dsi_dpi_set_power()
670 else if (mdfld_get_panel_type(dev, pipe) == TC35876X) in mdfld_dsi_dpi_set_power()
671 mdfld_dsi_configure_down(dsi_encoder, pipe); in mdfld_dsi_dpi_set_power()
673 mdfld_dsi_dpi_shut_down(dpi_output, pipe); in mdfld_dsi_dpi_set_power()
676 REG_WRITE(MIPI_PORT_CONTROL(pipe), in mdfld_dsi_dpi_set_power()
677 REG_READ(MIPI_PORT_CONTROL(pipe)) & ~BIT(31)); in mdfld_dsi_dpi_set_power()
678 REG_READ(MIPI_PORT_CONTROL(pipe)); in mdfld_dsi_dpi_set_power()
680 dev_priv->dpi_panel_on[pipe] = false; in mdfld_dsi_dpi_set_power()
727 static void mipi_set_properties(struct mdfld_dsi_config *dsi_config, int pipe) in mipi_set_properties() argument
731 REG_WRITE(MIPI_CTRL_REG(pipe), 0x00000018); in mipi_set_properties()
732 REG_WRITE(MIPI_INTR_EN_REG(pipe), 0xffffffff); in mipi_set_properties()
733 REG_WRITE(MIPI_HS_TX_TIMEOUT_REG(pipe), 0xffffff); in mipi_set_properties()
734 REG_WRITE(MIPI_LP_RX_TIMEOUT_REG(pipe), 0xffffff); in mipi_set_properties()
735 REG_WRITE(MIPI_TURN_AROUND_TIMEOUT_REG(pipe), 0x14); in mipi_set_properties()
736 REG_WRITE(MIPI_DEVICE_RESET_TIMER_REG(pipe), 0xff); in mipi_set_properties()
737 REG_WRITE(MIPI_HIGH_LOW_SWITCH_COUNT_REG(pipe), 0x25); in mipi_set_properties()
738 REG_WRITE(MIPI_INIT_COUNT_REG(pipe), 0xf0); in mipi_set_properties()
739 REG_WRITE(MIPI_EOT_DISABLE_REG(pipe), 0x00000000); in mipi_set_properties()
740 REG_WRITE(MIPI_LP_BYTECLK_REG(pipe), 0x00000004); in mipi_set_properties()
741 REG_WRITE(MIPI_DBI_BW_CTRL_REG(pipe), 0x00000820); in mipi_set_properties()
742 REG_WRITE(MIPI_CLK_LANE_SWITCH_TIME_CNT_REG(pipe), (0xa << 16) | 0x14); in mipi_set_properties()
746 int pipe) in mdfld_mipi_set_video_timing() argument
756 REG_WRITE(MIPI_DPI_RESOLUTION_REG(pipe), in mdfld_mipi_set_video_timing()
758 REG_WRITE(MIPI_HSYNC_COUNT_REG(pipe), in mdfld_mipi_set_video_timing()
760 REG_WRITE(MIPI_HBP_COUNT_REG(pipe), in mdfld_mipi_set_video_timing()
762 REG_WRITE(MIPI_HFP_COUNT_REG(pipe), in mdfld_mipi_set_video_timing()
764 REG_WRITE(MIPI_HACTIVE_COUNT_REG(pipe), in mdfld_mipi_set_video_timing()
766 REG_WRITE(MIPI_VSYNC_COUNT_REG(pipe), in mdfld_mipi_set_video_timing()
768 REG_WRITE(MIPI_VBP_COUNT_REG(pipe), in mdfld_mipi_set_video_timing()
770 REG_WRITE(MIPI_VFP_COUNT_REG(pipe), in mdfld_mipi_set_video_timing()
774 static void mdfld_mipi_config(struct mdfld_dsi_config *dsi_config, int pipe) in mdfld_mipi_config() argument
779 if (pipe) { in mdfld_mipi_config()
787 REG_WRITE(MIPI_DPHY_PARAM_REG(pipe), 0x150A600F); in mdfld_mipi_config()
788 REG_WRITE(MIPI_VIDEO_MODE_FORMAT_REG(pipe), 0x0000000F); in mdfld_mipi_config()
791 REG_WRITE(MIPI_DSI_FUNC_PRG_REG(pipe), 0x00000200 | lane_count); in mdfld_mipi_config()
793 mdfld_mipi_set_video_timing(dsi_config, pipe); in mdfld_mipi_config()
796 static void mdfld_set_pipe_timing(struct mdfld_dsi_config *dsi_config, int pipe) in mdfld_set_pipe_timing() argument
827 int pipe = mdfld_dsi_encoder_get_pipe(dsi_encoder); in mdfld_dsi_dpi_mode_set() local
834 if (WARN_ON(pipe < 0)) in mdfld_dsi_dpi_mode_set()
837 pipeconf = dev_priv->pipeconf[pipe]; in mdfld_dsi_dpi_mode_set()
838 dspcntr = dev_priv->dspcntr[pipe]; in mdfld_dsi_dpi_mode_set()
840 if (pipe) { in mdfld_dsi_dpi_mode_set()
844 if (mdfld_get_panel_type(dev, pipe) == TC35876X) in mdfld_dsi_dpi_mode_set()
854 if (mdfld_get_panel_type(dev, pipe) == TC35876X) { in mdfld_dsi_dpi_mode_set()
873 REG_WRITE(MIPI_DPHY_PARAM_REG(pipe), 0x2A0c6008); in mdfld_dsi_dpi_mode_set()
875 mipi_set_properties(dsi_config, pipe); in mdfld_dsi_dpi_mode_set()
876 mdfld_mipi_config(dsi_config, pipe); in mdfld_dsi_dpi_mode_set()
877 mdfld_set_pipe_timing(dsi_config, pipe); in mdfld_dsi_dpi_mode_set()
889 REG_WRITE(MIPI_PORT_CONTROL(pipe), 0x80810000); in mdfld_dsi_dpi_mode_set()
892 REG_WRITE(MIPI_PORT_CONTROL(pipe), mipi); in mdfld_dsi_dpi_mode_set()
894 REG_READ(MIPI_PORT_CONTROL(pipe)); in mdfld_dsi_dpi_mode_set()
896 if (mdfld_get_panel_type(dev, pipe) == TMD_VID) { in mdfld_dsi_dpi_mode_set()
898 } else if (mdfld_get_panel_type(dev, pipe) == TC35876X) { in mdfld_dsi_dpi_mode_set()
900 mdfld_dsi_dpi_controller_init(dsi_config, pipe); in mdfld_dsi_dpi_mode_set()
904 dev_priv->dpi_panel_on[pipe] = true; in mdfld_dsi_dpi_mode_set()
907 mdfld_dsi_dpi_turn_on(dpi_output, pipe); in mdfld_dsi_dpi_mode_set()
910 /*set up pipe*/ in mdfld_dsi_dpi_mode_set()
920 if (mdfld_get_panel_type(dev, pipe) == TMD_VID) { in mdfld_dsi_dpi_mode_set()
922 } else if (mdfld_get_panel_type(dev, pipe) == TC35876X) { in mdfld_dsi_dpi_mode_set()
923 mdfld_dsi_dpi_turn_on(dpi_output, pipe); in mdfld_dsi_dpi_mode_set()
926 mdfld_dsi_tpo_ic_init(dsi_config, pipe); in mdfld_dsi_dpi_mode_set()
928 mdfld_dsi_brightness_init(dsi_config, pipe); in mdfld_dsi_dpi_mode_set()
947 int pipe; in mdfld_dsi_dpi_init() local
951 pipe = dsi_connector->pipe; in mdfld_dsi_dpi_init()
953 if (mdfld_get_panel_type(dev, pipe) != TC35876X) { in mdfld_dsi_dpi_init()
958 ret = p_funcs->reset(dev, pipe); in mdfld_dsi_dpi_init()
960 DRM_ERROR("Panel %d hard-reset failed\n", pipe); in mdfld_dsi_dpi_init()
967 p_funcs->drv_ic_init(dsi_config, pipe); in mdfld_dsi_dpi_init()
972 DRM_ERROR("Panel %d get power mode failed\n", pipe); in mdfld_dsi_dpi_init()
975 DRM_INFO("pipe %d power mode 0x%x\n", pipe, data); in mdfld_dsi_dpi_init()
988 if (mdfld_get_panel_type(dev, pipe) != TC35876X) in mdfld_dsi_dpi_init()
1006 if (dsi_connector->pipe) { in mdfld_dsi_dpi_init()