Lines Matching full:dpll
188 pipe->dpll = PSB_RVDC32(map->dpll); in mdfld_save_display_registers()
242 u32 dpll; in mdfld_restore_display_registers() local
249 u32 dpll_val = pipe->dpll; in mdfld_restore_display_registers()
274 PSB_WVDC32(dpll_val & ~DPLL_VCO_ENABLE, map->dpll); in mdfld_restore_display_registers()
275 PSB_RVDC32(map->dpll); in mdfld_restore_display_registers()
280 dpll = PSB_RVDC32(map->dpll); in mdfld_restore_display_registers()
282 if (!(dpll & DPLL_VCO_ENABLE)) { in mdfld_restore_display_registers()
284 /* When ungating power of DPLL, needs to wait 0.5us in mdfld_restore_display_registers()
286 if (dpll & MDFLD_PWR_GATE_EN) { in mdfld_restore_display_registers()
287 dpll &= ~MDFLD_PWR_GATE_EN; in mdfld_restore_display_registers()
288 PSB_WVDC32(dpll, map->dpll); in mdfld_restore_display_registers()
294 PSB_WVDC32(dpll_val, map->dpll); in mdfld_restore_display_registers()
299 PSB_WVDC32(dpll_val, map->dpll); in mdfld_restore_display_registers()
300 PSB_RVDC32(map->dpll); in mdfld_restore_display_registers()
445 .dpll = MRST_DPLL_A,
467 .dpll = MDFLD_DPLL_B,
490 .dpll = MRST_DPLL_A,