21 #define MRST_BLC_MAX_PWM_REG_FREQ	    0xFFFF
27 #define BRIGHTNESS_MASK	0xFF
28 #define BLC_POLARITY_NORMAL 0
33 #define MDFLD_BLC_MAX_PWM_REG_FREQ        0xFFFE
34 #define MDFLD_BLC_MIN_PWM_REG_FREQ        0x2
36 #define MDFLD_BACKLIGHT_PWM_POLARITY_BIT_CLEAR (0xFFFE)
55 		u32 adjusted_level = 0;  in mdfld_set_brightness()
65 		if (mdfld_get_panel_type(dev, 0) == TC35876X) {  in mdfld_set_brightness()
66 			if (dev_priv->dpi_panel_on[0] ||  in mdfld_set_brightness()
71 			if (dev_priv->dpi_panel_on[0])  in mdfld_set_brightness()
72 				mdfld_dsi_brightness_control(dev, 0,  in mdfld_set_brightness()
84 	return 0;  in mdfld_set_brightness()
93 	DRM_DEBUG_DRIVER("brightness = 0x%x \n", dev_priv->brightness);  in mdfld_get_brightness()
112 	return 0;  in device_backlight_init()
118 	int ret = 0;  in mdfld_backlight_init()
120 	memset(&props, 0, sizeof(struct backlight_properties));  in mdfld_backlight_init()
136 	return 0;  in mdfld_backlight_init()
170 	case 0:  in mdfld_save_display_registers()
208 	for (i = 0; i < 256; i++)  in mdfld_save_display_registers()
217 		return 0;  in mdfld_save_display_registers()
221 	return 0;  in mdfld_save_display_registers()
234 	u32 temp = 0;  in mdfld_restore_display_registers()
243 	u32 timeout = 0;  in mdfld_restore_display_registers()
253 	case 0:  in mdfld_restore_display_registers()
255 		dsi_config = dev_priv->dsi_configs[0];  in mdfld_restore_display_registers()
271 	PSB_WVDC32(0x80000000, VGACNTRL);  in mdfld_restore_display_registers()
337 		for (i = 0; i < 256; i++)  in mdfld_restore_display_registers()
350 		return 0;  in mdfld_restore_display_registers()
383 	temp |= 0x3;  in mdfld_restore_display_registers()
399 	for (i = 0; i < 256; i++)  in mdfld_restore_display_registers()
402 	return 0;  in mdfld_restore_display_registers()
408 	mdfld_save_display_registers(dev, 0);  in mdfld_save_registers()
410 	mdfld_disable_crtc(dev, 0);  in mdfld_save_registers()
413 	return 0;  in mdfld_save_registers()
419 	mdfld_restore_display_registers(dev, 0);  in mdfld_restore_registers()
422 	return 0;  in mdfld_restore_registers()
428 	return 0;  in mdfld_power_down()
434 	return 0;  in mdfld_power_up()
510  * The GPIO lines for resetting DSI pipe 0 and 2 are available in the
511  * PCI device 0000:00:0c.0 on the Medfield.
515 		GPIO_LOOKUP("0000:00:0c.0", 128, "dsi-pipe0-reset",
517 		GPIO_LOOKUP("0000:00:0c.0", 34, "dsi-pipe2-reset",
539 	.accel_2d = 0,
544 	.cursor_needs_phys = 0,