206 /* Unlike most Intel display engines, on Cedarview the DPLL registers
208  * DPLL reference clock is on in the DPLL control register, but before
209  * the DPLL is enabled in the DPLL control register.
260 		DRM_DEBUG_KMS("use their DPLL for pipe A/B\n");  in cdv_dpll_set_clock_cdv()
583 	u32 dpll = 0, dspcntr, pipeconf;  in cdv_intel_crtc_mode_set()  local
662 	dpll = DPLL_VGA_MODE_DIS;  in cdv_intel_crtc_mode_set()
665 /*	dpll |= PLL_REF_INPUT_TVCLKINBC; */  in cdv_intel_crtc_mode_set()
666 		dpll |= 3;  in cdv_intel_crtc_mode_set()
668 /*		dpll |= PLL_REF_INPUT_DREFCLK; */  in cdv_intel_crtc_mode_set()
679 	dpll |= DPLL_SYNCLOCK_ENABLE;  in cdv_intel_crtc_mode_set()
681 		dpll |= DPLLB_MODE_LVDS;  in cdv_intel_crtc_mode_set()
683 		dpll |= DPLLB_MODE_DAC_SERIAL; */  in cdv_intel_crtc_mode_set()
684 	/* dpll |= (2 << 11); */  in cdv_intel_crtc_mode_set()
725 	REG_WRITE(map->dpll, dpll | DPLL_VGA_MODE_DIS | DPLL_SYNCLOCK_ENABLE);  in cdv_intel_crtc_mode_set()
726 	REG_READ(map->dpll);  in cdv_intel_crtc_mode_set()
761 	dpll |= DPLL_VCO_ENABLE;  in cdv_intel_crtc_mode_set()
770 	REG_WRITE(map->dpll,  in cdv_intel_crtc_mode_set()
771 		(REG_READ(map->dpll) & ~DPLL_LOCK) | DPLL_VCO_ENABLE);  in cdv_intel_crtc_mode_set()
772 	REG_READ(map->dpll);  in cdv_intel_crtc_mode_set()
776 	if (!(REG_READ(map->dpll) & DPLL_LOCK)) {  in cdv_intel_crtc_mode_set()
777 		dev_err(dev->dev, "Failed to get DPLL lock\n");  in cdv_intel_crtc_mode_set()
845 	u32 dpll;  in cdv_intel_crtc_clock_get()  local
852 		dpll = REG_READ(map->dpll);  in cdv_intel_crtc_clock_get()
853 		if ((dpll & DISPLAY_RATE_SELECT_FPA1) == 0)  in cdv_intel_crtc_clock_get()
860 		dpll = p->dpll;  in cdv_intel_crtc_clock_get()
861 		if ((dpll & DISPLAY_RATE_SELECT_FPA1) == 0)  in cdv_intel_crtc_clock_get()
876 		    ffs((dpll &  in cdv_intel_crtc_clock_get()
881 			dev_err(dev->dev, "PLL %d\n", dpll);  in cdv_intel_crtc_clock_get()
885 		if ((dpll & PLL_REF_INPUT_MASK) ==  in cdv_intel_crtc_clock_get()
892 		if (dpll & PLL_P1_DIVIDE_BY_TWO)  in cdv_intel_crtc_clock_get()
896 			    ((dpll &  in cdv_intel_crtc_clock_get()
900 		if (dpll & PLL_P2_DIVIDE_BY_4)  in cdv_intel_crtc_clock_get()