Lines Matching full:gpu
35 { .name = "etnaviv-gpu,2d" },
43 int etnaviv_gpu_get_param(struct etnaviv_gpu *gpu, u32 param, u64 *value) in etnaviv_gpu_get_param() argument
45 struct etnaviv_drm_private *priv = gpu->drm->dev_private; in etnaviv_gpu_get_param()
49 *value = gpu->identity.model; in etnaviv_gpu_get_param()
53 *value = gpu->identity.revision; in etnaviv_gpu_get_param()
57 *value = gpu->identity.features; in etnaviv_gpu_get_param()
61 *value = gpu->identity.minor_features0; in etnaviv_gpu_get_param()
65 *value = gpu->identity.minor_features1; in etnaviv_gpu_get_param()
69 *value = gpu->identity.minor_features2; in etnaviv_gpu_get_param()
73 *value = gpu->identity.minor_features3; in etnaviv_gpu_get_param()
77 *value = gpu->identity.minor_features4; in etnaviv_gpu_get_param()
81 *value = gpu->identity.minor_features5; in etnaviv_gpu_get_param()
85 *value = gpu->identity.minor_features6; in etnaviv_gpu_get_param()
89 *value = gpu->identity.minor_features7; in etnaviv_gpu_get_param()
93 *value = gpu->identity.minor_features8; in etnaviv_gpu_get_param()
97 *value = gpu->identity.minor_features9; in etnaviv_gpu_get_param()
101 *value = gpu->identity.minor_features10; in etnaviv_gpu_get_param()
105 *value = gpu->identity.minor_features11; in etnaviv_gpu_get_param()
109 *value = gpu->identity.stream_count; in etnaviv_gpu_get_param()
113 *value = gpu->identity.register_max; in etnaviv_gpu_get_param()
117 *value = gpu->identity.thread_count; in etnaviv_gpu_get_param()
121 *value = gpu->identity.vertex_cache_size; in etnaviv_gpu_get_param()
125 *value = gpu->identity.shader_core_count; in etnaviv_gpu_get_param()
129 *value = gpu->identity.pixel_pipes; in etnaviv_gpu_get_param()
133 *value = gpu->identity.vertex_output_buffer_size; in etnaviv_gpu_get_param()
137 *value = gpu->identity.buffer_size; in etnaviv_gpu_get_param()
141 *value = gpu->identity.instruction_count; in etnaviv_gpu_get_param()
145 *value = gpu->identity.num_constants; in etnaviv_gpu_get_param()
149 *value = gpu->identity.varyings_count; in etnaviv_gpu_get_param()
160 DBG("%s: invalid param: %u", dev_name(gpu->dev), param); in etnaviv_gpu_get_param()
168 #define etnaviv_is_model_rev(gpu, mod, rev) \ argument
169 ((gpu)->identity.model == chipModel_##mod && \
170 (gpu)->identity.revision == rev)
174 static void etnaviv_hw_specs(struct etnaviv_gpu *gpu) in etnaviv_hw_specs() argument
176 if (gpu->identity.minor_features0 & in etnaviv_hw_specs()
181 specs[0] = gpu_read(gpu, VIVS_HI_CHIP_SPECS); in etnaviv_hw_specs()
182 specs[1] = gpu_read(gpu, VIVS_HI_CHIP_SPECS_2); in etnaviv_hw_specs()
183 specs[2] = gpu_read(gpu, VIVS_HI_CHIP_SPECS_3); in etnaviv_hw_specs()
184 specs[3] = gpu_read(gpu, VIVS_HI_CHIP_SPECS_4); in etnaviv_hw_specs()
186 gpu->identity.stream_count = etnaviv_field(specs[0], in etnaviv_hw_specs()
188 gpu->identity.register_max = etnaviv_field(specs[0], in etnaviv_hw_specs()
190 gpu->identity.thread_count = etnaviv_field(specs[0], in etnaviv_hw_specs()
192 gpu->identity.vertex_cache_size = etnaviv_field(specs[0], in etnaviv_hw_specs()
194 gpu->identity.shader_core_count = etnaviv_field(specs[0], in etnaviv_hw_specs()
196 gpu->identity.pixel_pipes = etnaviv_field(specs[0], in etnaviv_hw_specs()
198 gpu->identity.vertex_output_buffer_size = in etnaviv_hw_specs()
202 gpu->identity.buffer_size = etnaviv_field(specs[1], in etnaviv_hw_specs()
204 gpu->identity.instruction_count = etnaviv_field(specs[1], in etnaviv_hw_specs()
206 gpu->identity.num_constants = etnaviv_field(specs[1], in etnaviv_hw_specs()
209 gpu->identity.varyings_count = etnaviv_field(specs[2], in etnaviv_hw_specs()
216 gpu->identity.stream_count = streams; in etnaviv_hw_specs()
220 if (gpu->identity.stream_count == 0) { in etnaviv_hw_specs()
221 if (gpu->identity.model >= 0x1000) in etnaviv_hw_specs()
222 gpu->identity.stream_count = 4; in etnaviv_hw_specs()
224 gpu->identity.stream_count = 1; in etnaviv_hw_specs()
228 if (gpu->identity.register_max) in etnaviv_hw_specs()
229 gpu->identity.register_max = 1 << gpu->identity.register_max; in etnaviv_hw_specs()
230 else if (gpu->identity.model == chipModel_GC400) in etnaviv_hw_specs()
231 gpu->identity.register_max = 32; in etnaviv_hw_specs()
233 gpu->identity.register_max = 64; in etnaviv_hw_specs()
236 if (gpu->identity.thread_count) in etnaviv_hw_specs()
237 gpu->identity.thread_count = 1 << gpu->identity.thread_count; in etnaviv_hw_specs()
238 else if (gpu->identity.model == chipModel_GC400) in etnaviv_hw_specs()
239 gpu->identity.thread_count = 64; in etnaviv_hw_specs()
240 else if (gpu->identity.model == chipModel_GC500 || in etnaviv_hw_specs()
241 gpu->identity.model == chipModel_GC530) in etnaviv_hw_specs()
242 gpu->identity.thread_count = 128; in etnaviv_hw_specs()
244 gpu->identity.thread_count = 256; in etnaviv_hw_specs()
246 if (gpu->identity.vertex_cache_size == 0) in etnaviv_hw_specs()
247 gpu->identity.vertex_cache_size = 8; in etnaviv_hw_specs()
249 if (gpu->identity.shader_core_count == 0) { in etnaviv_hw_specs()
250 if (gpu->identity.model >= 0x1000) in etnaviv_hw_specs()
251 gpu->identity.shader_core_count = 2; in etnaviv_hw_specs()
253 gpu->identity.shader_core_count = 1; in etnaviv_hw_specs()
256 if (gpu->identity.pixel_pipes == 0) in etnaviv_hw_specs()
257 gpu->identity.pixel_pipes = 1; in etnaviv_hw_specs()
260 if (gpu->identity.vertex_output_buffer_size) { in etnaviv_hw_specs()
261 gpu->identity.vertex_output_buffer_size = in etnaviv_hw_specs()
262 1 << gpu->identity.vertex_output_buffer_size; in etnaviv_hw_specs()
263 } else if (gpu->identity.model == chipModel_GC400) { in etnaviv_hw_specs()
264 if (gpu->identity.revision < 0x4000) in etnaviv_hw_specs()
265 gpu->identity.vertex_output_buffer_size = 512; in etnaviv_hw_specs()
266 else if (gpu->identity.revision < 0x4200) in etnaviv_hw_specs()
267 gpu->identity.vertex_output_buffer_size = 256; in etnaviv_hw_specs()
269 gpu->identity.vertex_output_buffer_size = 128; in etnaviv_hw_specs()
271 gpu->identity.vertex_output_buffer_size = 512; in etnaviv_hw_specs()
274 switch (gpu->identity.instruction_count) { in etnaviv_hw_specs()
276 if (etnaviv_is_model_rev(gpu, GC2000, 0x5108) || in etnaviv_hw_specs()
277 gpu->identity.model == chipModel_GC880) in etnaviv_hw_specs()
278 gpu->identity.instruction_count = 512; in etnaviv_hw_specs()
280 gpu->identity.instruction_count = 256; in etnaviv_hw_specs()
284 gpu->identity.instruction_count = 1024; in etnaviv_hw_specs()
288 gpu->identity.instruction_count = 2048; in etnaviv_hw_specs()
292 gpu->identity.instruction_count = 256; in etnaviv_hw_specs()
296 if (gpu->identity.num_constants == 0) in etnaviv_hw_specs()
297 gpu->identity.num_constants = 168; in etnaviv_hw_specs()
299 if (gpu->identity.varyings_count == 0) { in etnaviv_hw_specs()
300 if (gpu->identity.minor_features1 & chipMinorFeatures1_HALTI0) in etnaviv_hw_specs()
301 gpu->identity.varyings_count = 12; in etnaviv_hw_specs()
303 gpu->identity.varyings_count = 8; in etnaviv_hw_specs()
310 if (etnaviv_is_model_rev(gpu, GC5000, 0x5434) || in etnaviv_hw_specs()
311 etnaviv_is_model_rev(gpu, GC4000, 0x5222) || in etnaviv_hw_specs()
312 etnaviv_is_model_rev(gpu, GC4000, 0x5245) || in etnaviv_hw_specs()
313 etnaviv_is_model_rev(gpu, GC4000, 0x5208) || in etnaviv_hw_specs()
314 etnaviv_is_model_rev(gpu, GC3000, 0x5435) || in etnaviv_hw_specs()
315 etnaviv_is_model_rev(gpu, GC2200, 0x5244) || in etnaviv_hw_specs()
316 etnaviv_is_model_rev(gpu, GC2100, 0x5108) || in etnaviv_hw_specs()
317 etnaviv_is_model_rev(gpu, GC2000, 0x5108) || in etnaviv_hw_specs()
318 etnaviv_is_model_rev(gpu, GC1500, 0x5246) || in etnaviv_hw_specs()
319 etnaviv_is_model_rev(gpu, GC880, 0x5107) || in etnaviv_hw_specs()
320 etnaviv_is_model_rev(gpu, GC880, 0x5106)) in etnaviv_hw_specs()
321 gpu->identity.varyings_count -= 1; in etnaviv_hw_specs()
324 static void etnaviv_hw_identify(struct etnaviv_gpu *gpu) in etnaviv_hw_identify() argument
328 chipIdentity = gpu_read(gpu, VIVS_HI_CHIP_IDENTITY); in etnaviv_hw_identify()
332 gpu->identity.model = chipModel_GC500; in etnaviv_hw_identify()
333 gpu->identity.revision = etnaviv_field(chipIdentity, in etnaviv_hw_identify()
336 u32 chipDate = gpu_read(gpu, VIVS_HI_CHIP_DATE); in etnaviv_hw_identify()
338 gpu->identity.model = gpu_read(gpu, VIVS_HI_CHIP_MODEL); in etnaviv_hw_identify()
339 gpu->identity.revision = gpu_read(gpu, VIVS_HI_CHIP_REV); in etnaviv_hw_identify()
340 gpu->identity.customer_id = gpu_read(gpu, VIVS_HI_CHIP_CUSTOMER_ID); in etnaviv_hw_identify()
346 if (!etnaviv_is_model_rev(gpu, GC600, 0x19)) { in etnaviv_hw_identify()
347 gpu->identity.product_id = gpu_read(gpu, VIVS_HI_CHIP_PRODUCT_ID); in etnaviv_hw_identify()
348 gpu->identity.eco_id = gpu_read(gpu, VIVS_HI_CHIP_ECO_ID); in etnaviv_hw_identify()
357 if ((gpu->identity.model & 0xff00) == 0x0400 && in etnaviv_hw_identify()
358 gpu->identity.model != chipModel_GC420) { in etnaviv_hw_identify()
359 gpu->identity.model = gpu->identity.model & 0x0400; in etnaviv_hw_identify()
363 if (etnaviv_is_model_rev(gpu, GC300, 0x2201)) { in etnaviv_hw_identify()
364 u32 chipTime = gpu_read(gpu, VIVS_HI_CHIP_TIME); in etnaviv_hw_identify()
371 gpu->identity.revision = 0x1051; in etnaviv_hw_identify()
376 * NXP likes to call the GPU on the i.MX6QP GC2000+, but in in etnaviv_hw_identify()
382 if (etnaviv_is_model_rev(gpu, GC2000, 0xffff5450)) { in etnaviv_hw_identify()
383 gpu->identity.model = chipModel_GC3000; in etnaviv_hw_identify()
384 gpu->identity.revision &= 0xffff; in etnaviv_hw_identify()
387 if (etnaviv_is_model_rev(gpu, GC1000, 0x5037) && (chipDate == 0x20120617)) in etnaviv_hw_identify()
388 gpu->identity.eco_id = 1; in etnaviv_hw_identify()
390 if (etnaviv_is_model_rev(gpu, GC320, 0x5303) && (chipDate == 0x20140511)) in etnaviv_hw_identify()
391 gpu->identity.eco_id = 1; in etnaviv_hw_identify()
394 dev_info(gpu->dev, "model: GC%x, revision: %x\n", in etnaviv_hw_identify()
395 gpu->identity.model, gpu->identity.revision); in etnaviv_hw_identify()
397 gpu->idle_mask = ~VIVS_HI_IDLE_STATE_AXI_LP; in etnaviv_hw_identify()
402 if (etnaviv_fill_identity_from_hwdb(gpu)) in etnaviv_hw_identify()
405 gpu->identity.features = gpu_read(gpu, VIVS_HI_CHIP_FEATURE); in etnaviv_hw_identify()
408 if (gpu->identity.model == chipModel_GC700) in etnaviv_hw_identify()
409 gpu->identity.features &= ~chipFeatures_FAST_CLEAR; in etnaviv_hw_identify()
411 if ((gpu->identity.model == chipModel_GC500 && in etnaviv_hw_identify()
412 gpu->identity.revision < 2) || in etnaviv_hw_identify()
413 (gpu->identity.model == chipModel_GC300 && in etnaviv_hw_identify()
414 gpu->identity.revision < 0x2000)) { in etnaviv_hw_identify()
420 gpu->identity.minor_features0 = 0; in etnaviv_hw_identify()
421 gpu->identity.minor_features1 = 0; in etnaviv_hw_identify()
422 gpu->identity.minor_features2 = 0; in etnaviv_hw_identify()
423 gpu->identity.minor_features3 = 0; in etnaviv_hw_identify()
424 gpu->identity.minor_features4 = 0; in etnaviv_hw_identify()
425 gpu->identity.minor_features5 = 0; in etnaviv_hw_identify()
427 gpu->identity.minor_features0 = in etnaviv_hw_identify()
428 gpu_read(gpu, VIVS_HI_CHIP_MINOR_FEATURE_0); in etnaviv_hw_identify()
430 if (gpu->identity.minor_features0 & in etnaviv_hw_identify()
432 gpu->identity.minor_features1 = in etnaviv_hw_identify()
433 gpu_read(gpu, VIVS_HI_CHIP_MINOR_FEATURE_1); in etnaviv_hw_identify()
434 gpu->identity.minor_features2 = in etnaviv_hw_identify()
435 gpu_read(gpu, VIVS_HI_CHIP_MINOR_FEATURE_2); in etnaviv_hw_identify()
436 gpu->identity.minor_features3 = in etnaviv_hw_identify()
437 gpu_read(gpu, VIVS_HI_CHIP_MINOR_FEATURE_3); in etnaviv_hw_identify()
438 gpu->identity.minor_features4 = in etnaviv_hw_identify()
439 gpu_read(gpu, VIVS_HI_CHIP_MINOR_FEATURE_4); in etnaviv_hw_identify()
440 gpu->identity.minor_features5 = in etnaviv_hw_identify()
441 gpu_read(gpu, VIVS_HI_CHIP_MINOR_FEATURE_5); in etnaviv_hw_identify()
445 if (gpu->identity.model == chipModel_GC600) in etnaviv_hw_identify()
446 gpu->idle_mask = VIVS_HI_IDLE_STATE_TX | in etnaviv_hw_identify()
455 etnaviv_hw_specs(gpu); in etnaviv_hw_identify()
458 static void etnaviv_gpu_load_clock(struct etnaviv_gpu *gpu, u32 clock) in etnaviv_gpu_load_clock() argument
460 gpu_write(gpu, VIVS_HI_CLOCK_CONTROL, clock | in etnaviv_gpu_load_clock()
462 gpu_write(gpu, VIVS_HI_CLOCK_CONTROL, clock); in etnaviv_gpu_load_clock()
465 static void etnaviv_gpu_update_clock(struct etnaviv_gpu *gpu) in etnaviv_gpu_update_clock() argument
467 if (gpu->identity.minor_features2 & in etnaviv_gpu_update_clock()
469 clk_set_rate(gpu->clk_core, in etnaviv_gpu_update_clock()
470 gpu->base_rate_core >> gpu->freq_scale); in etnaviv_gpu_update_clock()
471 clk_set_rate(gpu->clk_shader, in etnaviv_gpu_update_clock()
472 gpu->base_rate_shader >> gpu->freq_scale); in etnaviv_gpu_update_clock()
474 unsigned int fscale = 1 << (6 - gpu->freq_scale); in etnaviv_gpu_update_clock()
475 u32 clock = gpu_read(gpu, VIVS_HI_CLOCK_CONTROL); in etnaviv_gpu_update_clock()
479 etnaviv_gpu_load_clock(gpu, clock); in etnaviv_gpu_update_clock()
483 static int etnaviv_hw_reset(struct etnaviv_gpu *gpu) in etnaviv_hw_reset() argument
489 /* We hope that the GPU resets in under one second */ in etnaviv_hw_reset()
494 unsigned int fscale = 1 << (6 - gpu->freq_scale); in etnaviv_hw_reset()
496 etnaviv_gpu_load_clock(gpu, control); in etnaviv_hw_reset()
498 /* isolate the GPU. */ in etnaviv_hw_reset()
500 gpu_write(gpu, VIVS_HI_CLOCK_CONTROL, control); in etnaviv_hw_reset()
502 if (gpu->sec_mode == ETNA_SEC_KERNEL) { in etnaviv_hw_reset()
503 gpu_write(gpu, VIVS_MMUv2_AHB_CONTROL, in etnaviv_hw_reset()
508 gpu_write(gpu, VIVS_HI_CLOCK_CONTROL, control); in etnaviv_hw_reset()
516 gpu_write(gpu, VIVS_HI_CLOCK_CONTROL, control); in etnaviv_hw_reset()
518 /* reset GPU isolation. */ in etnaviv_hw_reset()
520 gpu_write(gpu, VIVS_HI_CLOCK_CONTROL, control); in etnaviv_hw_reset()
523 idle = gpu_read(gpu, VIVS_HI_IDLE_STATE); in etnaviv_hw_reset()
527 dev_dbg(gpu->dev, "FE is not idle\n"); in etnaviv_hw_reset()
532 control = gpu_read(gpu, VIVS_HI_CLOCK_CONTROL); in etnaviv_hw_reset()
534 /* is the GPU idle? */ in etnaviv_hw_reset()
537 dev_dbg(gpu->dev, "GPU is not idle\n"); in etnaviv_hw_reset()
543 gpu_write(gpu, VIVS_HI_CLOCK_CONTROL, control); in etnaviv_hw_reset()
550 idle = gpu_read(gpu, VIVS_HI_IDLE_STATE); in etnaviv_hw_reset()
551 control = gpu_read(gpu, VIVS_HI_CLOCK_CONTROL); in etnaviv_hw_reset()
553 dev_err(gpu->dev, "GPU failed to reset: FE %sidle, 3D %sidle, 2D %sidle\n", in etnaviv_hw_reset()
561 /* We rely on the GPU running, so program the clock */ in etnaviv_hw_reset()
562 etnaviv_gpu_update_clock(gpu); in etnaviv_hw_reset()
567 static void etnaviv_gpu_enable_mlcg(struct etnaviv_gpu *gpu) in etnaviv_gpu_enable_mlcg() argument
572 ppc = gpu_read(gpu, VIVS_PM_POWER_CONTROLS); in etnaviv_gpu_enable_mlcg()
576 if (gpu->identity.revision == 0x4301 || in etnaviv_gpu_enable_mlcg()
577 gpu->identity.revision == 0x4302) in etnaviv_gpu_enable_mlcg()
580 gpu_write(gpu, VIVS_PM_POWER_CONTROLS, ppc); in etnaviv_gpu_enable_mlcg()
582 pmc = gpu_read(gpu, VIVS_PM_MODULE_CONTROLS); in etnaviv_gpu_enable_mlcg()
585 if (gpu->identity.model >= chipModel_GC400 && in etnaviv_gpu_enable_mlcg()
586 gpu->identity.model != chipModel_GC420 && in etnaviv_gpu_enable_mlcg()
587 !(gpu->identity.minor_features3 & chipMinorFeatures3_BUG_FIXES12)) in etnaviv_gpu_enable_mlcg()
594 if (gpu->identity.revision < 0x5000 && in etnaviv_gpu_enable_mlcg()
595 gpu->identity.minor_features0 & chipMinorFeatures0_HZ && in etnaviv_gpu_enable_mlcg()
596 !(gpu->identity.minor_features1 & in etnaviv_gpu_enable_mlcg()
600 if (gpu->identity.revision < 0x5422) in etnaviv_gpu_enable_mlcg()
604 if (etnaviv_is_model_rev(gpu, GC4000, 0x5222) || in etnaviv_gpu_enable_mlcg()
605 etnaviv_is_model_rev(gpu, GC2000, 0x5108)) in etnaviv_gpu_enable_mlcg()
611 gpu_write(gpu, VIVS_PM_MODULE_CONTROLS, pmc); in etnaviv_gpu_enable_mlcg()
614 void etnaviv_gpu_start_fe(struct etnaviv_gpu *gpu, u32 address, u16 prefetch) in etnaviv_gpu_start_fe() argument
616 gpu_write(gpu, VIVS_FE_COMMAND_ADDRESS, address); in etnaviv_gpu_start_fe()
617 gpu_write(gpu, VIVS_FE_COMMAND_CONTROL, in etnaviv_gpu_start_fe()
621 if (gpu->sec_mode == ETNA_SEC_KERNEL) { in etnaviv_gpu_start_fe()
622 gpu_write(gpu, VIVS_MMUv2_SEC_COMMAND_CONTROL, in etnaviv_gpu_start_fe()
628 static void etnaviv_gpu_start_fe_idleloop(struct etnaviv_gpu *gpu) in etnaviv_gpu_start_fe_idleloop() argument
630 u32 address = etnaviv_cmdbuf_get_va(&gpu->buffer, in etnaviv_gpu_start_fe_idleloop()
631 &gpu->mmu_context->cmdbuf_mapping); in etnaviv_gpu_start_fe_idleloop()
635 etnaviv_iommu_restore(gpu, gpu->mmu_context); in etnaviv_gpu_start_fe_idleloop()
638 prefetch = etnaviv_buffer_init(gpu); in etnaviv_gpu_start_fe_idleloop()
640 etnaviv_gpu_start_fe(gpu, address, prefetch); in etnaviv_gpu_start_fe_idleloop()
643 static void etnaviv_gpu_setup_pulse_eater(struct etnaviv_gpu *gpu) in etnaviv_gpu_setup_pulse_eater() argument
651 if (etnaviv_is_model_rev(gpu, GC4000, 0x5208) || in etnaviv_gpu_setup_pulse_eater()
652 etnaviv_is_model_rev(gpu, GC4000, 0x5222)) { in etnaviv_gpu_setup_pulse_eater()
657 if (etnaviv_is_model_rev(gpu, GC1000, 0x5039) || in etnaviv_gpu_setup_pulse_eater()
658 etnaviv_is_model_rev(gpu, GC1000, 0x5040)) { in etnaviv_gpu_setup_pulse_eater()
663 if ((gpu->identity.revision > 0x5420) && in etnaviv_gpu_setup_pulse_eater()
664 (gpu->identity.features & chipFeatures_PIPE_3D)) in etnaviv_gpu_setup_pulse_eater()
667 pulse_eater = gpu_read(gpu, VIVS_PM_PULSE_EATER); in etnaviv_gpu_setup_pulse_eater()
671 gpu_write(gpu, VIVS_PM_PULSE_EATER, pulse_eater); in etnaviv_gpu_setup_pulse_eater()
674 static void etnaviv_gpu_hw_init(struct etnaviv_gpu *gpu) in etnaviv_gpu_hw_init() argument
676 if ((etnaviv_is_model_rev(gpu, GC320, 0x5007) || in etnaviv_gpu_hw_init()
677 etnaviv_is_model_rev(gpu, GC320, 0x5220)) && in etnaviv_gpu_hw_init()
678 gpu_read(gpu, VIVS_HI_CHIP_TIME) != 0x2062400) { in etnaviv_gpu_hw_init()
681 mc_memory_debug = gpu_read(gpu, VIVS_MC_DEBUG_MEMORY) & ~0xff; in etnaviv_gpu_hw_init()
683 if (gpu->identity.revision == 0x5007) in etnaviv_gpu_hw_init()
688 gpu_write(gpu, VIVS_MC_DEBUG_MEMORY, mc_memory_debug); in etnaviv_gpu_hw_init()
692 etnaviv_gpu_enable_mlcg(gpu); in etnaviv_gpu_hw_init()
695 * Update GPU AXI cache atttribute to "cacheable, no allocate". in etnaviv_gpu_hw_init()
698 gpu_write(gpu, VIVS_HI_AXI_CONFIG, in etnaviv_gpu_hw_init()
703 if (etnaviv_is_model_rev(gpu, GC2000, 0x5108)) { in etnaviv_gpu_hw_init()
704 u32 bus_config = gpu_read(gpu, VIVS_MC_BUS_CONFIG); in etnaviv_gpu_hw_init()
709 gpu_write(gpu, VIVS_MC_BUS_CONFIG, bus_config); in etnaviv_gpu_hw_init()
712 if (gpu->sec_mode == ETNA_SEC_KERNEL) { in etnaviv_gpu_hw_init()
713 u32 val = gpu_read(gpu, VIVS_MMUv2_AHB_CONTROL); in etnaviv_gpu_hw_init()
715 gpu_write(gpu, VIVS_MMUv2_AHB_CONTROL, val); in etnaviv_gpu_hw_init()
719 etnaviv_gpu_setup_pulse_eater(gpu); in etnaviv_gpu_hw_init()
721 gpu_write(gpu, VIVS_HI_INTR_ENBL, ~0U); in etnaviv_gpu_hw_init()
724 int etnaviv_gpu_init(struct etnaviv_gpu *gpu) in etnaviv_gpu_init() argument
726 struct etnaviv_drm_private *priv = gpu->drm->dev_private; in etnaviv_gpu_init()
729 ret = pm_runtime_get_sync(gpu->dev); in etnaviv_gpu_init()
731 dev_err(gpu->dev, "Failed to enable GPU power domain\n"); in etnaviv_gpu_init()
735 etnaviv_hw_identify(gpu); in etnaviv_gpu_init()
737 if (gpu->identity.model == 0) { in etnaviv_gpu_init()
738 dev_err(gpu->dev, "Unknown GPU model\n"); in etnaviv_gpu_init()
744 if (gpu->identity.features & chipFeatures_PIPE_VG && in etnaviv_gpu_init()
745 gpu->identity.features & chipFeatures_FE20) { in etnaviv_gpu_init()
746 dev_info(gpu->dev, "Ignoring GPU with VG and FE2.0\n"); in etnaviv_gpu_init()
755 if ((gpu->identity.minor_features7 & chipMinorFeatures7_BIT_SECURITY) && in etnaviv_gpu_init()
756 (gpu->identity.minor_features10 & chipMinorFeatures10_SECURITY_AHB)) in etnaviv_gpu_init()
757 gpu->sec_mode = ETNA_SEC_KERNEL; in etnaviv_gpu_init()
759 ret = etnaviv_hw_reset(gpu); in etnaviv_gpu_init()
761 dev_err(gpu->dev, "GPU reset failed\n"); in etnaviv_gpu_init()
765 ret = etnaviv_iommu_global_init(gpu); in etnaviv_gpu_init()
770 * Set the GPU linear window to be at the end of the DMA window, where in etnaviv_gpu_init()
778 if (!(gpu->identity.features & chipFeatures_PIPE_3D) || in etnaviv_gpu_init()
779 (gpu->identity.minor_features0 & chipMinorFeatures0_MC20)) { in etnaviv_gpu_init()
780 u32 dma_mask = (u32)dma_get_required_mask(gpu->dev); in etnaviv_gpu_init()
786 dev_info(gpu->dev, "Need to move linear window on MC1.0, disabling TS\n"); in etnaviv_gpu_init()
788 gpu->identity.features &= ~chipFeatures_FAST_CLEAR; in etnaviv_gpu_init()
792 * If the GPU is part of a system with DMA addressing limitations, in etnaviv_gpu_init()
796 if (dma_addressing_limited(gpu->dev)) in etnaviv_gpu_init()
800 ret = etnaviv_cmdbuf_init(priv->cmdbuf_suballoc, &gpu->buffer, in etnaviv_gpu_init()
803 dev_err(gpu->dev, "could not create command buffer\n"); in etnaviv_gpu_init()
808 spin_lock_init(&gpu->event_spinlock); in etnaviv_gpu_init()
809 init_completion(&gpu->event_free); in etnaviv_gpu_init()
810 bitmap_zero(gpu->event_bitmap, ETNA_NR_EVENTS); in etnaviv_gpu_init()
811 for (i = 0; i < ARRAY_SIZE(gpu->event); i++) in etnaviv_gpu_init()
812 complete(&gpu->event_free); in etnaviv_gpu_init()
815 mutex_lock(&gpu->lock); in etnaviv_gpu_init()
816 etnaviv_gpu_hw_init(gpu); in etnaviv_gpu_init()
817 gpu->exec_state = -1; in etnaviv_gpu_init()
818 mutex_unlock(&gpu->lock); in etnaviv_gpu_init()
820 pm_runtime_mark_last_busy(gpu->dev); in etnaviv_gpu_init()
821 pm_runtime_put_autosuspend(gpu->dev); in etnaviv_gpu_init()
823 gpu->initialized = true; in etnaviv_gpu_init()
828 pm_runtime_mark_last_busy(gpu->dev); in etnaviv_gpu_init()
830 pm_runtime_put_autosuspend(gpu->dev); in etnaviv_gpu_init()
841 static void verify_dma(struct etnaviv_gpu *gpu, struct dma_debug *debug) in verify_dma() argument
845 debug->address[0] = gpu_read(gpu, VIVS_FE_DMA_ADDRESS); in verify_dma()
846 debug->state[0] = gpu_read(gpu, VIVS_FE_DMA_DEBUG_STATE); in verify_dma()
849 debug->address[1] = gpu_read(gpu, VIVS_FE_DMA_ADDRESS); in verify_dma()
850 debug->state[1] = gpu_read(gpu, VIVS_FE_DMA_DEBUG_STATE); in verify_dma()
860 int etnaviv_gpu_debugfs(struct etnaviv_gpu *gpu, struct seq_file *m) in etnaviv_gpu_debugfs() argument
866 seq_printf(m, "%s Status:\n", dev_name(gpu->dev)); in etnaviv_gpu_debugfs()
868 ret = pm_runtime_get_sync(gpu->dev); in etnaviv_gpu_debugfs()
872 dma_lo = gpu_read(gpu, VIVS_FE_DMA_LOW); in etnaviv_gpu_debugfs()
873 dma_hi = gpu_read(gpu, VIVS_FE_DMA_HIGH); in etnaviv_gpu_debugfs()
874 axi = gpu_read(gpu, VIVS_HI_AXI_STATUS); in etnaviv_gpu_debugfs()
875 idle = gpu_read(gpu, VIVS_HI_IDLE_STATE); in etnaviv_gpu_debugfs()
877 verify_dma(gpu, &debug); in etnaviv_gpu_debugfs()
880 seq_printf(m, "\t model: 0x%x\n", gpu->identity.model); in etnaviv_gpu_debugfs()
881 seq_printf(m, "\t revision: 0x%x\n", gpu->identity.revision); in etnaviv_gpu_debugfs()
882 seq_printf(m, "\t product_id: 0x%x\n", gpu->identity.product_id); in etnaviv_gpu_debugfs()
883 seq_printf(m, "\t customer_id: 0x%x\n", gpu->identity.customer_id); in etnaviv_gpu_debugfs()
884 seq_printf(m, "\t eco_id: 0x%x\n", gpu->identity.eco_id); in etnaviv_gpu_debugfs()
888 gpu->identity.features); in etnaviv_gpu_debugfs()
890 gpu->identity.minor_features0); in etnaviv_gpu_debugfs()
892 gpu->identity.minor_features1); in etnaviv_gpu_debugfs()
894 gpu->identity.minor_features2); in etnaviv_gpu_debugfs()
896 gpu->identity.minor_features3); in etnaviv_gpu_debugfs()
898 gpu->identity.minor_features4); in etnaviv_gpu_debugfs()
900 gpu->identity.minor_features5); in etnaviv_gpu_debugfs()
902 gpu->identity.minor_features6); in etnaviv_gpu_debugfs()
904 gpu->identity.minor_features7); in etnaviv_gpu_debugfs()
906 gpu->identity.minor_features8); in etnaviv_gpu_debugfs()
908 gpu->identity.minor_features9); in etnaviv_gpu_debugfs()
910 gpu->identity.minor_features10); in etnaviv_gpu_debugfs()
912 gpu->identity.minor_features11); in etnaviv_gpu_debugfs()
916 gpu->identity.stream_count); in etnaviv_gpu_debugfs()
918 gpu->identity.register_max); in etnaviv_gpu_debugfs()
920 gpu->identity.thread_count); in etnaviv_gpu_debugfs()
922 gpu->identity.vertex_cache_size); in etnaviv_gpu_debugfs()
924 gpu->identity.shader_core_count); in etnaviv_gpu_debugfs()
926 gpu->identity.pixel_pipes); in etnaviv_gpu_debugfs()
928 gpu->identity.vertex_output_buffer_size); in etnaviv_gpu_debugfs()
930 gpu->identity.buffer_size); in etnaviv_gpu_debugfs()
932 gpu->identity.instruction_count); in etnaviv_gpu_debugfs()
934 gpu->identity.num_constants); in etnaviv_gpu_debugfs()
936 gpu->identity.varyings_count); in etnaviv_gpu_debugfs()
940 idle |= ~gpu->idle_mask & ~VIVS_HI_IDLE_STATE_AXI_LP; in etnaviv_gpu_debugfs()
982 if (gpu->identity.features & chipFeatures_DEBUG_MODE) { in etnaviv_gpu_debugfs()
983 u32 read0 = gpu_read(gpu, VIVS_MC_DEBUG_READ0); in etnaviv_gpu_debugfs()
984 u32 read1 = gpu_read(gpu, VIVS_MC_DEBUG_READ1); in etnaviv_gpu_debugfs()
985 u32 write = gpu_read(gpu, VIVS_MC_DEBUG_WRITE); in etnaviv_gpu_debugfs()
1013 pm_runtime_mark_last_busy(gpu->dev); in etnaviv_gpu_debugfs()
1015 pm_runtime_put_autosuspend(gpu->dev); in etnaviv_gpu_debugfs()
1021 void etnaviv_gpu_recover_hang(struct etnaviv_gpu *gpu) in etnaviv_gpu_recover_hang() argument
1025 dev_err(gpu->dev, "recover hung GPU!\n"); in etnaviv_gpu_recover_hang()
1027 if (pm_runtime_get_sync(gpu->dev) < 0) in etnaviv_gpu_recover_hang()
1030 mutex_lock(&gpu->lock); in etnaviv_gpu_recover_hang()
1032 etnaviv_hw_reset(gpu); in etnaviv_gpu_recover_hang()
1034 /* complete all events, the GPU won't do it after the reset */ in etnaviv_gpu_recover_hang()
1035 spin_lock(&gpu->event_spinlock); in etnaviv_gpu_recover_hang()
1036 for_each_set_bit_from(i, gpu->event_bitmap, ETNA_NR_EVENTS) in etnaviv_gpu_recover_hang()
1037 complete(&gpu->event_free); in etnaviv_gpu_recover_hang()
1038 bitmap_zero(gpu->event_bitmap, ETNA_NR_EVENTS); in etnaviv_gpu_recover_hang()
1039 spin_unlock(&gpu->event_spinlock); in etnaviv_gpu_recover_hang()
1041 etnaviv_gpu_hw_init(gpu); in etnaviv_gpu_recover_hang()
1042 gpu->exec_state = -1; in etnaviv_gpu_recover_hang()
1043 gpu->mmu_context = NULL; in etnaviv_gpu_recover_hang()
1045 mutex_unlock(&gpu->lock); in etnaviv_gpu_recover_hang()
1046 pm_runtime_mark_last_busy(gpu->dev); in etnaviv_gpu_recover_hang()
1048 pm_runtime_put_autosuspend(gpu->dev); in etnaviv_gpu_recover_hang()
1053 struct etnaviv_gpu *gpu; member
1071 return dev_name(f->gpu->dev); in etnaviv_fence_get_timeline_name()
1078 return (s32)(f->gpu->completed_fence - f->base.seqno) >= 0; in etnaviv_fence_signaled()
1095 static struct dma_fence *etnaviv_gpu_fence_alloc(struct etnaviv_gpu *gpu) in etnaviv_gpu_fence_alloc() argument
1100 * GPU lock must already be held, otherwise fence completion order might in etnaviv_gpu_fence_alloc()
1103 lockdep_assert_held(&gpu->lock); in etnaviv_gpu_fence_alloc()
1109 f->gpu = gpu; in etnaviv_gpu_fence_alloc()
1111 dma_fence_init(&f->base, &etnaviv_fence_ops, &gpu->fence_spinlock, in etnaviv_gpu_fence_alloc()
1112 gpu->fence_context, ++gpu->next_fence); in etnaviv_gpu_fence_alloc()
1127 static int event_alloc(struct etnaviv_gpu *gpu, unsigned nr_events, in event_alloc() argument
1136 ret = wait_for_completion_timeout(&gpu->event_free, timeout); in event_alloc()
1139 dev_err(gpu->dev, "wait_for_completion_timeout failed"); in event_alloc()
1147 spin_lock(&gpu->event_spinlock); in event_alloc()
1150 int event = find_first_zero_bit(gpu->event_bitmap, ETNA_NR_EVENTS); in event_alloc()
1153 memset(&gpu->event[event], 0, sizeof(struct etnaviv_event)); in event_alloc()
1154 set_bit(event, gpu->event_bitmap); in event_alloc()
1157 spin_unlock(&gpu->event_spinlock); in event_alloc()
1163 complete(&gpu->event_free); in event_alloc()
1168 static void event_free(struct etnaviv_gpu *gpu, unsigned int event) in event_free() argument
1170 if (!test_bit(event, gpu->event_bitmap)) { in event_free()
1171 dev_warn(gpu->dev, "event %u is already marked as free", in event_free()
1174 clear_bit(event, gpu->event_bitmap); in event_free()
1175 complete(&gpu->event_free); in event_free()
1182 int etnaviv_gpu_wait_fence_interruptible(struct etnaviv_gpu *gpu, in etnaviv_gpu_wait_fence_interruptible() argument
1194 fence = idr_find(&gpu->fence_idr, id); in etnaviv_gpu_wait_fence_interruptible()
1226 * Although the retirement happens under the gpu lock, we don't want to hold
1229 int etnaviv_gpu_wait_obj_inactive(struct etnaviv_gpu *gpu, in etnaviv_gpu_wait_obj_inactive() argument
1241 ret = wait_event_interruptible_timeout(gpu->fence_event, in etnaviv_gpu_wait_obj_inactive()
1252 static void sync_point_perfmon_sample(struct etnaviv_gpu *gpu, in sync_point_perfmon_sample() argument
1262 etnaviv_perfmon_process(gpu, pmr, submit->exec_state); in sync_point_perfmon_sample()
1266 static void sync_point_perfmon_sample_pre(struct etnaviv_gpu *gpu, in sync_point_perfmon_sample_pre() argument
1272 val = gpu_read(gpu, VIVS_PM_POWER_CONTROLS); in sync_point_perfmon_sample_pre()
1274 gpu_write(gpu, VIVS_PM_POWER_CONTROLS, val); in sync_point_perfmon_sample_pre()
1277 val = gpu_read(gpu, VIVS_HI_CLOCK_CONTROL); in sync_point_perfmon_sample_pre()
1279 gpu_write(gpu, VIVS_HI_CLOCK_CONTROL, val); in sync_point_perfmon_sample_pre()
1281 sync_point_perfmon_sample(gpu, event, ETNA_PM_PROCESS_PRE); in sync_point_perfmon_sample_pre()
1284 static void sync_point_perfmon_sample_post(struct etnaviv_gpu *gpu, in sync_point_perfmon_sample_post() argument
1291 sync_point_perfmon_sample(gpu, event, ETNA_PM_PROCESS_POST); in sync_point_perfmon_sample_post()
1300 val = gpu_read(gpu, VIVS_HI_CLOCK_CONTROL); in sync_point_perfmon_sample_post()
1302 gpu_write(gpu, VIVS_HI_CLOCK_CONTROL, val); in sync_point_perfmon_sample_post()
1305 val = gpu_read(gpu, VIVS_PM_POWER_CONTROLS); in sync_point_perfmon_sample_post()
1307 gpu_write(gpu, VIVS_PM_POWER_CONTROLS, val); in sync_point_perfmon_sample_post()
1311 /* add bo's to gpu's ring, and kick gpu: */
1314 struct etnaviv_gpu *gpu = submit->gpu; in etnaviv_gpu_submit() local
1320 ret = pm_runtime_get_sync(gpu->dev); in etnaviv_gpu_submit()
1322 pm_runtime_put_noidle(gpu->dev); in etnaviv_gpu_submit()
1330 * - a sync point to re-configure gpu and process ETNA_PM_PROCESS_PRE in etnaviv_gpu_submit()
1332 * - a sync point to re-configure gpu, process ETNA_PM_PROCESS_POST requests in etnaviv_gpu_submit()
1338 ret = event_alloc(gpu, nr_events, event); in etnaviv_gpu_submit()
1341 pm_runtime_put_noidle(gpu->dev); in etnaviv_gpu_submit()
1345 mutex_lock(&gpu->lock); in etnaviv_gpu_submit()
1347 gpu_fence = etnaviv_gpu_fence_alloc(gpu); in etnaviv_gpu_submit()
1350 event_free(gpu, event[i]); in etnaviv_gpu_submit()
1355 if (!gpu->mmu_context) { in etnaviv_gpu_submit()
1357 gpu->mmu_context = submit->mmu_context; in etnaviv_gpu_submit()
1358 etnaviv_gpu_start_fe_idleloop(gpu); in etnaviv_gpu_submit()
1360 etnaviv_iommu_context_get(gpu->mmu_context); in etnaviv_gpu_submit()
1361 submit->prev_mmu_context = gpu->mmu_context; in etnaviv_gpu_submit()
1365 gpu->event[event[1]].sync_point = &sync_point_perfmon_sample_pre; in etnaviv_gpu_submit()
1367 gpu->event[event[1]].submit = submit; in etnaviv_gpu_submit()
1368 etnaviv_sync_point_queue(gpu, event[1]); in etnaviv_gpu_submit()
1371 gpu->event[event[0]].fence = gpu_fence; in etnaviv_gpu_submit()
1373 etnaviv_buffer_queue(gpu, submit->exec_state, submit->mmu_context, in etnaviv_gpu_submit()
1377 gpu->event[event[2]].sync_point = &sync_point_perfmon_sample_post; in etnaviv_gpu_submit()
1379 gpu->event[event[2]].submit = submit; in etnaviv_gpu_submit()
1380 etnaviv_sync_point_queue(gpu, event[2]); in etnaviv_gpu_submit()
1384 mutex_unlock(&gpu->lock); in etnaviv_gpu_submit()
1391 struct etnaviv_gpu *gpu = container_of(work, struct etnaviv_gpu, in sync_point_worker() local
1393 struct etnaviv_event *event = &gpu->event[gpu->sync_point_event]; in sync_point_worker()
1394 u32 addr = gpu_read(gpu, VIVS_FE_DMA_ADDRESS); in sync_point_worker()
1396 event->sync_point(gpu, event); in sync_point_worker()
1398 event_free(gpu, gpu->sync_point_event); in sync_point_worker()
1400 /* restart FE last to avoid GPU and IRQ racing against this worker */ in sync_point_worker()
1401 etnaviv_gpu_start_fe(gpu, addr + 2, 2); in sync_point_worker()
1404 static void dump_mmu_fault(struct etnaviv_gpu *gpu) in dump_mmu_fault() argument
1409 if (gpu->sec_mode == ETNA_SEC_NONE) in dump_mmu_fault()
1414 status = gpu_read(gpu, status_reg); in dump_mmu_fault()
1415 dev_err_ratelimited(gpu->dev, "MMU fault status 0x%08x\n", status); in dump_mmu_fault()
1423 if (gpu->sec_mode == ETNA_SEC_NONE) in dump_mmu_fault()
1428 dev_err_ratelimited(gpu->dev, "MMU %d fault addr 0x%08x\n", i, in dump_mmu_fault()
1429 gpu_read(gpu, address_reg)); in dump_mmu_fault()
1435 struct etnaviv_gpu *gpu = data; in irq_handler() local
1438 u32 intr = gpu_read(gpu, VIVS_HI_INTR_ACKNOWLEDGE); in irq_handler()
1443 pm_runtime_mark_last_busy(gpu->dev); in irq_handler()
1445 dev_dbg(gpu->dev, "intr 0x%08x\n", intr); in irq_handler()
1448 dev_err(gpu->dev, "AXI bus error\n"); in irq_handler()
1453 dump_mmu_fault(gpu); in irq_handler()
1464 dev_dbg(gpu->dev, "event %u\n", event); in irq_handler()
1466 if (gpu->event[event].sync_point) { in irq_handler()
1467 gpu->sync_point_event = event; in irq_handler()
1468 queue_work(gpu->wq, &gpu->sync_point_work); in irq_handler()
1471 fence = gpu->event[event].fence; in irq_handler()
1475 gpu->event[event].fence = NULL; in irq_handler()
1486 if (fence_after(fence->seqno, gpu->completed_fence)) in irq_handler()
1487 gpu->completed_fence = fence->seqno; in irq_handler()
1490 event_free(gpu, event); in irq_handler()
1499 static int etnaviv_gpu_clk_enable(struct etnaviv_gpu *gpu) in etnaviv_gpu_clk_enable() argument
1503 ret = clk_prepare_enable(gpu->clk_reg); in etnaviv_gpu_clk_enable()
1507 ret = clk_prepare_enable(gpu->clk_bus); in etnaviv_gpu_clk_enable()
1511 ret = clk_prepare_enable(gpu->clk_core); in etnaviv_gpu_clk_enable()
1515 ret = clk_prepare_enable(gpu->clk_shader); in etnaviv_gpu_clk_enable()
1522 clk_disable_unprepare(gpu->clk_core); in etnaviv_gpu_clk_enable()
1524 clk_disable_unprepare(gpu->clk_bus); in etnaviv_gpu_clk_enable()
1526 clk_disable_unprepare(gpu->clk_reg); in etnaviv_gpu_clk_enable()
1531 static int etnaviv_gpu_clk_disable(struct etnaviv_gpu *gpu) in etnaviv_gpu_clk_disable() argument
1533 clk_disable_unprepare(gpu->clk_shader); in etnaviv_gpu_clk_disable()
1534 clk_disable_unprepare(gpu->clk_core); in etnaviv_gpu_clk_disable()
1535 clk_disable_unprepare(gpu->clk_bus); in etnaviv_gpu_clk_disable()
1536 clk_disable_unprepare(gpu->clk_reg); in etnaviv_gpu_clk_disable()
1541 int etnaviv_gpu_wait_idle(struct etnaviv_gpu *gpu, unsigned int timeout_ms) in etnaviv_gpu_wait_idle() argument
1546 u32 idle = gpu_read(gpu, VIVS_HI_IDLE_STATE); in etnaviv_gpu_wait_idle()
1548 if ((idle & gpu->idle_mask) == gpu->idle_mask) in etnaviv_gpu_wait_idle()
1552 dev_warn(gpu->dev, in etnaviv_gpu_wait_idle()
1562 static int etnaviv_gpu_hw_suspend(struct etnaviv_gpu *gpu) in etnaviv_gpu_hw_suspend() argument
1564 if (gpu->initialized && gpu->mmu_context) { in etnaviv_gpu_hw_suspend()
1566 mutex_lock(&gpu->lock); in etnaviv_gpu_hw_suspend()
1567 etnaviv_buffer_end(gpu); in etnaviv_gpu_hw_suspend()
1568 mutex_unlock(&gpu->lock); in etnaviv_gpu_hw_suspend()
1575 etnaviv_gpu_wait_idle(gpu, 100); in etnaviv_gpu_hw_suspend()
1577 etnaviv_iommu_context_put(gpu->mmu_context); in etnaviv_gpu_hw_suspend()
1578 gpu->mmu_context = NULL; in etnaviv_gpu_hw_suspend()
1581 gpu->exec_state = -1; in etnaviv_gpu_hw_suspend()
1583 return etnaviv_gpu_clk_disable(gpu); in etnaviv_gpu_hw_suspend()
1587 static int etnaviv_gpu_hw_resume(struct etnaviv_gpu *gpu) in etnaviv_gpu_hw_resume() argument
1591 ret = mutex_lock_killable(&gpu->lock); in etnaviv_gpu_hw_resume()
1595 etnaviv_gpu_update_clock(gpu); in etnaviv_gpu_hw_resume()
1596 etnaviv_gpu_hw_init(gpu); in etnaviv_gpu_hw_resume()
1598 mutex_unlock(&gpu->lock); in etnaviv_gpu_hw_resume()
1617 struct etnaviv_gpu *gpu = cdev->devdata; in etnaviv_gpu_cooling_get_cur_state() local
1619 *state = gpu->freq_scale; in etnaviv_gpu_cooling_get_cur_state()
1628 struct etnaviv_gpu *gpu = cdev->devdata; in etnaviv_gpu_cooling_set_cur_state() local
1630 mutex_lock(&gpu->lock); in etnaviv_gpu_cooling_set_cur_state()
1631 gpu->freq_scale = state; in etnaviv_gpu_cooling_set_cur_state()
1632 if (!pm_runtime_suspended(gpu->dev)) in etnaviv_gpu_cooling_set_cur_state()
1633 etnaviv_gpu_update_clock(gpu); in etnaviv_gpu_cooling_set_cur_state()
1634 mutex_unlock(&gpu->lock); in etnaviv_gpu_cooling_set_cur_state()
1650 struct etnaviv_gpu *gpu = dev_get_drvdata(dev); in etnaviv_gpu_bind() local
1654 gpu->cooling = thermal_of_cooling_device_register(dev->of_node, in etnaviv_gpu_bind()
1655 (char *)dev_name(dev), gpu, &cooling_ops); in etnaviv_gpu_bind()
1656 if (IS_ERR(gpu->cooling)) in etnaviv_gpu_bind()
1657 return PTR_ERR(gpu->cooling); in etnaviv_gpu_bind()
1660 gpu->wq = alloc_ordered_workqueue(dev_name(dev), 0); in etnaviv_gpu_bind()
1661 if (!gpu->wq) { in etnaviv_gpu_bind()
1666 ret = etnaviv_sched_init(gpu); in etnaviv_gpu_bind()
1671 ret = pm_runtime_get_sync(gpu->dev); in etnaviv_gpu_bind()
1673 ret = etnaviv_gpu_clk_enable(gpu); in etnaviv_gpu_bind()
1679 gpu->drm = drm; in etnaviv_gpu_bind()
1680 gpu->fence_context = dma_fence_context_alloc(1); in etnaviv_gpu_bind()
1681 idr_init(&gpu->fence_idr); in etnaviv_gpu_bind()
1682 spin_lock_init(&gpu->fence_spinlock); in etnaviv_gpu_bind()
1684 INIT_WORK(&gpu->sync_point_work, sync_point_worker); in etnaviv_gpu_bind()
1685 init_waitqueue_head(&gpu->fence_event); in etnaviv_gpu_bind()
1687 priv->gpu[priv->num_gpus++] = gpu; in etnaviv_gpu_bind()
1689 pm_runtime_mark_last_busy(gpu->dev); in etnaviv_gpu_bind()
1690 pm_runtime_put_autosuspend(gpu->dev); in etnaviv_gpu_bind()
1695 etnaviv_sched_fini(gpu); in etnaviv_gpu_bind()
1698 destroy_workqueue(gpu->wq); in etnaviv_gpu_bind()
1702 thermal_cooling_device_unregister(gpu->cooling); in etnaviv_gpu_bind()
1710 struct etnaviv_gpu *gpu = dev_get_drvdata(dev); in etnaviv_gpu_unbind() local
1712 DBG("%s", dev_name(gpu->dev)); in etnaviv_gpu_unbind()
1714 flush_workqueue(gpu->wq); in etnaviv_gpu_unbind()
1715 destroy_workqueue(gpu->wq); in etnaviv_gpu_unbind()
1717 etnaviv_sched_fini(gpu); in etnaviv_gpu_unbind()
1720 pm_runtime_get_sync(gpu->dev); in etnaviv_gpu_unbind()
1721 pm_runtime_put_sync_suspend(gpu->dev); in etnaviv_gpu_unbind()
1723 etnaviv_gpu_hw_suspend(gpu); in etnaviv_gpu_unbind()
1726 if (gpu->initialized) { in etnaviv_gpu_unbind()
1727 etnaviv_cmdbuf_free(&gpu->buffer); in etnaviv_gpu_unbind()
1728 etnaviv_iommu_global_fini(gpu); in etnaviv_gpu_unbind()
1729 gpu->initialized = false; in etnaviv_gpu_unbind()
1732 gpu->drm = NULL; in etnaviv_gpu_unbind()
1733 idr_destroy(&gpu->fence_idr); in etnaviv_gpu_unbind()
1736 thermal_cooling_device_unregister(gpu->cooling); in etnaviv_gpu_unbind()
1737 gpu->cooling = NULL; in etnaviv_gpu_unbind()
1756 struct etnaviv_gpu *gpu; in etnaviv_gpu_platform_probe() local
1759 gpu = devm_kzalloc(dev, sizeof(*gpu), GFP_KERNEL); in etnaviv_gpu_platform_probe()
1760 if (!gpu) in etnaviv_gpu_platform_probe()
1763 gpu->dev = &pdev->dev; in etnaviv_gpu_platform_probe()
1764 mutex_init(&gpu->lock); in etnaviv_gpu_platform_probe()
1765 mutex_init(&gpu->fence_lock); in etnaviv_gpu_platform_probe()
1768 gpu->mmio = devm_platform_ioremap_resource(pdev, 0); in etnaviv_gpu_platform_probe()
1769 if (IS_ERR(gpu->mmio)) in etnaviv_gpu_platform_probe()
1770 return PTR_ERR(gpu->mmio); in etnaviv_gpu_platform_probe()
1773 gpu->irq = platform_get_irq(pdev, 0); in etnaviv_gpu_platform_probe()
1774 if (gpu->irq < 0) { in etnaviv_gpu_platform_probe()
1775 dev_err(dev, "failed to get irq: %d\n", gpu->irq); in etnaviv_gpu_platform_probe()
1776 return gpu->irq; in etnaviv_gpu_platform_probe()
1779 err = devm_request_irq(&pdev->dev, gpu->irq, irq_handler, 0, in etnaviv_gpu_platform_probe()
1780 dev_name(gpu->dev), gpu); in etnaviv_gpu_platform_probe()
1782 dev_err(dev, "failed to request IRQ%u: %d\n", gpu->irq, err); in etnaviv_gpu_platform_probe()
1787 gpu->clk_reg = devm_clk_get_optional(&pdev->dev, "reg"); in etnaviv_gpu_platform_probe()
1788 DBG("clk_reg: %p", gpu->clk_reg); in etnaviv_gpu_platform_probe()
1789 if (IS_ERR(gpu->clk_reg)) in etnaviv_gpu_platform_probe()
1790 return PTR_ERR(gpu->clk_reg); in etnaviv_gpu_platform_probe()
1792 gpu->clk_bus = devm_clk_get_optional(&pdev->dev, "bus"); in etnaviv_gpu_platform_probe()
1793 DBG("clk_bus: %p", gpu->clk_bus); in etnaviv_gpu_platform_probe()
1794 if (IS_ERR(gpu->clk_bus)) in etnaviv_gpu_platform_probe()
1795 return PTR_ERR(gpu->clk_bus); in etnaviv_gpu_platform_probe()
1797 gpu->clk_core = devm_clk_get(&pdev->dev, "core"); in etnaviv_gpu_platform_probe()
1798 DBG("clk_core: %p", gpu->clk_core); in etnaviv_gpu_platform_probe()
1799 if (IS_ERR(gpu->clk_core)) in etnaviv_gpu_platform_probe()
1800 return PTR_ERR(gpu->clk_core); in etnaviv_gpu_platform_probe()
1801 gpu->base_rate_core = clk_get_rate(gpu->clk_core); in etnaviv_gpu_platform_probe()
1803 gpu->clk_shader = devm_clk_get_optional(&pdev->dev, "shader"); in etnaviv_gpu_platform_probe()
1804 DBG("clk_shader: %p", gpu->clk_shader); in etnaviv_gpu_platform_probe()
1805 if (IS_ERR(gpu->clk_shader)) in etnaviv_gpu_platform_probe()
1806 return PTR_ERR(gpu->clk_shader); in etnaviv_gpu_platform_probe()
1807 gpu->base_rate_shader = clk_get_rate(gpu->clk_shader); in etnaviv_gpu_platform_probe()
1810 dev_set_drvdata(dev, gpu); in etnaviv_gpu_platform_probe()
1817 pm_runtime_use_autosuspend(gpu->dev); in etnaviv_gpu_platform_probe()
1818 pm_runtime_set_autosuspend_delay(gpu->dev, 200); in etnaviv_gpu_platform_probe()
1819 pm_runtime_enable(gpu->dev); in etnaviv_gpu_platform_probe()
1840 struct etnaviv_gpu *gpu = dev_get_drvdata(dev); in etnaviv_gpu_rpm_suspend() local
1844 if (atomic_read(&gpu->sched.hw_rq_count)) in etnaviv_gpu_rpm_suspend()
1848 mask = gpu->idle_mask & ~(VIVS_HI_IDLE_STATE_FE | in etnaviv_gpu_rpm_suspend()
1850 idle = gpu_read(gpu, VIVS_HI_IDLE_STATE) & mask; in etnaviv_gpu_rpm_suspend()
1852 dev_warn_ratelimited(dev, "GPU not yet idle, mask: 0x%08x\n", in etnaviv_gpu_rpm_suspend()
1857 return etnaviv_gpu_hw_suspend(gpu); in etnaviv_gpu_rpm_suspend()
1862 struct etnaviv_gpu *gpu = dev_get_drvdata(dev); in etnaviv_gpu_rpm_resume() local
1865 ret = etnaviv_gpu_clk_enable(gpu); in etnaviv_gpu_rpm_resume()
1870 if (gpu->drm && gpu->initialized) { in etnaviv_gpu_rpm_resume()
1871 ret = etnaviv_gpu_hw_resume(gpu); in etnaviv_gpu_rpm_resume()
1873 etnaviv_gpu_clk_disable(gpu); in etnaviv_gpu_rpm_resume()
1889 .name = "etnaviv-gpu",