Lines Matching +full:mipi +full:- +full:to +full:- +full:edp
1 // SPDX-License-Identifier: MIT
22 * Compression (DSC) used to compress the pixel bits before sending it on
23 * DP/eDP/MIPI DSI interface. DSC is required to be enabled so that the existing
27 * These functions contain some common logic and helpers to deal with VESA
28 * Display Stream Compression standard required for DSC on Display Port/eDP or
29 * MIPI display interfaces.
33 * drm_dsc_dp_pps_header_init() - Initializes the PPS Header
39 * picture parameter infoframes from the source to the sink.
47 pps_header->HB1 = DP_SDP_PPS; in drm_dsc_dp_pps_header_init()
48 pps_header->HB2 = DP_SDP_PPS_HEADER_PAYLOAD_BYTES_MINUS_1; in drm_dsc_dp_pps_header_init()
53 * drm_dsc_pps_payload_pack() - Populates the DSC PPS
63 * information required by the sink to decode the compressed frame. Driver
81 pps_payload->dsc_version = in drm_dsc_pps_payload_pack()
82 dsc_cfg->dsc_version_minor | in drm_dsc_pps_payload_pack()
83 dsc_cfg->dsc_version_major << DSC_PPS_VERSION_MAJOR_SHIFT; in drm_dsc_pps_payload_pack()
88 pps_payload->pps_3 = in drm_dsc_pps_payload_pack()
89 dsc_cfg->line_buf_depth | in drm_dsc_pps_payload_pack()
90 dsc_cfg->bits_per_component << DSC_PPS_BPC_SHIFT; in drm_dsc_pps_payload_pack()
93 pps_payload->pps_4 = in drm_dsc_pps_payload_pack()
94 ((dsc_cfg->bits_per_pixel & DSC_PPS_BPP_HIGH_MASK) >> in drm_dsc_pps_payload_pack()
96 dsc_cfg->vbr_enable << DSC_PPS_VBR_EN_SHIFT | in drm_dsc_pps_payload_pack()
97 dsc_cfg->simple_422 << DSC_PPS_SIMPLE422_SHIFT | in drm_dsc_pps_payload_pack()
98 dsc_cfg->convert_rgb << DSC_PPS_CONVERT_RGB_SHIFT | in drm_dsc_pps_payload_pack()
99 dsc_cfg->block_pred_enable << DSC_PPS_BLOCK_PRED_EN_SHIFT; in drm_dsc_pps_payload_pack()
102 pps_payload->bits_per_pixel_low = in drm_dsc_pps_payload_pack()
103 (dsc_cfg->bits_per_pixel & DSC_PPS_LSB_MASK); in drm_dsc_pps_payload_pack()
106 * The DSC panel expects the PPS packet to have big endian format in drm_dsc_pps_payload_pack()
107 * for data spanning 2 bytes. Use a macro cpu_to_be16() to convert in drm_dsc_pps_payload_pack()
108 * to big endian format. If format is little endian, it will swap in drm_dsc_pps_payload_pack()
109 * bytes to convert to Big endian else keep it unchanged. in drm_dsc_pps_payload_pack()
113 pps_payload->pic_height = cpu_to_be16(dsc_cfg->pic_height); in drm_dsc_pps_payload_pack()
116 pps_payload->pic_width = cpu_to_be16(dsc_cfg->pic_width); in drm_dsc_pps_payload_pack()
119 pps_payload->slice_height = cpu_to_be16(dsc_cfg->slice_height); in drm_dsc_pps_payload_pack()
122 pps_payload->slice_width = cpu_to_be16(dsc_cfg->slice_width); in drm_dsc_pps_payload_pack()
125 pps_payload->chunk_size = cpu_to_be16(dsc_cfg->slice_chunk_size); in drm_dsc_pps_payload_pack()
128 pps_payload->initial_xmit_delay_high = in drm_dsc_pps_payload_pack()
129 ((dsc_cfg->initial_xmit_delay & in drm_dsc_pps_payload_pack()
134 pps_payload->initial_xmit_delay_low = in drm_dsc_pps_payload_pack()
135 (dsc_cfg->initial_xmit_delay & DSC_PPS_LSB_MASK); in drm_dsc_pps_payload_pack()
138 pps_payload->initial_dec_delay = in drm_dsc_pps_payload_pack()
139 cpu_to_be16(dsc_cfg->initial_dec_delay); in drm_dsc_pps_payload_pack()
144 pps_payload->initial_scale_value = in drm_dsc_pps_payload_pack()
145 dsc_cfg->initial_scale_value; in drm_dsc_pps_payload_pack()
148 pps_payload->scale_increment_interval = in drm_dsc_pps_payload_pack()
149 cpu_to_be16(dsc_cfg->scale_increment_interval); in drm_dsc_pps_payload_pack()
152 pps_payload->scale_decrement_interval_high = in drm_dsc_pps_payload_pack()
153 ((dsc_cfg->scale_decrement_interval & in drm_dsc_pps_payload_pack()
158 pps_payload->scale_decrement_interval_low = in drm_dsc_pps_payload_pack()
159 (dsc_cfg->scale_decrement_interval & DSC_PPS_LSB_MASK); in drm_dsc_pps_payload_pack()
164 pps_payload->first_line_bpg_offset = in drm_dsc_pps_payload_pack()
165 dsc_cfg->first_line_bpg_offset; in drm_dsc_pps_payload_pack()
168 pps_payload->nfl_bpg_offset = in drm_dsc_pps_payload_pack()
169 cpu_to_be16(dsc_cfg->nfl_bpg_offset); in drm_dsc_pps_payload_pack()
172 pps_payload->slice_bpg_offset = in drm_dsc_pps_payload_pack()
173 cpu_to_be16(dsc_cfg->slice_bpg_offset); in drm_dsc_pps_payload_pack()
176 pps_payload->initial_offset = in drm_dsc_pps_payload_pack()
177 cpu_to_be16(dsc_cfg->initial_offset); in drm_dsc_pps_payload_pack()
180 pps_payload->final_offset = cpu_to_be16(dsc_cfg->final_offset); in drm_dsc_pps_payload_pack()
183 pps_payload->flatness_min_qp = dsc_cfg->flatness_min_qp; in drm_dsc_pps_payload_pack()
186 pps_payload->flatness_max_qp = dsc_cfg->flatness_max_qp; in drm_dsc_pps_payload_pack()
189 pps_payload->rc_model_size = in drm_dsc_pps_payload_pack()
193 pps_payload->rc_edge_factor = DSC_RC_EDGE_FACTOR_CONST; in drm_dsc_pps_payload_pack()
196 pps_payload->rc_quant_incr_limit0 = in drm_dsc_pps_payload_pack()
197 dsc_cfg->rc_quant_incr_limit0; in drm_dsc_pps_payload_pack()
200 pps_payload->rc_quant_incr_limit1 = in drm_dsc_pps_payload_pack()
201 dsc_cfg->rc_quant_incr_limit1; in drm_dsc_pps_payload_pack()
204 pps_payload->rc_tgt_offset = DSC_RC_TGT_OFFSET_LO_CONST | in drm_dsc_pps_payload_pack()
207 /* PPS 44 - 57 */ in drm_dsc_pps_payload_pack()
208 for (i = 0; i < DSC_NUM_BUF_RANGES - 1; i++) in drm_dsc_pps_payload_pack()
209 pps_payload->rc_buf_thresh[i] = in drm_dsc_pps_payload_pack()
210 dsc_cfg->rc_buf_thresh[i]; in drm_dsc_pps_payload_pack()
212 /* PPS 58 - 87 */ in drm_dsc_pps_payload_pack()
218 pps_payload->rc_range_parameters[i] = in drm_dsc_pps_payload_pack()
219 cpu_to_be16((dsc_cfg->rc_range_params[i].range_min_qp << in drm_dsc_pps_payload_pack()
221 (dsc_cfg->rc_range_params[i].range_max_qp << in drm_dsc_pps_payload_pack()
223 (dsc_cfg->rc_range_params[i].range_bpg_offset)); in drm_dsc_pps_payload_pack()
227 pps_payload->native_422_420 = dsc_cfg->native_422 | in drm_dsc_pps_payload_pack()
228 dsc_cfg->native_420 << DSC_PPS_NATIVE_420_SHIFT; in drm_dsc_pps_payload_pack()
231 pps_payload->second_line_bpg_offset = in drm_dsc_pps_payload_pack()
232 dsc_cfg->second_line_bpg_offset; in drm_dsc_pps_payload_pack()
235 pps_payload->nsl_bpg_offset = in drm_dsc_pps_payload_pack()
236 cpu_to_be16(dsc_cfg->nsl_bpg_offset); in drm_dsc_pps_payload_pack()
239 pps_payload->second_line_offset_adj = in drm_dsc_pps_payload_pack()
240 cpu_to_be16(dsc_cfg->second_line_offset_adj); in drm_dsc_pps_payload_pack()
242 /* PPS 94 - 127 are O */ in drm_dsc_pps_payload_pack()
247 * drm_dsc_compute_rc_parameters() - Write rate control
248 * parameters to the dsc configuration defined in
266 if (vdsc_cfg->native_420 || vdsc_cfg->native_422) { in drm_dsc_compute_rc_parameters()
267 /* Number of groups used to code each line of a slice */ in drm_dsc_compute_rc_parameters()
268 groups_per_line = DIV_ROUND_UP(vdsc_cfg->slice_width / 2, in drm_dsc_compute_rc_parameters()
272 vdsc_cfg->slice_chunk_size = DIV_ROUND_UP(vdsc_cfg->slice_width / 2 * in drm_dsc_compute_rc_parameters()
273 vdsc_cfg->bits_per_pixel, in drm_dsc_compute_rc_parameters()
276 /* Number of groups used to code each line of a slice */ in drm_dsc_compute_rc_parameters()
277 groups_per_line = DIV_ROUND_UP(vdsc_cfg->slice_width, in drm_dsc_compute_rc_parameters()
281 vdsc_cfg->slice_chunk_size = DIV_ROUND_UP(vdsc_cfg->slice_width * in drm_dsc_compute_rc_parameters()
282 vdsc_cfg->bits_per_pixel, in drm_dsc_compute_rc_parameters()
286 if (vdsc_cfg->convert_rgb) in drm_dsc_compute_rc_parameters()
287 num_extra_mux_bits = 3 * (vdsc_cfg->mux_word_size + in drm_dsc_compute_rc_parameters()
288 (4 * vdsc_cfg->bits_per_component + 4) in drm_dsc_compute_rc_parameters()
289 - 2); in drm_dsc_compute_rc_parameters()
290 else if (vdsc_cfg->native_422) in drm_dsc_compute_rc_parameters()
291 num_extra_mux_bits = 4 * vdsc_cfg->mux_word_size + in drm_dsc_compute_rc_parameters()
292 (4 * vdsc_cfg->bits_per_component + 4) + in drm_dsc_compute_rc_parameters()
293 3 * (4 * vdsc_cfg->bits_per_component) - 2; in drm_dsc_compute_rc_parameters()
295 num_extra_mux_bits = 3 * vdsc_cfg->mux_word_size + in drm_dsc_compute_rc_parameters()
296 (4 * vdsc_cfg->bits_per_component + 4) + in drm_dsc_compute_rc_parameters()
297 2 * (4 * vdsc_cfg->bits_per_component) - 2; in drm_dsc_compute_rc_parameters()
299 slice_bits = 8 * vdsc_cfg->slice_chunk_size * vdsc_cfg->slice_height; in drm_dsc_compute_rc_parameters()
302 ((slice_bits - num_extra_mux_bits) % vdsc_cfg->mux_word_size)) in drm_dsc_compute_rc_parameters()
303 num_extra_mux_bits--; in drm_dsc_compute_rc_parameters()
305 if (groups_per_line < vdsc_cfg->initial_scale_value - 8) in drm_dsc_compute_rc_parameters()
306 vdsc_cfg->initial_scale_value = groups_per_line + 8; in drm_dsc_compute_rc_parameters()
308 /* scale_decrement_interval calculation according to DSC spec 1.11 */ in drm_dsc_compute_rc_parameters()
309 if (vdsc_cfg->initial_scale_value > 8) in drm_dsc_compute_rc_parameters()
310 vdsc_cfg->scale_decrement_interval = groups_per_line / in drm_dsc_compute_rc_parameters()
311 (vdsc_cfg->initial_scale_value - 8); in drm_dsc_compute_rc_parameters()
313 vdsc_cfg->scale_decrement_interval = DSC_SCALE_DECREMENT_INTERVAL_MAX; in drm_dsc_compute_rc_parameters()
315 vdsc_cfg->final_offset = vdsc_cfg->rc_model_size - in drm_dsc_compute_rc_parameters()
316 (vdsc_cfg->initial_xmit_delay * in drm_dsc_compute_rc_parameters()
317 vdsc_cfg->bits_per_pixel + 8) / 16 + num_extra_mux_bits; in drm_dsc_compute_rc_parameters()
319 if (vdsc_cfg->final_offset >= vdsc_cfg->rc_model_size) { in drm_dsc_compute_rc_parameters()
321 return -ERANGE; in drm_dsc_compute_rc_parameters()
324 final_scale = (vdsc_cfg->rc_model_size * 8) / in drm_dsc_compute_rc_parameters()
325 (vdsc_cfg->rc_model_size - vdsc_cfg->final_offset); in drm_dsc_compute_rc_parameters()
326 if (vdsc_cfg->slice_height > 1) in drm_dsc_compute_rc_parameters()
332 vdsc_cfg->nfl_bpg_offset = DIV_ROUND_UP((vdsc_cfg->first_line_bpg_offset << 11), in drm_dsc_compute_rc_parameters()
333 (vdsc_cfg->slice_height - 1)); in drm_dsc_compute_rc_parameters()
335 vdsc_cfg->nfl_bpg_offset = 0; in drm_dsc_compute_rc_parameters()
337 /* Number of groups used to code the entire slice */ in drm_dsc_compute_rc_parameters()
338 groups_total = groups_per_line * vdsc_cfg->slice_height; in drm_dsc_compute_rc_parameters()
341 vdsc_cfg->slice_bpg_offset = DIV_ROUND_UP(((vdsc_cfg->rc_model_size - in drm_dsc_compute_rc_parameters()
342 vdsc_cfg->initial_offset + in drm_dsc_compute_rc_parameters()
349 * finaloffset/((NflBpgOffset + SliceBpgOffset)*8(finalscale - 1.125)) in drm_dsc_compute_rc_parameters()
353 vdsc_cfg->scale_increment_interval = in drm_dsc_compute_rc_parameters()
354 (vdsc_cfg->final_offset * (1 << 11)) / in drm_dsc_compute_rc_parameters()
355 ((vdsc_cfg->nfl_bpg_offset + in drm_dsc_compute_rc_parameters()
356 vdsc_cfg->slice_bpg_offset) * in drm_dsc_compute_rc_parameters()
357 (final_scale - 9)); in drm_dsc_compute_rc_parameters()
360 * If finalScaleValue is less than or equal to 9, a value of 0 should in drm_dsc_compute_rc_parameters()
361 * be used to disable the scale increment at the end of the slice in drm_dsc_compute_rc_parameters()
363 vdsc_cfg->scale_increment_interval = 0; in drm_dsc_compute_rc_parameters()
371 rbs_min = vdsc_cfg->rc_model_size - vdsc_cfg->initial_offset + in drm_dsc_compute_rc_parameters()
372 DIV_ROUND_UP(vdsc_cfg->initial_xmit_delay * in drm_dsc_compute_rc_parameters()
373 vdsc_cfg->bits_per_pixel, 16) + in drm_dsc_compute_rc_parameters()
374 groups_per_line * vdsc_cfg->first_line_bpg_offset; in drm_dsc_compute_rc_parameters()
376 hrd_delay = DIV_ROUND_UP((rbs_min * 16), vdsc_cfg->bits_per_pixel); in drm_dsc_compute_rc_parameters()
377 vdsc_cfg->rc_bits = (hrd_delay * vdsc_cfg->bits_per_pixel) / 16; in drm_dsc_compute_rc_parameters()
378 vdsc_cfg->initial_dec_delay = hrd_delay - vdsc_cfg->initial_xmit_delay; in drm_dsc_compute_rc_parameters()