Lines Matching +full:mipi +full:- +full:to +full:- +full:edp
1 // SPDX-License-Identifier: GPL-2.0
96 /* fudge factor required to account for 8b/10b encoding */
110 * struct ti_sn_bridge - Platform data for ti-sn65dsi86 driver.
111 * @dev: Pointer to our device.
118 * @dsi: Our MIPI DSI source.
121 * @enable_gpio: The GPIO we toggle to enable the bridge.
124 * @ln_assign: Value to program to the LN_ASSIGN register.
125 * @ln_polrs: Value for the 4-bit LN_POLRS field of SN_ENH_FRAME_REG.
128 * @gchip_output: A cache of whether we've set GPIOs to output. This
129 * serves double-duty of keeping track of the direction and
135 * each other's read-modify-write.
179 regmap_write(pdata->regmap, reg, val & 0xFF); in ti_sn_bridge_write_u16()
180 regmap_write(pdata->regmap, reg + 1, val >> 8); in ti_sn_bridge_write_u16()
188 ret = regulator_bulk_enable(SN_REGULATOR_SUPPLY_NUM, pdata->supplies); in ti_sn_bridge_resume()
190 DRM_ERROR("failed to enable supplies %d\n", ret); in ti_sn_bridge_resume()
194 gpiod_set_value(pdata->enable_gpio, 1); in ti_sn_bridge_resume()
204 gpiod_set_value(pdata->enable_gpio, 0); in ti_sn_bridge_suspend()
206 ret = regulator_bulk_disable(SN_REGULATOR_SUPPLY_NUM, pdata->supplies); in ti_sn_bridge_suspend()
208 DRM_ERROR("failed to disable supplies %d\n", ret); in ti_sn_bridge_suspend()
221 struct ti_sn_bridge *pdata = s->private; in status_show()
226 pm_runtime_get_sync(pdata->dev); in status_show()
230 regmap_read(pdata->regmap, reg, &val); in status_show()
234 pm_runtime_put(pdata->dev); in status_show()
243 pdata->debugfs = debugfs_create_dir(dev_name(pdata->dev), NULL); in ti_sn_debugfs_init()
245 debugfs_create_file("status", 0600, pdata->debugfs, pdata, in ti_sn_debugfs_init()
251 debugfs_remove_recursive(pdata->debugfs); in ti_sn_debugfs_remove()
252 pdata->debugfs = NULL; in ti_sn_debugfs_remove()
266 return drm_panel_get_modes(pdata->panel, connector); in ti_sn_bridge_connector_get_modes()
274 if (mode->clock > 594000) in ti_sn_bridge_connector_mode_valid()
290 * return the status as connected. Need to add support to detect in ti_sn_bridge_connector_detect()
318 pdata->supplies[i].supply = ti_sn_bridge_supply_names[i]; in ti_sn_bridge_parse_regulators()
320 return devm_regulator_bulk_get(pdata->dev, SN_REGULATOR_SUPPLY_NUM, in ti_sn_bridge_parse_regulators()
321 pdata->supplies); in ti_sn_bridge_parse_regulators()
337 DRM_ERROR("Fix bridge driver to make connector optional!"); in ti_sn_bridge_attach()
338 return -EINVAL; in ti_sn_bridge_attach()
341 ret = drm_connector_init(bridge->dev, &pdata->connector, in ti_sn_bridge_attach()
345 DRM_ERROR("Failed to initialize connector with drm\n"); in ti_sn_bridge_attach()
349 drm_connector_helper_add(&pdata->connector, in ti_sn_bridge_attach()
351 drm_connector_attach_encoder(&pdata->connector, bridge->encoder); in ti_sn_bridge_attach()
355 * to be done in bridge probe. But some existing DSI host drivers will in ti_sn_bridge_attach()
356 * wait for any of the drm_bridge/drm_panel to get added to the global in ti_sn_bridge_attach()
362 * is fixed we can move the below code to bridge probe safely. in ti_sn_bridge_attach()
364 host = of_find_mipi_dsi_host_by_node(pdata->host_node); in ti_sn_bridge_attach()
366 DRM_ERROR("failed to find dsi host\n"); in ti_sn_bridge_attach()
367 ret = -ENODEV; in ti_sn_bridge_attach()
373 DRM_ERROR("failed to create dsi device\n"); in ti_sn_bridge_attach()
378 /* TODO: setting to 4 MIPI lanes always for now */ in ti_sn_bridge_attach()
379 dsi->lanes = 4; in ti_sn_bridge_attach()
380 dsi->format = MIPI_DSI_FMT_RGB888; in ti_sn_bridge_attach()
381 dsi->mode_flags = MIPI_DSI_MODE_VIDEO; in ti_sn_bridge_attach()
384 pm_runtime_get_sync(pdata->dev); in ti_sn_bridge_attach()
385 regmap_read(pdata->regmap, SN_DPPLL_SRC_REG, &val); in ti_sn_bridge_attach()
386 pm_runtime_put(pdata->dev); in ti_sn_bridge_attach()
388 dsi->mode_flags |= MIPI_DSI_CLOCK_NON_CONTINUOUS; in ti_sn_bridge_attach()
392 DRM_ERROR("failed to attach dsi to host\n"); in ti_sn_bridge_attach()
395 pdata->dsi = dsi; in ti_sn_bridge_attach()
402 drm_connector_cleanup(&pdata->connector); in ti_sn_bridge_attach()
410 drm_panel_disable(pdata->panel); in ti_sn_bridge_disable()
413 regmap_update_bits(pdata->regmap, SN_ENH_FRAME_REG, VSTREAM_ENABLE, 0); in ti_sn_bridge_disable()
415 regmap_write(pdata->regmap, SN_ML_TX_MODE_REG, 0); in ti_sn_bridge_disable()
417 regmap_write(pdata->regmap, SN_PLL_ENABLE_REG, 0); in ti_sn_bridge_disable()
419 drm_panel_unprepare(pdata->panel); in ti_sn_bridge_disable()
426 &pdata->bridge.encoder->crtc->state->adjusted_mode; in ti_sn_bridge_get_dsi_freq()
428 bit_rate_khz = mode->clock * in ti_sn_bridge_get_dsi_freq()
429 mipi_dsi_pixel_format_to_bpp(pdata->dsi->format); in ti_sn_bridge_get_dsi_freq()
430 clk_freq_khz = bit_rate_khz / (pdata->dsi->lanes * 2); in ti_sn_bridge_get_dsi_freq()
460 if (pdata->refclk) { in ti_sn_bridge_set_refclk_freq()
461 refclk_rate = clk_get_rate(pdata->refclk); in ti_sn_bridge_set_refclk_freq()
464 clk_prepare_enable(pdata->refclk); in ti_sn_bridge_set_refclk_freq()
471 /* for i equals to refclk_lut_size means default frequency */ in ti_sn_bridge_set_refclk_freq()
476 regmap_update_bits(pdata->regmap, SN_DPPLL_SRC_REG, REFCLK_FREQ_MASK, in ti_sn_bridge_set_refclk_freq()
485 &pdata->bridge.encoder->crtc->state->adjusted_mode; in ti_sn_bridge_set_dsi_rate()
488 bit_rate_mhz = (mode->clock / 1000) * in ti_sn_bridge_set_dsi_rate()
489 mipi_dsi_pixel_format_to_bpp(pdata->dsi->format); in ti_sn_bridge_set_dsi_rate()
490 clk_freq_mhz = bit_rate_mhz / (pdata->dsi->lanes * 2); in ti_sn_bridge_set_dsi_rate()
494 (((clk_freq_mhz - MIN_DSI_CLK_FREQ_MHZ) / 5) & 0xFF); in ti_sn_bridge_set_dsi_rate()
495 regmap_write(pdata->regmap, SN_DSIA_CLK_FREQ_REG, val); in ti_sn_bridge_set_dsi_rate()
500 if (pdata->connector.display_info.bpc <= 6) in ti_sn_bridge_get_bpp()
507 * LUT index corresponds to register value and
508 * LUT values corresponds to dp data rate supported
520 &pdata->bridge.encoder->crtc->state->adjusted_mode; in ti_sn_bridge_calc_min_dp_rate_idx()
523 bit_rate_khz = mode->clock * ti_sn_bridge_get_bpp(pdata); in ti_sn_bridge_calc_min_dp_rate_idx()
527 1000 * pdata->dp_lanes * DP_CLK_FUDGE_DEN); in ti_sn_bridge_calc_min_dp_rate_idx()
529 for (i = 1; i < ARRAY_SIZE(ti_sn_bridge_dp_rate_lut) - 1; i++) in ti_sn_bridge_calc_min_dp_rate_idx()
545 ret = drm_dp_dpcd_readb(&pdata->aux, DP_EDP_DPCD_REV, &dpcd_val); in ti_sn_bridge_read_valid_rates()
547 DRM_DEV_ERROR(pdata->dev, in ti_sn_bridge_read_valid_rates()
548 "Can't read eDP rev (%d), assuming 1.1\n", ret); in ti_sn_bridge_read_valid_rates()
553 /* eDP 1.4 devices must provide a custom table */ in ti_sn_bridge_read_valid_rates()
556 ret = drm_dp_dpcd_read(&pdata->aux, DP_SUPPORTED_LINK_RATES, in ti_sn_bridge_read_valid_rates()
560 DRM_DEV_ERROR(pdata->dev, in ti_sn_bridge_read_valid_rates()
563 /* By zeroing we'll fall back to DP_MAX_LINK_RATE. */ in ti_sn_bridge_read_valid_rates()
586 DRM_DEV_ERROR(pdata->dev, in ti_sn_bridge_read_valid_rates()
587 "No matching eDP rates in table; falling back\n"); in ti_sn_bridge_read_valid_rates()
591 ret = drm_dp_dpcd_readb(&pdata->aux, DP_MAX_LINK_RATE, &dpcd_val); in ti_sn_bridge_read_valid_rates()
593 DRM_DEV_ERROR(pdata->dev, in ti_sn_bridge_read_valid_rates()
601 DRM_DEV_ERROR(pdata->dev, in ti_sn_bridge_read_valid_rates()
620 &pdata->bridge.encoder->crtc->state->adjusted_mode; in ti_sn_bridge_set_video_timings()
623 if (mode->flags & DRM_MODE_FLAG_PHSYNC) in ti_sn_bridge_set_video_timings()
625 if (mode->flags & DRM_MODE_FLAG_PVSYNC) in ti_sn_bridge_set_video_timings()
629 mode->hdisplay); in ti_sn_bridge_set_video_timings()
631 mode->vdisplay); in ti_sn_bridge_set_video_timings()
632 regmap_write(pdata->regmap, SN_CHA_HSYNC_PULSE_WIDTH_LOW_REG, in ti_sn_bridge_set_video_timings()
633 (mode->hsync_end - mode->hsync_start) & 0xFF); in ti_sn_bridge_set_video_timings()
634 regmap_write(pdata->regmap, SN_CHA_HSYNC_PULSE_WIDTH_HIGH_REG, in ti_sn_bridge_set_video_timings()
635 (((mode->hsync_end - mode->hsync_start) >> 8) & 0x7F) | in ti_sn_bridge_set_video_timings()
637 regmap_write(pdata->regmap, SN_CHA_VSYNC_PULSE_WIDTH_LOW_REG, in ti_sn_bridge_set_video_timings()
638 (mode->vsync_end - mode->vsync_start) & 0xFF); in ti_sn_bridge_set_video_timings()
639 regmap_write(pdata->regmap, SN_CHA_VSYNC_PULSE_WIDTH_HIGH_REG, in ti_sn_bridge_set_video_timings()
640 (((mode->vsync_end - mode->vsync_start) >> 8) & 0x7F) | in ti_sn_bridge_set_video_timings()
643 regmap_write(pdata->regmap, SN_CHA_HORIZONTAL_BACK_PORCH_REG, in ti_sn_bridge_set_video_timings()
644 (mode->htotal - mode->hsync_end) & 0xFF); in ti_sn_bridge_set_video_timings()
645 regmap_write(pdata->regmap, SN_CHA_VERTICAL_BACK_PORCH_REG, in ti_sn_bridge_set_video_timings()
646 (mode->vtotal - mode->vsync_end) & 0xFF); in ti_sn_bridge_set_video_timings()
648 regmap_write(pdata->regmap, SN_CHA_HORIZONTAL_FRONT_PORCH_REG, in ti_sn_bridge_set_video_timings()
649 (mode->hsync_start - mode->hdisplay) & 0xFF); in ti_sn_bridge_set_video_timings()
650 regmap_write(pdata->regmap, SN_CHA_VERTICAL_FRONT_PORCH_REG, in ti_sn_bridge_set_video_timings()
651 (mode->vsync_start - mode->vdisplay) & 0xFF); in ti_sn_bridge_set_video_timings()
661 ret = drm_dp_dpcd_readb(&pdata->aux, DP_MAX_LANE_COUNT, &data); in ti_sn_get_max_lanes()
663 DRM_DEV_ERROR(pdata->dev, in ti_sn_get_max_lanes()
678 regmap_update_bits(pdata->regmap, SN_DATARATE_CONFIG_REG, in ti_sn_link_training()
682 regmap_write(pdata->regmap, SN_PLL_ENABLE_REG, 1); in ti_sn_link_training()
684 ret = regmap_read_poll_timeout(pdata->regmap, SN_DPPLL_SRC_REG, val, in ti_sn_link_training()
693 regmap_write(pdata->regmap, SN_ML_TX_MODE_REG, 0x0A); in ti_sn_link_training()
694 ret = regmap_read_poll_timeout(pdata->regmap, SN_ML_TX_MODE_REG, val, in ti_sn_link_training()
702 ret = -EIO; in ti_sn_link_training()
708 regmap_write(pdata->regmap, SN_PLL_ENABLE_REG, 0); in ti_sn_link_training()
720 int ret = -EINVAL; in ti_sn_bridge_enable()
724 pdata->dp_lanes = min(pdata->dp_lanes, max_dp_lanes); in ti_sn_bridge_enable()
727 val = CHA_DSI_LANES(SN_MAX_DP_LANES - pdata->dsi->lanes); in ti_sn_bridge_enable()
728 regmap_update_bits(pdata->regmap, SN_DSI_LANES_REG, in ti_sn_bridge_enable()
731 regmap_write(pdata->regmap, SN_LN_ASSIGN_REG, pdata->ln_assign); in ti_sn_bridge_enable()
732 regmap_update_bits(pdata->regmap, SN_ENH_FRAME_REG, LN_POLRS_MASK, in ti_sn_bridge_enable()
733 pdata->ln_polrs << LN_POLRS_OFFSET); in ti_sn_bridge_enable()
740 * this method is enabled by default. An eDP panel must support this in ti_sn_bridge_enable()
741 * authentication method. We need to enable this method in the eDP panel in ti_sn_bridge_enable()
742 * at DisplayPort address 0x0010A prior to link training. in ti_sn_bridge_enable()
744 drm_dp_dpcd_writeb(&pdata->aux, DP_EDP_CONFIGURATION_SET, in ti_sn_bridge_enable()
749 regmap_update_bits(pdata->regmap, SN_DATA_FORMAT_REG, BPP_18_RGB, val); in ti_sn_bridge_enable()
752 val = DP_NUM_LANES(min(pdata->dp_lanes, 3)); in ti_sn_bridge_enable()
753 regmap_update_bits(pdata->regmap, SN_SSC_CONFIG_REG, DP_NUM_LANES_MASK, in ti_sn_bridge_enable()
770 DRM_DEV_ERROR(pdata->dev, "%s (%d)\n", last_err_str, ret); in ti_sn_bridge_enable()
778 regmap_update_bits(pdata->regmap, SN_ENH_FRAME_REG, VSTREAM_ENABLE, in ti_sn_bridge_enable()
781 drm_panel_enable(pdata->panel); in ti_sn_bridge_enable()
788 pm_runtime_get_sync(pdata->dev); in ti_sn_bridge_pre_enable()
794 * HPD on this bridge chip is a bit useless. This is an eDP bridge in ti_sn_bridge_pre_enable()
795 * so the HPD is an internal signal that's only there to signal that in ti_sn_bridge_pre_enable()
798 * voltage, and temperate--I measured it at about 200 ms). One in ti_sn_bridge_pre_enable()
805 * If HPD somehow makes sense on some future panel we'll have to in ti_sn_bridge_pre_enable()
806 * change this to be conditional on someone specifying that HPD should in ti_sn_bridge_pre_enable()
809 regmap_update_bits(pdata->regmap, SN_HPD_DISABLE_REG, HPD_DISABLE, in ti_sn_bridge_pre_enable()
812 drm_panel_prepare(pdata->panel); in ti_sn_bridge_pre_enable()
819 if (pdata->refclk) in ti_sn_bridge_post_disable()
820 clk_disable_unprepare(pdata->refclk); in ti_sn_bridge_post_disable()
822 pm_runtime_put_sync(pdata->dev); in ti_sn_bridge_post_disable()
842 u32 request = msg->request & ~DP_AUX_I2C_MOT; in ti_sn_aux_transfer()
843 u32 request_val = AUX_CMD_REQ(msg->request); in ti_sn_aux_transfer()
844 u8 *buf = (u8 *)msg->buffer; in ti_sn_aux_transfer()
848 if (msg->size > SN_AUX_MAX_PAYLOAD_BYTES) in ti_sn_aux_transfer()
849 return -EINVAL; in ti_sn_aux_transfer()
856 regmap_write(pdata->regmap, SN_AUX_CMD_REG, request_val); in ti_sn_aux_transfer()
859 return -EINVAL; in ti_sn_aux_transfer()
862 regmap_write(pdata->regmap, SN_AUX_ADDR_19_16_REG, in ti_sn_aux_transfer()
863 (msg->address >> 16) & 0xF); in ti_sn_aux_transfer()
864 regmap_write(pdata->regmap, SN_AUX_ADDR_15_8_REG, in ti_sn_aux_transfer()
865 (msg->address >> 8) & 0xFF); in ti_sn_aux_transfer()
866 regmap_write(pdata->regmap, SN_AUX_ADDR_7_0_REG, msg->address & 0xFF); in ti_sn_aux_transfer()
868 regmap_write(pdata->regmap, SN_AUX_LENGTH_REG, msg->size); in ti_sn_aux_transfer()
871 for (i = 0; i < msg->size; i++) in ti_sn_aux_transfer()
872 regmap_write(pdata->regmap, SN_AUX_WDATA_REG(i), in ti_sn_aux_transfer()
877 regmap_write(pdata->regmap, SN_AUX_CMD_STATUS_REG, in ti_sn_aux_transfer()
882 regmap_write(pdata->regmap, SN_AUX_CMD_REG, request_val | AUX_CMD_SEND); in ti_sn_aux_transfer()
884 ret = regmap_read_poll_timeout(pdata->regmap, SN_AUX_CMD_REG, val, in ti_sn_aux_transfer()
890 ret = regmap_read(pdata->regmap, SN_AUX_CMD_STATUS_REG, &val); in ti_sn_aux_transfer()
896 return -ENXIO; in ti_sn_aux_transfer()
899 return msg->size; in ti_sn_aux_transfer()
901 for (i = 0; i < msg->size; i++) { in ti_sn_aux_transfer()
903 ret = regmap_read(pdata->regmap, SN_AUX_RDATA_REG(i), in ti_sn_aux_transfer()
912 return msg->size; in ti_sn_aux_transfer()
917 struct device_node *np = pdata->dev->of_node; in ti_sn_bridge_parse_dsi_host()
919 pdata->host_node = of_graph_get_remote_node(np, 0, 0); in ti_sn_bridge_parse_dsi_host()
921 if (!pdata->host_node) { in ti_sn_bridge_parse_dsi_host()
923 return -ENODEV; in ti_sn_bridge_parse_dsi_host()
935 if (WARN_ON(gpiospec->args_count < chip->of_gpio_n_cells)) in tn_sn_bridge_of_xlate()
936 return -EINVAL; in tn_sn_bridge_of_xlate()
938 if (gpiospec->args[0] > chip->ngpio || gpiospec->args[0] < 1) in tn_sn_bridge_of_xlate()
939 return -EINVAL; in tn_sn_bridge_of_xlate()
942 *flags = gpiospec->args[1]; in tn_sn_bridge_of_xlate()
944 return gpiospec->args[0] - SN_GPIO_PHYSICAL_OFFSET; in tn_sn_bridge_of_xlate()
953 * We already have to keep track of the direction because we use in ti_sn_bridge_gpio_get_direction()
954 * that to figure out whether we've powered the device. We can in ti_sn_bridge_gpio_get_direction()
956 * to ask its direction. in ti_sn_bridge_gpio_get_direction()
958 return test_bit(offset, pdata->gchip_output) ? in ti_sn_bridge_gpio_get_direction()
970 * powered--we just power it on to read the pin. NOTE: part of in ti_sn_bridge_gpio_get()
972 * powered back on) to all 4 GPIOs being configured as GPIO input. in ti_sn_bridge_gpio_get()
976 pm_runtime_get_sync(pdata->dev); in ti_sn_bridge_gpio_get()
977 ret = regmap_read(pdata->regmap, SN_GPIO_IO_REG, &val); in ti_sn_bridge_gpio_get()
978 pm_runtime_put(pdata->dev); in ti_sn_bridge_gpio_get()
992 if (!test_bit(offset, pdata->gchip_output)) { in ti_sn_bridge_gpio_set()
993 dev_err(pdata->dev, "Ignoring GPIO set while input\n"); in ti_sn_bridge_gpio_set()
998 ret = regmap_update_bits(pdata->regmap, SN_GPIO_IO_REG, in ti_sn_bridge_gpio_set()
1002 dev_warn(pdata->dev, in ti_sn_bridge_gpio_set()
1003 "Failed to set bridge GPIO %u: %d\n", offset, ret); in ti_sn_bridge_gpio_set()
1013 if (!test_and_clear_bit(offset, pdata->gchip_output)) in ti_sn_bridge_gpio_direction_input()
1016 ret = regmap_update_bits(pdata->regmap, SN_GPIO_CTRL_REG, in ti_sn_bridge_gpio_direction_input()
1020 set_bit(offset, pdata->gchip_output); in ti_sn_bridge_gpio_direction_input()
1029 pm_runtime_put(pdata->dev); in ti_sn_bridge_gpio_direction_input()
1041 if (test_and_set_bit(offset, pdata->gchip_output)) in ti_sn_bridge_gpio_direction_output()
1044 pm_runtime_get_sync(pdata->dev); in ti_sn_bridge_gpio_direction_output()
1046 /* Set value first to avoid glitching */ in ti_sn_bridge_gpio_direction_output()
1050 ret = regmap_update_bits(pdata->regmap, SN_GPIO_CTRL_REG, in ti_sn_bridge_gpio_direction_output()
1054 clear_bit(offset, pdata->gchip_output); in ti_sn_bridge_gpio_direction_output()
1055 pm_runtime_put(pdata->dev); in ti_sn_bridge_gpio_direction_output()
1075 /* Only init if someone is going to use us as a GPIO controller */ in ti_sn_setup_gpio_controller()
1076 if (!of_property_read_bool(pdata->dev->of_node, "gpio-controller")) in ti_sn_setup_gpio_controller()
1079 pdata->gchip.label = dev_name(pdata->dev); in ti_sn_setup_gpio_controller()
1080 pdata->gchip.parent = pdata->dev; in ti_sn_setup_gpio_controller()
1081 pdata->gchip.owner = THIS_MODULE; in ti_sn_setup_gpio_controller()
1082 pdata->gchip.of_xlate = tn_sn_bridge_of_xlate; in ti_sn_setup_gpio_controller()
1083 pdata->gchip.of_gpio_n_cells = 2; in ti_sn_setup_gpio_controller()
1084 pdata->gchip.free = ti_sn_bridge_gpio_free; in ti_sn_setup_gpio_controller()
1085 pdata->gchip.get_direction = ti_sn_bridge_gpio_get_direction; in ti_sn_setup_gpio_controller()
1086 pdata->gchip.direction_input = ti_sn_bridge_gpio_direction_input; in ti_sn_setup_gpio_controller()
1087 pdata->gchip.direction_output = ti_sn_bridge_gpio_direction_output; in ti_sn_setup_gpio_controller()
1088 pdata->gchip.get = ti_sn_bridge_gpio_get; in ti_sn_setup_gpio_controller()
1089 pdata->gchip.set = ti_sn_bridge_gpio_set; in ti_sn_setup_gpio_controller()
1090 pdata->gchip.can_sleep = true; in ti_sn_setup_gpio_controller()
1091 pdata->gchip.names = ti_sn_bridge_gpio_names; in ti_sn_setup_gpio_controller()
1092 pdata->gchip.ngpio = SN_NUM_GPIOS; in ti_sn_setup_gpio_controller()
1093 pdata->gchip.base = -1; in ti_sn_setup_gpio_controller()
1094 ret = devm_gpiochip_add_data(pdata->dev, &pdata->gchip, pdata); in ti_sn_setup_gpio_controller()
1096 dev_err(pdata->dev, "can't add gpio chip\n"); in ti_sn_setup_gpio_controller()
1124 * normal polarity if nothing is specified. It's OK to specify just in ti_sn_bridge_parse_lanes()
1125 * data-lanes but not lane-polarities but not vice versa. in ti_sn_bridge_parse_lanes()
1131 endpoint = of_graph_get_endpoint_by_regs(np, 1, -1); in ti_sn_bridge_parse_lanes()
1132 dp_lanes = of_property_count_u32_elems(endpoint, "data-lanes"); in ti_sn_bridge_parse_lanes()
1134 of_property_read_u32_array(endpoint, "data-lanes", in ti_sn_bridge_parse_lanes()
1136 of_property_read_u32_array(endpoint, "lane-polarities", in ti_sn_bridge_parse_lanes()
1145 * data-lanes had fewer elements so that we nicely initialize in ti_sn_bridge_parse_lanes()
1148 for (i = SN_MAX_DP_LANES - 1; i >= 0; i--) { in ti_sn_bridge_parse_lanes()
1154 pdata->dp_lanes = dp_lanes; in ti_sn_bridge_parse_lanes()
1155 pdata->ln_assign = ln_assign; in ti_sn_bridge_parse_lanes()
1156 pdata->ln_polrs = ln_polrs; in ti_sn_bridge_parse_lanes()
1165 if (!i2c_check_functionality(client->adapter, I2C_FUNC_I2C)) { in ti_sn_bridge_probe()
1167 return -ENODEV; in ti_sn_bridge_probe()
1170 pdata = devm_kzalloc(&client->dev, sizeof(struct ti_sn_bridge), in ti_sn_bridge_probe()
1173 return -ENOMEM; in ti_sn_bridge_probe()
1175 pdata->regmap = devm_regmap_init_i2c(client, in ti_sn_bridge_probe()
1177 if (IS_ERR(pdata->regmap)) { in ti_sn_bridge_probe()
1179 return PTR_ERR(pdata->regmap); in ti_sn_bridge_probe()
1182 pdata->dev = &client->dev; in ti_sn_bridge_probe()
1184 ret = drm_of_find_panel_or_bridge(pdata->dev->of_node, 1, 0, in ti_sn_bridge_probe()
1185 &pdata->panel, NULL); in ti_sn_bridge_probe()
1191 dev_set_drvdata(&client->dev, pdata); in ti_sn_bridge_probe()
1193 pdata->enable_gpio = devm_gpiod_get(pdata->dev, "enable", in ti_sn_bridge_probe()
1195 if (IS_ERR(pdata->enable_gpio)) { in ti_sn_bridge_probe()
1196 DRM_ERROR("failed to get enable gpio from DT\n"); in ti_sn_bridge_probe()
1197 ret = PTR_ERR(pdata->enable_gpio); in ti_sn_bridge_probe()
1201 ti_sn_bridge_parse_lanes(pdata, client->dev.of_node); in ti_sn_bridge_probe()
1205 DRM_ERROR("failed to parse regulators\n"); in ti_sn_bridge_probe()
1209 pdata->refclk = devm_clk_get(pdata->dev, "refclk"); in ti_sn_bridge_probe()
1210 if (IS_ERR(pdata->refclk)) { in ti_sn_bridge_probe()
1211 ret = PTR_ERR(pdata->refclk); in ti_sn_bridge_probe()
1212 if (ret == -EPROBE_DEFER) in ti_sn_bridge_probe()
1215 pdata->refclk = NULL; in ti_sn_bridge_probe()
1222 pm_runtime_enable(pdata->dev); in ti_sn_bridge_probe()
1226 pm_runtime_disable(pdata->dev); in ti_sn_bridge_probe()
1232 pdata->aux.name = "ti-sn65dsi86-aux"; in ti_sn_bridge_probe()
1233 pdata->aux.dev = pdata->dev; in ti_sn_bridge_probe()
1234 pdata->aux.transfer = ti_sn_aux_transfer; in ti_sn_bridge_probe()
1235 drm_dp_aux_register(&pdata->aux); in ti_sn_bridge_probe()
1237 pdata->bridge.funcs = &ti_sn_bridge_funcs; in ti_sn_bridge_probe()
1238 pdata->bridge.of_node = client->dev.of_node; in ti_sn_bridge_probe()
1240 drm_bridge_add(&pdata->bridge); in ti_sn_bridge_probe()
1252 return -EINVAL; in ti_sn_bridge_remove()
1256 of_node_put(pdata->host_node); in ti_sn_bridge_remove()
1258 pm_runtime_disable(pdata->dev); in ti_sn_bridge_remove()
1260 if (pdata->dsi) { in ti_sn_bridge_remove()
1261 mipi_dsi_detach(pdata->dsi); in ti_sn_bridge_remove()
1262 mipi_dsi_device_unregister(pdata->dsi); in ti_sn_bridge_remove()
1265 drm_bridge_remove(&pdata->bridge); in ti_sn_bridge_remove()
1295 MODULE_DESCRIPTION("sn65dsi86 DSI to eDP bridge driver");