37 		.regs_offset = 0x40,
38 		.id = 0,
40 		.cfgs_offset = 0x2c,
46 		.clut_offset = 0x400,
51 	.min_width = 0,
52 	.min_height = 0,
55 	.max_spw = 0x3f,
56 	.max_vpw = 0x3f,
57 	.max_hpw = 0xff,
67 		.regs_offset = 0x40,
68 		.id = 0,
70 		.cfgs_offset = 0x2c,
78 		.clut_offset = 0x400,
83 		.regs_offset = 0x100,
86 		.cfgs_offset = 0x2c,
97 		.clut_offset = 0x800,
102 		.regs_offset = 0x280,
105 		.cfgs_offset = 0x4c,
119 		.clut_offset = 0x1000,
124 		.regs_offset = 0x340,
129 		.cfgs_offset = 0x2c,
139 		.clut_offset = 0x1400,
144 	.min_width = 0,
145 	.min_height = 0,
148 	.max_spw = 0x3f,
149 	.max_vpw = 0x3f,
150 	.max_hpw = 0xff,
160 		.regs_offset = 0x40,
161 		.id = 0,
163 		.cfgs_offset = 0x2c,
171 		.clut_offset = 0x600,
176 		.regs_offset = 0x140,
179 		.cfgs_offset = 0x2c,
190 		.clut_offset = 0xa00,
195 		.regs_offset = 0x240,
198 		.cfgs_offset = 0x2c,
209 		.clut_offset = 0xe00,
214 		.regs_offset = 0x340,
217 		.cfgs_offset = 0x4c,
235 		.clut_offset = 0x1200,
240 		.regs_offset = 0x440,
245 		.cfgs_offset = 0x2c,
257 		.clut_offset = 0x1600,
262 	.min_width = 0,
263 	.min_height = 0,
266 	.max_spw = 0x3f,
267 	.max_vpw = 0x3f,
268 	.max_hpw = 0x1ff,
278 		.regs_offset = 0x40,
279 		.id = 0,
281 		.cfgs_offset = 0x2c,
289 		.clut_offset = 0x600,
294 		.regs_offset = 0x140,
297 		.cfgs_offset = 0x2c,
308 		.clut_offset = 0xa00,
313 		.regs_offset = 0x240,
316 		.cfgs_offset = 0x2c,
327 		.clut_offset = 0xe00,
332 		.regs_offset = 0x340,
335 		.cfgs_offset = 0x4c,
353 		.clut_offset = 0x1200,
358 	.min_width = 0,
359 	.min_height = 0,
362 	.max_spw = 0xff,
363 	.max_vpw = 0xff,
364 	.max_hpw = 0x3ff,
373 		.regs_offset = 0x60,
374 		.id = 0,
376 		.cfgs_offset = 0x2c,
384 		.clut_offset = 0x600,
389 		.regs_offset = 0x160,
392 		.cfgs_offset = 0x2c,
403 		.clut_offset = 0xa00,
408 		.regs_offset = 0x260,
411 		.cfgs_offset = 0x2c,
422 		.clut_offset = 0xe00,
427 		.regs_offset = 0x360,
430 		.cfgs_offset = 0x4c,
448 		.clut_offset = 0x1200,
453 	.min_width = 0,
454 	.min_height = 0,
457 	.max_spw = 0xff,
458 	.max_vpw = 0xff,
459 	.max_hpw = 0x3ff,
517 	    vback_porch > dc->desc->max_vpw || vback_porch < 0 ||  in atmel_hlcdc_dc_mode_valid()
552 	for (i = 0; i < ATMEL_HLCDC_MAX_LAYERS; i++) {  in atmel_hlcdc_dc_irq_handler()
575 	drm_atomic_helper_commit_planes(dev, old_state, 0);  in atmel_hlcdc_dc_atomic_complete()
627 	if (ret == 0)  in atmel_hlcdc_dc_atomic_commit()
635 	BUG_ON(drm_atomic_helper_swap_state(state, false) < 0);  in atmel_hlcdc_dc_atomic_commit()
644 	return 0;  in atmel_hlcdc_dc_atomic_commit()
690 	return 0;  in atmel_hlcdc_dc_modeset_init()
715 	dc->wq = alloc_ordered_workqueue("atmel-hlcdc-dc", 0);  in atmel_hlcdc_dc_load()
733 	if (ret < 0) {  in atmel_hlcdc_dc_load()
739 	if (ret < 0) {  in atmel_hlcdc_dc_load()
749 	if (ret < 0) {  in atmel_hlcdc_dc_load()
758 	return 0;  in atmel_hlcdc_dc_load()
793 	unsigned int cfg = 0;  in atmel_hlcdc_dc_irq_postinstall()
797 	for (i = 0; i < ATMEL_HLCDC_MAX_LAYERS; i++) {  in atmel_hlcdc_dc_irq_postinstall()
804 	return 0;  in atmel_hlcdc_dc_irq_postinstall()
812 	regmap_write(dc->hlcdc->regmap, ATMEL_HLCDC_IDR, 0xffffffff);  in atmel_hlcdc_dc_irq_uninstall()
830 	.minor = 0,
846 	ret = drm_dev_register(ddev, 0);  in atmel_hlcdc_dc_drm_probe()
852 	return 0;  in atmel_hlcdc_dc_drm_probe()
871 	return 0;  in atmel_hlcdc_dc_drm_remove()
892 	return 0;  in atmel_hlcdc_dc_drm_suspend()