Lines Matching full:table
421 pr_err("vdd_dep_on_sclk table is NULL\n"); in ci_populate_single_graphic_level()
585 "The CAC Leakage table does not exist!", return -EINVAL); in ci_populate_bapm_vddc_vid_sidd()
773 "The SCLK/VDDC Dependency Table does not exist.\n", in ci_get_std_voltage_value_sidd()
777 pr_warn("CAC Leakage Table does not exist, using vddc.\n"); in ci_get_std_voltage_value_sidd()
788 …warn("Index from SCLK/VDDC Dependency Table exceeds the CAC Leakage Table index, using maximum ind… in ci_get_std_voltage_value_sidd()
804 …ex from SCLK/VDDC Dependency Table exceeds the CAC Leakage Table index in second look up, using ma… in ci_get_std_voltage_value_sidd()
813 pr_warn("Unable to get std_vddc from SCLK/VDDC Dependency Table, using vddc.\n"); in ci_get_std_voltage_value_sidd()
841 SMU7_Discrete_DpmTable *table) in ci_populate_smc_vddc_table() argument
847 table->VddcLevelCount = data->vddc_voltage_table.count; in ci_populate_smc_vddc_table()
848 for (count = 0; count < table->VddcLevelCount; count++) { in ci_populate_smc_vddc_table()
851 &(table->VddcLevel[count])); in ci_populate_smc_vddc_table()
852 PP_ASSERT_WITH_CODE(0 == result, "do not populate SMC VDDC voltage table", return -EINVAL); in ci_populate_smc_vddc_table()
856 table->VddcLevel[count].Smio = (uint8_t) count; in ci_populate_smc_vddc_table()
857 table->Smio[count] |= data->vddc_voltage_table.entries[count].smio_low; in ci_populate_smc_vddc_table()
858 table->SmioMaskVddcVid |= data->vddc_voltage_table.entries[count].smio_low; in ci_populate_smc_vddc_table()
860 table->VddcLevel[count].Smio = 0; in ci_populate_smc_vddc_table()
864 CONVERT_FROM_HOST_TO_SMC_UL(table->VddcLevelCount); in ci_populate_smc_vddc_table()
870 SMU7_Discrete_DpmTable *table) in ci_populate_smc_vdd_ci_table() argument
876 table->VddciLevelCount = data->vddci_voltage_table.count; in ci_populate_smc_vdd_ci_table()
878 for (count = 0; count < table->VddciLevelCount; count++) { in ci_populate_smc_vdd_ci_table()
881 &(table->VddciLevel[count])); in ci_populate_smc_vdd_ci_table()
882 PP_ASSERT_WITH_CODE(result == 0, "do not populate SMC VDDCI voltage table", return -EINVAL); in ci_populate_smc_vdd_ci_table()
884 table->VddciLevel[count].Smio = (uint8_t) count; in ci_populate_smc_vdd_ci_table()
885 table->Smio[count] |= data->vddci_voltage_table.entries[count].smio_low; in ci_populate_smc_vdd_ci_table()
886 table->SmioMaskVddciVid |= data->vddci_voltage_table.entries[count].smio_low; in ci_populate_smc_vdd_ci_table()
888 table->VddciLevel[count].Smio = 0; in ci_populate_smc_vdd_ci_table()
892 CONVERT_FROM_HOST_TO_SMC_UL(table->VddciLevelCount); in ci_populate_smc_vdd_ci_table()
898 SMU7_Discrete_DpmTable *table) in ci_populate_smc_mvdd_table() argument
904 table->MvddLevelCount = data->mvdd_voltage_table.count; in ci_populate_smc_mvdd_table()
906 for (count = 0; count < table->MvddLevelCount; count++) { in ci_populate_smc_mvdd_table()
909 &table->MvddLevel[count]); in ci_populate_smc_mvdd_table()
910 PP_ASSERT_WITH_CODE(result == 0, "do not populate SMC mvdd voltage table", return -EINVAL); in ci_populate_smc_mvdd_table()
912 table->MvddLevel[count].Smio = (uint8_t) count; in ci_populate_smc_mvdd_table()
913 table->Smio[count] |= data->mvdd_voltage_table.entries[count].smio_low; in ci_populate_smc_mvdd_table()
914 table->SmioMaskMvddVid |= data->mvdd_voltage_table.entries[count].smio_low; in ci_populate_smc_mvdd_table()
916 table->MvddLevel[count].Smio = 0; in ci_populate_smc_mvdd_table()
920 CONVERT_FROM_HOST_TO_SMC_UL(table->MvddLevelCount); in ci_populate_smc_mvdd_table()
927 SMU7_Discrete_DpmTable *table) in ci_populate_smc_voltage_tables() argument
931 result = ci_populate_smc_vddc_table(hwmgr, table); in ci_populate_smc_voltage_tables()
933 "can not populate VDDC voltage table to SMC", return -EINVAL); in ci_populate_smc_voltage_tables()
935 result = ci_populate_smc_vdd_ci_table(hwmgr, table); in ci_populate_smc_voltage_tables()
937 "can not populate VDDCI voltage table to SMC", return -EINVAL); in ci_populate_smc_voltage_tables()
939 result = ci_populate_smc_mvdd_table(hwmgr, table); in ci_populate_smc_voltage_tables()
941 "can not populate MVDD voltage table to SMC", return -EINVAL); in ci_populate_smc_voltage_tables()
996 static int ci_populate_smc_link_level(struct pp_hwmgr *hwmgr, SMU7_Discrete_DpmTable *table) in ci_populate_smc_link_level() argument
1005 table->LinkLevel[i].PcieGenSpeed = in ci_populate_smc_link_level()
1007 table->LinkLevel[i].PcieLaneCount = in ci_populate_smc_link_level()
1009 table->LinkLevel[i].EnabledForActivity = 1; in ci_populate_smc_link_level()
1010 table->LinkLevel[i].DownT = PP_HOST_TO_SMC_UL(5); in ci_populate_smc_link_level()
1011 table->LinkLevel[i].UpT = PP_HOST_TO_SMC_UL(30); in ci_populate_smc_link_level()
1190 "can not find MinVddc voltage value from memory VDDC voltage dependency table", return result); in ci_populate_single_memory_level()
1199 "can not find MinVddci voltage value from memory VDDCI voltage dependency table", return result); in ci_populate_single_memory_level()
1208 "can not find MinVddci voltage value from memory MVDD voltage dependency table", return result); in ci_populate_single_memory_level()
1377 SMU7_Discrete_DpmTable *table) in ci_populate_smc_acpi_level() argument
1391 table->ACPILevel.Flags &= ~PPSMC_SWSTATE_FLAG_DC; in ci_populate_smc_acpi_level()
1394 table->ACPILevel.MinVddc = PP_HOST_TO_SMC_UL(data->acpi_vddc * VOLTAGE_SCALE); in ci_populate_smc_acpi_level()
1396 table->ACPILevel.MinVddc = PP_HOST_TO_SMC_UL(data->min_vddc_in_pptable * VOLTAGE_SCALE); in ci_populate_smc_acpi_level()
1398 table->ACPILevel.MinVddcPhases = data->vddc_phase_shed_control ? 0 : 1; in ci_populate_smc_acpi_level()
1400 table->ACPILevel.SclkFrequency = atomctrl_get_reference_clock(hwmgr); in ci_populate_smc_acpi_level()
1404 table->ACPILevel.SclkFrequency, ÷rs); in ci_populate_smc_acpi_level()
1410 table->ACPILevel.SclkDid = (uint8_t)dividers.pll_post_divider; in ci_populate_smc_acpi_level()
1411 table->ACPILevel.DisplayWatermark = PPSMC_DISPLAY_WATERMARK_LOW; in ci_populate_smc_acpi_level()
1412 table->ACPILevel.DeepSleepDivId = 0; in ci_populate_smc_acpi_level()
1421 table->ACPILevel.CgSpllFuncCntl = spll_func_cntl; in ci_populate_smc_acpi_level()
1422 table->ACPILevel.CgSpllFuncCntl2 = spll_func_cntl_2; in ci_populate_smc_acpi_level()
1423 table->ACPILevel.CgSpllFuncCntl3 = data->clock_registers.vCG_SPLL_FUNC_CNTL_3; in ci_populate_smc_acpi_level()
1424 table->ACPILevel.CgSpllFuncCntl4 = data->clock_registers.vCG_SPLL_FUNC_CNTL_4; in ci_populate_smc_acpi_level()
1425 table->ACPILevel.SpllSpreadSpectrum = data->clock_registers.vCG_SPLL_SPREAD_SPECTRUM; in ci_populate_smc_acpi_level()
1426 table->ACPILevel.SpllSpreadSpectrum2 = data->clock_registers.vCG_SPLL_SPREAD_SPECTRUM_2; in ci_populate_smc_acpi_level()
1427 table->ACPILevel.CcPwrDynRm = 0; in ci_populate_smc_acpi_level()
1428 table->ACPILevel.CcPwrDynRm1 = 0; in ci_populate_smc_acpi_level()
1431 CONVERT_FROM_HOST_TO_SMC_UL(table->ACPILevel.Flags); in ci_populate_smc_acpi_level()
1433 CONVERT_FROM_HOST_TO_SMC_UL(table->ACPILevel.SclkFrequency); in ci_populate_smc_acpi_level()
1434 CONVERT_FROM_HOST_TO_SMC_UL(table->ACPILevel.CgSpllFuncCntl); in ci_populate_smc_acpi_level()
1435 CONVERT_FROM_HOST_TO_SMC_UL(table->ACPILevel.CgSpllFuncCntl2); in ci_populate_smc_acpi_level()
1436 CONVERT_FROM_HOST_TO_SMC_UL(table->ACPILevel.CgSpllFuncCntl3); in ci_populate_smc_acpi_level()
1437 CONVERT_FROM_HOST_TO_SMC_UL(table->ACPILevel.CgSpllFuncCntl4); in ci_populate_smc_acpi_level()
1438 CONVERT_FROM_HOST_TO_SMC_UL(table->ACPILevel.SpllSpreadSpectrum); in ci_populate_smc_acpi_level()
1439 CONVERT_FROM_HOST_TO_SMC_UL(table->ACPILevel.SpllSpreadSpectrum2); in ci_populate_smc_acpi_level()
1440 CONVERT_FROM_HOST_TO_SMC_UL(table->ACPILevel.CcPwrDynRm); in ci_populate_smc_acpi_level()
1441 CONVERT_FROM_HOST_TO_SMC_UL(table->ACPILevel.CcPwrDynRm1); in ci_populate_smc_acpi_level()
1444 /* table->MemoryACPILevel.MinVddcPhases = table->ACPILevel.MinVddcPhases;*/ in ci_populate_smc_acpi_level()
1445 table->MemoryACPILevel.MinVddc = table->ACPILevel.MinVddc; in ci_populate_smc_acpi_level()
1446 table->MemoryACPILevel.MinVddcPhases = table->ACPILevel.MinVddcPhases; in ci_populate_smc_acpi_level()
1449 table->MemoryACPILevel.MinVddci = table->MemoryACPILevel.MinVddc; in ci_populate_smc_acpi_level()
1452 table->MemoryACPILevel.MinVddci = PP_HOST_TO_SMC_UL(data->acpi_vddci * VOLTAGE_SCALE); in ci_populate_smc_acpi_level()
1454 table->MemoryACPILevel.MinVddci = PP_HOST_TO_SMC_UL(data->min_vddci_in_pptable * VOLTAGE_SCALE); in ci_populate_smc_acpi_level()
1458 table->MemoryACPILevel.MinMvdd = in ci_populate_smc_acpi_level()
1461 table->MemoryACPILevel.MinMvdd = 0; in ci_populate_smc_acpi_level()
1481 table->MemoryACPILevel.DllCntl = in ci_populate_smc_acpi_level()
1483 table->MemoryACPILevel.MclkPwrmgtCntl = in ci_populate_smc_acpi_level()
1485 table->MemoryACPILevel.MpllAdFuncCntl = in ci_populate_smc_acpi_level()
1487 table->MemoryACPILevel.MpllDqFuncCntl = in ci_populate_smc_acpi_level()
1489 table->MemoryACPILevel.MpllFuncCntl = in ci_populate_smc_acpi_level()
1491 table->MemoryACPILevel.MpllFuncCntl_1 = in ci_populate_smc_acpi_level()
1493 table->MemoryACPILevel.MpllFuncCntl_2 = in ci_populate_smc_acpi_level()
1495 table->MemoryACPILevel.MpllSs1 = in ci_populate_smc_acpi_level()
1497 table->MemoryACPILevel.MpllSs2 = in ci_populate_smc_acpi_level()
1500 table->MemoryACPILevel.EnabledForThrottle = 0; in ci_populate_smc_acpi_level()
1501 table->MemoryACPILevel.EnabledForActivity = 0; in ci_populate_smc_acpi_level()
1502 table->MemoryACPILevel.UpH = 0; in ci_populate_smc_acpi_level()
1503 table->MemoryACPILevel.DownH = 100; in ci_populate_smc_acpi_level()
1504 table->MemoryACPILevel.VoltageDownH = 0; in ci_populate_smc_acpi_level()
1506 …table->MemoryACPILevel.ActivityLevel = PP_HOST_TO_SMC_US(data->current_profile_setting.mclk_activi… in ci_populate_smc_acpi_level()
1508 table->MemoryACPILevel.StutterEnable = 0; in ci_populate_smc_acpi_level()
1509 table->MemoryACPILevel.StrobeEnable = 0; in ci_populate_smc_acpi_level()
1510 table->MemoryACPILevel.EdcReadEnable = 0; in ci_populate_smc_acpi_level()
1511 table->MemoryACPILevel.EdcWriteEnable = 0; in ci_populate_smc_acpi_level()
1512 table->MemoryACPILevel.RttEnable = 0; in ci_populate_smc_acpi_level()
1518 SMU7_Discrete_DpmTable *table) in ci_populate_smc_uvd_level() argument
1526 table->UvdLevelCount = (uint8_t)(uvd_table->count); in ci_populate_smc_uvd_level()
1528 for (count = 0; count < table->UvdLevelCount; count++) { in ci_populate_smc_uvd_level()
1529 table->UvdLevel[count].VclkFrequency = in ci_populate_smc_uvd_level()
1531 table->UvdLevel[count].DclkFrequency = in ci_populate_smc_uvd_level()
1533 table->UvdLevel[count].MinVddc = in ci_populate_smc_uvd_level()
1535 table->UvdLevel[count].MinVddcPhases = 1; in ci_populate_smc_uvd_level()
1538 table->UvdLevel[count].VclkFrequency, ÷rs); in ci_populate_smc_uvd_level()
1542 table->UvdLevel[count].VclkDivider = (uint8_t)dividers.pll_post_divider; in ci_populate_smc_uvd_level()
1545 table->UvdLevel[count].DclkFrequency, ÷rs); in ci_populate_smc_uvd_level()
1549 table->UvdLevel[count].DclkDivider = (uint8_t)dividers.pll_post_divider; in ci_populate_smc_uvd_level()
1550 CONVERT_FROM_HOST_TO_SMC_UL(table->UvdLevel[count].VclkFrequency); in ci_populate_smc_uvd_level()
1551 CONVERT_FROM_HOST_TO_SMC_UL(table->UvdLevel[count].DclkFrequency); in ci_populate_smc_uvd_level()
1552 CONVERT_FROM_HOST_TO_SMC_US(table->UvdLevel[count].MinVddc); in ci_populate_smc_uvd_level()
1559 SMU7_Discrete_DpmTable *table) in ci_populate_smc_vce_level() argument
1567 table->VceLevelCount = (uint8_t)(vce_table->count); in ci_populate_smc_vce_level()
1568 table->VceBootLevel = 0; in ci_populate_smc_vce_level()
1570 for (count = 0; count < table->VceLevelCount; count++) { in ci_populate_smc_vce_level()
1571 table->VceLevel[count].Frequency = vce_table->entries[count].evclk; in ci_populate_smc_vce_level()
1572 table->VceLevel[count].MinVoltage = in ci_populate_smc_vce_level()
1574 table->VceLevel[count].MinPhases = 1; in ci_populate_smc_vce_level()
1577 table->VceLevel[count].Frequency, ÷rs); in ci_populate_smc_vce_level()
1582 table->VceLevel[count].Divider = (uint8_t)dividers.pll_post_divider; in ci_populate_smc_vce_level()
1584 CONVERT_FROM_HOST_TO_SMC_UL(table->VceLevel[count].Frequency); in ci_populate_smc_vce_level()
1585 CONVERT_FROM_HOST_TO_SMC_US(table->VceLevel[count].MinVoltage); in ci_populate_smc_vce_level()
1591 SMU7_Discrete_DpmTable *table) in ci_populate_smc_acp_level() argument
1599 table->AcpLevelCount = (uint8_t)(acp_table->count); in ci_populate_smc_acp_level()
1600 table->AcpBootLevel = 0; in ci_populate_smc_acp_level()
1602 for (count = 0; count < table->AcpLevelCount; count++) { in ci_populate_smc_acp_level()
1603 table->AcpLevel[count].Frequency = acp_table->entries[count].acpclk; in ci_populate_smc_acp_level()
1604 table->AcpLevel[count].MinVoltage = acp_table->entries[count].v; in ci_populate_smc_acp_level()
1605 table->AcpLevel[count].MinPhases = 1; in ci_populate_smc_acp_level()
1608 table->AcpLevel[count].Frequency, ÷rs); in ci_populate_smc_acp_level()
1612 table->AcpLevel[count].Divider = (uint8_t)dividers.pll_post_divider; in ci_populate_smc_acp_level()
1614 CONVERT_FROM_HOST_TO_SMC_UL(table->AcpLevel[count].Frequency); in ci_populate_smc_acp_level()
1615 CONVERT_FROM_HOST_TO_SMC_US(table->AcpLevel[count].MinVoltage); in ci_populate_smc_acp_level()
1685 SMU7_Discrete_DpmTable *table) in ci_populate_smc_boot_level() argument
1691 table->GraphicsBootLevel = 0; in ci_populate_smc_boot_level()
1692 table->MemoryBootLevel = 0; in ci_populate_smc_boot_level()
1694 /* find boot level from dpm table*/ in ci_populate_smc_boot_level()
1701 …pr_err("VBIOS did not find boot engine clock value in dependency table. Using Graphics DPM level 0… in ci_populate_smc_boot_level()
1711 …pr_err("VBIOS did not find boot engine clock value in dependency table. Using Memory DPM level 0!\… in ci_populate_smc_boot_level()
1715 table->BootVddc = data->vbios_boot_state.vddc_bootup_value; in ci_populate_smc_boot_level()
1716 table->BootVddci = data->vbios_boot_state.vddci_bootup_value; in ci_populate_smc_boot_level()
1717 table->BootMVdd = data->vbios_boot_state.mvdd_bootup_value; in ci_populate_smc_boot_level()
1883 SMU7_Discrete_DpmTable *table) in ci_populate_smc_svi2_config() argument
1888 table->SVI2Enable = 1; in ci_populate_smc_svi2_config()
1890 table->SVI2Enable = 0; in ci_populate_smc_svi2_config()
1910 static int ci_populate_vr_config(struct pp_hwmgr *hwmgr, SMU7_Discrete_DpmTable *table) in ci_populate_vr_config() argument
1916 table->VRConfig |= (config<<VRCONF_VDDGFX_SHIFT); in ci_populate_vr_config()
1920 table->VRConfig |= config; in ci_populate_vr_config()
1927 table->VRConfig |= (config<<VRCONF_VDDCI_SHIFT); in ci_populate_vr_config()
1930 table->VRConfig |= (config<<VRCONF_VDDCI_SHIFT); in ci_populate_vr_config()
1935 table->VRConfig |= (config<<VRCONF_MVDD_SHIFT); in ci_populate_vr_config()
1946 SMU7_Discrete_DpmTable *table = &(smu_data->smc_state_table); in ci_init_smc_table() local
1954 ci_populate_smc_voltage_tables(hwmgr, table); in ci_init_smc_table()
1958 table->SystemFlags |= PPSMC_SYSTEMFLAG_GPIO_DC; in ci_init_smc_table()
1963 table->SystemFlags |= PPSMC_SYSTEMFLAG_STEPVDDC; in ci_init_smc_table()
1966 table->SystemFlags |= PPSMC_SYSTEMFLAG_GDDR5; in ci_init_smc_table()
1969 result = ci_populate_ulv_state(hwmgr, &(table->Ulv)); in ci_init_smc_table()
1985 result = ci_populate_smc_link_level(hwmgr, table); in ci_init_smc_table()
1989 result = ci_populate_smc_acpi_level(hwmgr, table); in ci_init_smc_table()
1993 result = ci_populate_smc_vce_level(hwmgr, table); in ci_init_smc_table()
1997 result = ci_populate_smc_acp_level(hwmgr, table); in ci_init_smc_table()
2007 result = ci_populate_smc_uvd_level(hwmgr, table); in ci_init_smc_table()
2011 table->UvdBootLevel = 0; in ci_init_smc_table()
2012 table->VceBootLevel = 0; in ci_init_smc_table()
2013 table->AcpBootLevel = 0; in ci_init_smc_table()
2014 table->SamuBootLevel = 0; in ci_init_smc_table()
2016 table->GraphicsBootLevel = 0; in ci_init_smc_table()
2017 table->MemoryBootLevel = 0; in ci_init_smc_table()
2019 result = ci_populate_smc_boot_level(hwmgr, table); in ci_init_smc_table()
2029 table->UVDInterval = 1; in ci_init_smc_table()
2030 table->VCEInterval = 1; in ci_init_smc_table()
2031 table->ACPInterval = 1; in ci_init_smc_table()
2032 table->SAMUInterval = 1; in ci_init_smc_table()
2033 table->GraphicsVoltageChangeEnable = 1; in ci_init_smc_table()
2034 table->GraphicsThermThrottleEnable = 1; in ci_init_smc_table()
2035 table->GraphicsInterval = 1; in ci_init_smc_table()
2036 table->VoltageInterval = 1; in ci_init_smc_table()
2037 table->ThermalInterval = 1; in ci_init_smc_table()
2039 table->TemperatureLimitHigh = in ci_init_smc_table()
2042 table->TemperatureLimitLow = in ci_init_smc_table()
2046 table->MemoryVoltageChangeEnable = 1; in ci_init_smc_table()
2047 table->MemoryInterval = 1; in ci_init_smc_table()
2048 table->VoltageResponseTime = 0; in ci_init_smc_table()
2049 table->VddcVddciDelta = 4000; in ci_init_smc_table()
2050 table->PhaseResponseTime = 0; in ci_init_smc_table()
2051 table->MemoryThermThrottleEnable = 1; in ci_init_smc_table()
2057 table->PCIeBootLinkLevel = (uint8_t)data->dpm_table.pcie_speed_table.count; in ci_init_smc_table()
2058 table->PCIeGenInterval = 1; in ci_init_smc_table()
2060 result = ci_populate_vr_config(hwmgr, table); in ci_init_smc_table()
2063 data->vr_config = table->VRConfig; in ci_init_smc_table()
2065 ci_populate_smc_svi2_config(hwmgr, table); in ci_init_smc_table()
2068 CONVERT_FROM_HOST_TO_SMC_UL(table->Smio[i]); in ci_init_smc_table()
2070 table->ThermGpio = 17; in ci_init_smc_table()
2071 table->SclkStepSize = 0x4000; in ci_init_smc_table()
2073 table->VRHotGpio = gpio_pin.uc_gpio_pin_bit_shift; in ci_init_smc_table()
2077 table->VRHotGpio = SMU7_UNUSED_GPIO_PIN; in ci_init_smc_table()
2082 table->AcDcGpio = SMU7_UNUSED_GPIO_PIN; in ci_init_smc_table()
2084 CONVERT_FROM_HOST_TO_SMC_UL(table->SystemFlags); in ci_init_smc_table()
2085 CONVERT_FROM_HOST_TO_SMC_UL(table->VRConfig); in ci_init_smc_table()
2086 CONVERT_FROM_HOST_TO_SMC_UL(table->SmioMaskVddcVid); in ci_init_smc_table()
2087 CONVERT_FROM_HOST_TO_SMC_UL(table->SmioMaskVddcPhase); in ci_init_smc_table()
2088 CONVERT_FROM_HOST_TO_SMC_UL(table->SmioMaskVddciVid); in ci_init_smc_table()
2089 CONVERT_FROM_HOST_TO_SMC_UL(table->SmioMaskMvddVid); in ci_init_smc_table()
2090 CONVERT_FROM_HOST_TO_SMC_UL(table->SclkStepSize); in ci_init_smc_table()
2091 CONVERT_FROM_HOST_TO_SMC_US(table->TemperatureLimitHigh); in ci_init_smc_table()
2092 CONVERT_FROM_HOST_TO_SMC_US(table->TemperatureLimitLow); in ci_init_smc_table()
2093 table->VddcVddciDelta = PP_HOST_TO_SMC_US(table->VddcVddciDelta); in ci_init_smc_table()
2094 CONVERT_FROM_HOST_TO_SMC_US(table->VoltageResponseTime); in ci_init_smc_table()
2095 CONVERT_FROM_HOST_TO_SMC_US(table->PhaseResponseTime); in ci_init_smc_table()
2097 table->BootVddc = PP_HOST_TO_SMC_US(table->BootVddc * VOLTAGE_SCALE); in ci_init_smc_table()
2098 table->BootVddci = PP_HOST_TO_SMC_US(table->BootVddci * VOLTAGE_SCALE); in ci_init_smc_table()
2099 table->BootMVdd = PP_HOST_TO_SMC_US(table->BootMVdd * VOLTAGE_SCALE); in ci_init_smc_table()
2104 (uint8_t *)&(table->SystemFlags), in ci_init_smc_table()
2113 "Failed to populate initialize MC Reg table!", return result); in ci_init_smc_table()
2238 PP_ASSERT_WITH_CODE((0 == result), "Failed to upload MC reg table!", return result); in ci_update_sclk_threshold()
2539 static int ci_set_s0_mc_reg_index(struct ci_mc_reg_table *table) in ci_set_s0_mc_reg_index() argument
2544 for (i = 0; i < table->last; i++) { in ci_set_s0_mc_reg_index()
2545 table->mc_reg_address[i].s0 = in ci_set_s0_mc_reg_index()
2546 ci_check_s0_mc_reg_index(table->mc_reg_address[i].s1, &address) in ci_set_s0_mc_reg_index()
2547 ? address : table->mc_reg_address[i].s1; in ci_set_s0_mc_reg_index()
2552 static int ci_copy_vbios_smc_reg_table(const pp_atomctrl_mc_reg_table *table, in ci_copy_vbios_smc_reg_table() argument
2557 PP_ASSERT_WITH_CODE((table->last <= SMU7_DISCRETE_MC_REGISTER_ARRAY_SIZE), in ci_copy_vbios_smc_reg_table()
2558 "Invalid VramInfo table.", return -EINVAL); in ci_copy_vbios_smc_reg_table()
2559 PP_ASSERT_WITH_CODE((table->num_entries <= MAX_AC_TIMING_ENTRIES), in ci_copy_vbios_smc_reg_table()
2560 "Invalid VramInfo table.", return -EINVAL); in ci_copy_vbios_smc_reg_table()
2562 for (i = 0; i < table->last; i++) in ci_copy_vbios_smc_reg_table()
2563 ni_table->mc_reg_address[i].s1 = table->mc_reg_address[i].s1; in ci_copy_vbios_smc_reg_table()
2565 ni_table->last = table->last; in ci_copy_vbios_smc_reg_table()
2567 for (i = 0; i < table->num_entries; i++) { in ci_copy_vbios_smc_reg_table()
2569 table->mc_reg_table_entry[i].mclk_max; in ci_copy_vbios_smc_reg_table()
2570 for (j = 0; j < table->last; j++) { in ci_copy_vbios_smc_reg_table()
2572 table->mc_reg_table_entry[i].mc_data[j]; in ci_copy_vbios_smc_reg_table()
2576 ni_table->num_entries = table->num_entries; in ci_copy_vbios_smc_reg_table()
2582 struct ci_mc_reg_table *table) in ci_set_mc_special_registers() argument
2588 for (i = 0, j = table->last; i < table->last; i++) { in ci_set_mc_special_registers()
2590 "Invalid VramInfo table.", return -EINVAL); in ci_set_mc_special_registers()
2592 switch (table->mc_reg_address[i].s1) { in ci_set_mc_special_registers()
2596 table->mc_reg_address[j].s1 = mmMC_PMG_CMD_EMRS; in ci_set_mc_special_registers()
2597 table->mc_reg_address[j].s0 = mmMC_SEQ_PMG_CMD_EMRS_LP; in ci_set_mc_special_registers()
2598 for (k = 0; k < table->num_entries; k++) { in ci_set_mc_special_registers()
2599 table->mc_reg_table_entry[k].mc_data[j] = in ci_set_mc_special_registers()
2601 ((table->mc_reg_table_entry[k].mc_data[i] & 0xffff0000) >> 16); in ci_set_mc_special_registers()
2606 "Invalid VramInfo table.", return -EINVAL); in ci_set_mc_special_registers()
2608 table->mc_reg_address[j].s1 = mmMC_PMG_CMD_MRS; in ci_set_mc_special_registers()
2609 table->mc_reg_address[j].s0 = mmMC_SEQ_PMG_CMD_MRS_LP; in ci_set_mc_special_registers()
2610 for (k = 0; k < table->num_entries; k++) { in ci_set_mc_special_registers()
2611 table->mc_reg_table_entry[k].mc_data[j] = in ci_set_mc_special_registers()
2613 (table->mc_reg_table_entry[k].mc_data[i] & 0x0000ffff); in ci_set_mc_special_registers()
2616 table->mc_reg_table_entry[k].mc_data[j] |= 0x100; in ci_set_mc_special_registers()
2622 "Invalid VramInfo table.", return -EINVAL); in ci_set_mc_special_registers()
2623 table->mc_reg_address[j].s1 = mmMC_PMG_AUTO_CMD; in ci_set_mc_special_registers()
2624 table->mc_reg_address[j].s0 = mmMC_PMG_AUTO_CMD; in ci_set_mc_special_registers()
2625 for (k = 0; k < table->num_entries; k++) { in ci_set_mc_special_registers()
2626 table->mc_reg_table_entry[k].mc_data[j] = in ci_set_mc_special_registers()
2627 (table->mc_reg_table_entry[k].mc_data[i] & 0xffff0000) >> 16; in ci_set_mc_special_registers()
2636 table->mc_reg_address[j].s1 = mmMC_PMG_CMD_MRS1; in ci_set_mc_special_registers()
2637 table->mc_reg_address[j].s0 = mmMC_SEQ_PMG_CMD_MRS1_LP; in ci_set_mc_special_registers()
2638 for (k = 0; k < table->num_entries; k++) { in ci_set_mc_special_registers()
2639 table->mc_reg_table_entry[k].mc_data[j] = in ci_set_mc_special_registers()
2641 (table->mc_reg_table_entry[k].mc_data[i] & 0x0000ffff); in ci_set_mc_special_registers()
2652 table->last = j; in ci_set_mc_special_registers()
2657 static int ci_set_valid_flag(struct ci_mc_reg_table *table) in ci_set_valid_flag() argument
2661 for (i = 0; i < table->last; i++) { in ci_set_valid_flag()
2662 for (j = 1; j < table->num_entries; j++) { in ci_set_valid_flag()
2663 if (table->mc_reg_table_entry[j-1].mc_data[i] != in ci_set_valid_flag()
2664 table->mc_reg_table_entry[j].mc_data[i]) { in ci_set_valid_flag()
2665 table->validflag |= (1 << i); in ci_set_valid_flag()
2678 pp_atomctrl_mc_reg_table *table; in ci_initialize_mc_reg_table() local
2682 table = kzalloc(sizeof(pp_atomctrl_mc_reg_table), GFP_KERNEL); in ci_initialize_mc_reg_table()
2684 if (NULL == table) in ci_initialize_mc_reg_table()
2709 result = atomctrl_initialize_mc_reg_table(hwmgr, module_index, table); in ci_initialize_mc_reg_table()
2712 result = ci_copy_vbios_smc_reg_table(table, ni_table); in ci_initialize_mc_reg_table()
2722 kfree(table); in ci_initialize_mc_reg_table()