Lines Matching full:enum

42 enum DISPLAY_GAP {
48 typedef enum DISPLAY_GAP DISPLAY_GAP;
50 enum BACO_STATE {
72 enum PHM_BackEnd_Magic {
193 enum SMU_ASIC_RESET_MODE
248 					enum amd_dpm_forced_level level);
303 …int (*get_clock_by_type)(struct pp_hwmgr *hwmgr, enum amd_pp_clock_type type, struct amd_pp_clocks…
305 			enum amd_pp_clock_type type,
308 			enum amd_pp_clock_type type,
315 	int (*force_clock_level)(struct pp_hwmgr *hwmgr, enum pp_clock_type type, uint32_t mask);
316 	int (*print_clock_levels)(struct pp_hwmgr *hwmgr, enum pp_clock_type type, char *buf);
342 					enum PP_OD_DPM_TABLE_COMMAND type,
345 				      enum PP_OD_DPM_TABLE_COMMAND type,
357 	int (*get_asic_baco_state)(struct pp_hwmgr *hwmgr, enum BACO_STATE *state);
358 	int (*set_asic_baco_state)(struct pp_hwmgr *hwmgr, enum BACO_STATE state);
361 	int (*set_mp1_state)(struct pp_hwmgr *hwmgr, enum pp_mp1_state mp1_state);
362 	int (*asic_reset)(struct pp_hwmgr *hwmgr, enum SMU_ASIC_RESET_MODE mode);
364 	int (*set_df_cstate)(struct pp_hwmgr *hwmgr, enum pp_df_cstate state);
732 enum PP_TABLE_VERSION {
766 	enum amd_dpm_forced_level dpm_level;
767 	enum amd_dpm_forced_level saved_dpm_level;
768 	enum amd_dpm_forced_level request_dpm_level;
778 	enum PP_DAL_POWERLEVEL dal_power_level;
823 				enum amd_pp_task task_id,
824 				enum amd_pm_state_type *user_state);