Lines Matching defs:smu_context

387 struct smu_context  struct
389 	struct amdgpu_device            *adev;
390 	struct amdgpu_irq_src		irq_source;
392 	const struct pptable_funcs	*ppt_funcs;
393 	const struct cmn2asic_msg_mapping	*message_map;
394 	const struct cmn2asic_mapping	*clock_map;
395 	const struct cmn2asic_mapping	*feature_map;
396 	const struct cmn2asic_mapping	*table_map;
397 	const struct cmn2asic_mapping	*pwr_src_map;
398 	const struct cmn2asic_mapping	*workload_map;
399 	struct mutex			mutex;
400 	struct mutex			sensor_lock;
401 	struct mutex			metrics_lock;
402 	struct mutex			message_lock;
403 	uint64_t pool_size;
405 	struct smu_table_context	smu_table;
406 	struct smu_dpm_context		smu_dpm;
407 	struct smu_power_context	smu_power;
408 	struct smu_feature		smu_feature;
409 	struct amd_pp_display_configuration  *display_config;
410 	struct smu_baco_context		smu_baco;
411 	struct smu_temperature_range	thermal_range;
412 	void *od_settings;
414 	struct dentry                   *debugfs_sclk;
417 	struct smu_umd_pstate_table	pstate_table;
418 	uint32_t pstate_sclk;
419 	uint32_t pstate_mclk;
421 	bool od_enabled;
422 	uint32_t current_power_limit;
423 	uint32_t max_power_limit;
426 	uint32_t ppt_offset_bytes;
427 	uint32_t ppt_size_bytes;
428 	uint8_t  *ppt_start_addr;
430 	bool support_power_containment;
431 	bool disable_watermark;
435 	uint32_t watermarks_bitmap;
436 	uint32_t hard_min_uclk_req_from_dal;
437 	bool disable_uclk_switch;
439 	uint32_t workload_mask;
440 	uint32_t workload_prority[WORKLOAD_POLICY_MAX];
441 	uint32_t workload_setting[WORKLOAD_POLICY_MAX];
465 	int (*run_btc)(struct smu_context *smu);  argument