Lines Matching full:pm
114 if (rps == adev->pm.dpm.current_ps) in amdgpu_dpm_print_ps_status()
116 if (rps == adev->pm.dpm.requested_ps) in amdgpu_dpm_print_ps_status()
118 if (rps == adev->pm.dpm.boot_ps) in amdgpu_dpm_print_ps_status()
129 adev->pm.dpm.new_active_crtcs = 0; in amdgpu_dpm_get_active_displays()
130 adev->pm.dpm.new_active_crtc_count = 0; in amdgpu_dpm_get_active_displays()
136 adev->pm.dpm.new_active_crtcs |= (1 << amdgpu_crtc->crtc_id); in amdgpu_dpm_get_active_displays()
137 adev->pm.dpm.new_active_crtc_count++; in amdgpu_dpm_get_active_displays()
269 adev->pm.dpm.platform_caps = le32_to_cpu(power_info->pplib.ulPlatformCaps); in amdgpu_get_platform_caps()
270 adev->pm.dpm.backbias_response_time = le16_to_cpu(power_info->pplib.usBackbiasTime); in amdgpu_get_platform_caps()
271 adev->pm.dpm.voltage_response_time = le16_to_cpu(power_info->pplib.usVoltageTime); in amdgpu_get_platform_caps()
308 adev->pm.dpm.fan.t_hyst = fan_info->fan.ucTHyst; in amdgpu_parse_extended_power_table()
309 adev->pm.dpm.fan.t_min = le16_to_cpu(fan_info->fan.usTMin); in amdgpu_parse_extended_power_table()
310 adev->pm.dpm.fan.t_med = le16_to_cpu(fan_info->fan.usTMed); in amdgpu_parse_extended_power_table()
311 adev->pm.dpm.fan.t_high = le16_to_cpu(fan_info->fan.usTHigh); in amdgpu_parse_extended_power_table()
312 adev->pm.dpm.fan.pwm_min = le16_to_cpu(fan_info->fan.usPWMMin); in amdgpu_parse_extended_power_table()
313 adev->pm.dpm.fan.pwm_med = le16_to_cpu(fan_info->fan.usPWMMed); in amdgpu_parse_extended_power_table()
314 adev->pm.dpm.fan.pwm_high = le16_to_cpu(fan_info->fan.usPWMHigh); in amdgpu_parse_extended_power_table()
316 adev->pm.dpm.fan.t_max = le16_to_cpu(fan_info->fan2.usTMax); in amdgpu_parse_extended_power_table()
318 adev->pm.dpm.fan.t_max = 10900; in amdgpu_parse_extended_power_table()
319 adev->pm.dpm.fan.cycle_delay = 100000; in amdgpu_parse_extended_power_table()
321 adev->pm.dpm.fan.control_mode = fan_info->fan3.ucFanControlMode; in amdgpu_parse_extended_power_table()
322 adev->pm.dpm.fan.default_max_fan_pwm = in amdgpu_parse_extended_power_table()
324 adev->pm.dpm.fan.default_fan_output_sensitivity = 4836; in amdgpu_parse_extended_power_table()
325 adev->pm.dpm.fan.fan_output_sensitivity = in amdgpu_parse_extended_power_table()
328 adev->pm.dpm.fan.ucode_fan_control = true; in amdgpu_parse_extended_power_table()
339 ret = amdgpu_parse_clk_voltage_dep_table(&adev->pm.dpm.dyn_state.vddc_dependency_on_sclk, in amdgpu_parse_extended_power_table()
350 ret = amdgpu_parse_clk_voltage_dep_table(&adev->pm.dpm.dyn_state.vddci_dependency_on_mclk, in amdgpu_parse_extended_power_table()
361 ret = amdgpu_parse_clk_voltage_dep_table(&adev->pm.dpm.dyn_state.vddc_dependency_on_mclk, in amdgpu_parse_extended_power_table()
372 ret = amdgpu_parse_clk_voltage_dep_table(&adev->pm.dpm.dyn_state.mvdd_dependency_on_mclk, in amdgpu_parse_extended_power_table()
385 adev->pm.dpm.dyn_state.max_clock_voltage_on_dc.sclk = in amdgpu_parse_extended_power_table()
388 adev->pm.dpm.dyn_state.max_clock_voltage_on_dc.mclk = in amdgpu_parse_extended_power_table()
391 adev->pm.dpm.dyn_state.max_clock_voltage_on_dc.vddc = in amdgpu_parse_extended_power_table()
393 adev->pm.dpm.dyn_state.max_clock_voltage_on_dc.vddci = in amdgpu_parse_extended_power_table()
404 adev->pm.dpm.dyn_state.phase_shedding_limits_table.entries = in amdgpu_parse_extended_power_table()
408 if (!adev->pm.dpm.dyn_state.phase_shedding_limits_table.entries) { in amdgpu_parse_extended_power_table()
415 adev->pm.dpm.dyn_state.phase_shedding_limits_table.entries[i].sclk = in amdgpu_parse_extended_power_table()
417 adev->pm.dpm.dyn_state.phase_shedding_limits_table.entries[i].mclk = in amdgpu_parse_extended_power_table()
419 adev->pm.dpm.dyn_state.phase_shedding_limits_table.entries[i].voltage = in amdgpu_parse_extended_power_table()
424 adev->pm.dpm.dyn_state.phase_shedding_limits_table.count = in amdgpu_parse_extended_power_table()
432 adev->pm.dpm.tdp_limit = le32_to_cpu(power_info->pplib5.ulTDPLimit); in amdgpu_parse_extended_power_table()
433 adev->pm.dpm.near_tdp_limit = le32_to_cpu(power_info->pplib5.ulNearTDPLimit); in amdgpu_parse_extended_power_table()
434 adev->pm.dpm.near_tdp_limit_adjusted = adev->pm.dpm.near_tdp_limit; in amdgpu_parse_extended_power_table()
435 adev->pm.dpm.tdp_od_limit = le16_to_cpu(power_info->pplib5.usTDPODLimit); in amdgpu_parse_extended_power_table()
436 if (adev->pm.dpm.tdp_od_limit) in amdgpu_parse_extended_power_table()
437 adev->pm.dpm.power_control = true; in amdgpu_parse_extended_power_table()
439 adev->pm.dpm.power_control = false; in amdgpu_parse_extended_power_table()
440 adev->pm.dpm.tdp_adjustment = 0; in amdgpu_parse_extended_power_table()
441 adev->pm.dpm.sq_ramping_threshold = le32_to_cpu(power_info->pplib5.ulSQRampingThreshold); in amdgpu_parse_extended_power_table()
442 adev->pm.dpm.cac_leakage = le32_to_cpu(power_info->pplib5.ulCACLeakage); in amdgpu_parse_extended_power_table()
443 adev->pm.dpm.load_line_slope = le16_to_cpu(power_info->pplib5.usLoadLineSlope); in amdgpu_parse_extended_power_table()
451 adev->pm.dpm.dyn_state.cac_leakage_table.entries = kzalloc(size, GFP_KERNEL); in amdgpu_parse_extended_power_table()
452 if (!adev->pm.dpm.dyn_state.cac_leakage_table.entries) { in amdgpu_parse_extended_power_table()
458 if (adev->pm.dpm.platform_caps & ATOM_PP_PLATFORM_CAP_EVV) { in amdgpu_parse_extended_power_table()
459 adev->pm.dpm.dyn_state.cac_leakage_table.entries[i].vddc1 = in amdgpu_parse_extended_power_table()
461 adev->pm.dpm.dyn_state.cac_leakage_table.entries[i].vddc2 = in amdgpu_parse_extended_power_table()
463 adev->pm.dpm.dyn_state.cac_leakage_table.entries[i].vddc3 = in amdgpu_parse_extended_power_table()
466 adev->pm.dpm.dyn_state.cac_leakage_table.entries[i].vddc = in amdgpu_parse_extended_power_table()
468 adev->pm.dpm.dyn_state.cac_leakage_table.entries[i].leakage = in amdgpu_parse_extended_power_table()
474 adev->pm.dpm.dyn_state.cac_leakage_table.count = cac_table->ucNumEntries; in amdgpu_parse_extended_power_table()
505 adev->pm.dpm.dyn_state.vce_clock_voltage_dependency_table.entries = in amdgpu_parse_extended_power_table()
507 if (!adev->pm.dpm.dyn_state.vce_clock_voltage_dependency_table.entries) { in amdgpu_parse_extended_power_table()
511 adev->pm.dpm.dyn_state.vce_clock_voltage_dependency_table.count = in amdgpu_parse_extended_power_table()
519 adev->pm.dpm.dyn_state.vce_clock_voltage_dependency_table.entries[i].evclk = in amdgpu_parse_extended_power_table()
521 adev->pm.dpm.dyn_state.vce_clock_voltage_dependency_table.entries[i].ecclk = in amdgpu_parse_extended_power_table()
523 adev->pm.dpm.dyn_state.vce_clock_voltage_dependency_table.entries[i].v = in amdgpu_parse_extended_power_table()
528 adev->pm.dpm.num_of_vce_states = in amdgpu_parse_extended_power_table()
531 for (i = 0; i < adev->pm.dpm.num_of_vce_states; i++) { in amdgpu_parse_extended_power_table()
535 adev->pm.dpm.vce_states[i].evclk = in amdgpu_parse_extended_power_table()
537 adev->pm.dpm.vce_states[i].ecclk = in amdgpu_parse_extended_power_table()
539 adev->pm.dpm.vce_states[i].clk_idx = in amdgpu_parse_extended_power_table()
541 adev->pm.dpm.vce_states[i].pstate = in amdgpu_parse_extended_power_table()
560 adev->pm.dpm.dyn_state.uvd_clock_voltage_dependency_table.entries = in amdgpu_parse_extended_power_table()
562 if (!adev->pm.dpm.dyn_state.uvd_clock_voltage_dependency_table.entries) { in amdgpu_parse_extended_power_table()
566 adev->pm.dpm.dyn_state.uvd_clock_voltage_dependency_table.count = in amdgpu_parse_extended_power_table()
573 adev->pm.dpm.dyn_state.uvd_clock_voltage_dependency_table.entries[i].vclk = in amdgpu_parse_extended_power_table()
575 adev->pm.dpm.dyn_state.uvd_clock_voltage_dependency_table.entries[i].dclk = in amdgpu_parse_extended_power_table()
577 adev->pm.dpm.dyn_state.uvd_clock_voltage_dependency_table.entries[i].v = in amdgpu_parse_extended_power_table()
592 adev->pm.dpm.dyn_state.samu_clock_voltage_dependency_table.entries = in amdgpu_parse_extended_power_table()
594 if (!adev->pm.dpm.dyn_state.samu_clock_voltage_dependency_table.entries) { in amdgpu_parse_extended_power_table()
598 adev->pm.dpm.dyn_state.samu_clock_voltage_dependency_table.count = in amdgpu_parse_extended_power_table()
602 adev->pm.dpm.dyn_state.samu_clock_voltage_dependency_table.entries[i].clk = in amdgpu_parse_extended_power_table()
604 adev->pm.dpm.dyn_state.samu_clock_voltage_dependency_table.entries[i].v = in amdgpu_parse_extended_power_table()
615 adev->pm.dpm.dyn_state.ppm_table = in amdgpu_parse_extended_power_table()
617 if (!adev->pm.dpm.dyn_state.ppm_table) { in amdgpu_parse_extended_power_table()
621 adev->pm.dpm.dyn_state.ppm_table->ppm_design = ppm->ucPpmDesign; in amdgpu_parse_extended_power_table()
622 adev->pm.dpm.dyn_state.ppm_table->cpu_core_number = in amdgpu_parse_extended_power_table()
624 adev->pm.dpm.dyn_state.ppm_table->platform_tdp = in amdgpu_parse_extended_power_table()
626 adev->pm.dpm.dyn_state.ppm_table->small_ac_platform_tdp = in amdgpu_parse_extended_power_table()
628 adev->pm.dpm.dyn_state.ppm_table->platform_tdc = in amdgpu_parse_extended_power_table()
630 adev->pm.dpm.dyn_state.ppm_table->small_ac_platform_tdc = in amdgpu_parse_extended_power_table()
632 adev->pm.dpm.dyn_state.ppm_table->apu_tdp = in amdgpu_parse_extended_power_table()
634 adev->pm.dpm.dyn_state.ppm_table->dgpu_tdp = in amdgpu_parse_extended_power_table()
636 adev->pm.dpm.dyn_state.ppm_table->dgpu_ulv_power = in amdgpu_parse_extended_power_table()
638 adev->pm.dpm.dyn_state.ppm_table->tj_max = in amdgpu_parse_extended_power_table()
650 adev->pm.dpm.dyn_state.acp_clock_voltage_dependency_table.entries = in amdgpu_parse_extended_power_table()
652 if (!adev->pm.dpm.dyn_state.acp_clock_voltage_dependency_table.entries) { in amdgpu_parse_extended_power_table()
656 adev->pm.dpm.dyn_state.acp_clock_voltage_dependency_table.count = in amdgpu_parse_extended_power_table()
660 adev->pm.dpm.dyn_state.acp_clock_voltage_dependency_table.entries[i].clk = in amdgpu_parse_extended_power_table()
662 adev->pm.dpm.dyn_state.acp_clock_voltage_dependency_table.entries[i].v = in amdgpu_parse_extended_power_table()
673 adev->pm.dpm.dyn_state.cac_tdp_table = in amdgpu_parse_extended_power_table()
675 if (!adev->pm.dpm.dyn_state.cac_tdp_table) { in amdgpu_parse_extended_power_table()
683 adev->pm.dpm.dyn_state.cac_tdp_table->maximum_power_delivery_limit = in amdgpu_parse_extended_power_table()
690 adev->pm.dpm.dyn_state.cac_tdp_table->maximum_power_delivery_limit = 255; in amdgpu_parse_extended_power_table()
693 adev->pm.dpm.dyn_state.cac_tdp_table->tdp = le16_to_cpu(pt->usTDP); in amdgpu_parse_extended_power_table()
694 adev->pm.dpm.dyn_state.cac_tdp_table->configurable_tdp = in amdgpu_parse_extended_power_table()
696 adev->pm.dpm.dyn_state.cac_tdp_table->tdc = le16_to_cpu(pt->usTDC); in amdgpu_parse_extended_power_table()
697 adev->pm.dpm.dyn_state.cac_tdp_table->battery_power_limit = in amdgpu_parse_extended_power_table()
699 adev->pm.dpm.dyn_state.cac_tdp_table->small_power_limit = in amdgpu_parse_extended_power_table()
701 adev->pm.dpm.dyn_state.cac_tdp_table->low_cac_leakage = in amdgpu_parse_extended_power_table()
703 adev->pm.dpm.dyn_state.cac_tdp_table->high_cac_leakage = in amdgpu_parse_extended_power_table()
712 &adev->pm.dpm.dyn_state.vddgfx_dependency_on_sclk, in amdgpu_parse_extended_power_table()
715 kfree(adev->pm.dpm.dyn_state.vddgfx_dependency_on_sclk.entries); in amdgpu_parse_extended_power_table()
726 struct amdgpu_dpm_dynamic_state *dyn_state = &adev->pm.dpm.dyn_state; in amdgpu_free_extended_power_table()
786 adev->pm.no_fan = true; in amdgpu_add_thermal_controller()
787 adev->pm.fan_pulses_per_revolution = in amdgpu_add_thermal_controller()
789 if (adev->pm.fan_pulses_per_revolution) { in amdgpu_add_thermal_controller()
790 adev->pm.fan_min_rpm = controller->ucFanMinRPM; in amdgpu_add_thermal_controller()
791 adev->pm.fan_max_rpm = controller->ucFanMaxRPM; in amdgpu_add_thermal_controller()
797 adev->pm.int_thermal_type = THERMAL_TYPE_RV6XX; in amdgpu_add_thermal_controller()
802 adev->pm.int_thermal_type = THERMAL_TYPE_RV770; in amdgpu_add_thermal_controller()
807 adev->pm.int_thermal_type = THERMAL_TYPE_EVERGREEN; in amdgpu_add_thermal_controller()
812 adev->pm.int_thermal_type = THERMAL_TYPE_SUMO; in amdgpu_add_thermal_controller()
817 adev->pm.int_thermal_type = THERMAL_TYPE_NI; in amdgpu_add_thermal_controller()
822 adev->pm.int_thermal_type = THERMAL_TYPE_SI; in amdgpu_add_thermal_controller()
827 adev->pm.int_thermal_type = THERMAL_TYPE_CI; in amdgpu_add_thermal_controller()
832 adev->pm.int_thermal_type = THERMAL_TYPE_KV; in amdgpu_add_thermal_controller()
837 adev->pm.int_thermal_type = THERMAL_TYPE_EXTERNAL_GPIO; in amdgpu_add_thermal_controller()
843 adev->pm.int_thermal_type = THERMAL_TYPE_ADT7473_WITH_INTERNAL; in amdgpu_add_thermal_controller()
849 adev->pm.int_thermal_type = THERMAL_TYPE_EMC2103_WITH_INTERNAL; in amdgpu_add_thermal_controller()
856 adev->pm.int_thermal_type = THERMAL_TYPE_EXTERNAL; in amdgpu_add_thermal_controller()
858 adev->pm.i2c_bus = amdgpu_i2c_lookup(adev, &i2c_bus); in amdgpu_add_thermal_controller()
859 if (adev->pm.i2c_bus) { in amdgpu_add_thermal_controller()
864 i2c_new_client_device(&adev->pm.i2c_bus->adapter, &info); in amdgpu_add_thermal_controller()
906 if (idx < adev->pm.dpm.num_of_vce_states) in amdgpu_get_vce_clock_state()
907 return &adev->pm.dpm.vce_states[idx]; in amdgpu_get_vce_clock_state()
961 * Here adev->pm.mutex lock protection is enforced on in amdgpu_dpm_set_powergating_by_smu()
984 mutex_lock(&adev->pm.mutex); in amdgpu_dpm_set_powergating_by_smu()
987 mutex_unlock(&adev->pm.mutex); in amdgpu_dpm_set_powergating_by_smu()
1271 if (adev->pm.dpm_enabled) { in amdgpu_pm_acpi_event_handler()
1272 mutex_lock(&adev->pm.mutex); in amdgpu_pm_acpi_event_handler()
1274 adev->pm.ac_power = true; in amdgpu_pm_acpi_event_handler()
1276 adev->pm.ac_power = false; in amdgpu_pm_acpi_event_handler()
1279 amdgpu_dpm_enable_bapm(adev, adev->pm.ac_power); in amdgpu_pm_acpi_event_handler()
1280 mutex_unlock(&adev->pm.mutex); in amdgpu_pm_acpi_event_handler()
1312 pm.dpm.thermal.work); in amdgpu_dpm_thermal_work_handler()
1317 if (!adev->pm.dpm_enabled) in amdgpu_dpm_thermal_work_handler()
1322 if (temp < adev->pm.dpm.thermal.min_temp) in amdgpu_dpm_thermal_work_handler()
1324 dpm_state = adev->pm.dpm.user_state; in amdgpu_dpm_thermal_work_handler()
1326 if (adev->pm.dpm.thermal.high_to_low) in amdgpu_dpm_thermal_work_handler()
1328 dpm_state = adev->pm.dpm.user_state; in amdgpu_dpm_thermal_work_handler()
1330 mutex_lock(&adev->pm.mutex); in amdgpu_dpm_thermal_work_handler()
1332 adev->pm.dpm.thermal_active = true; in amdgpu_dpm_thermal_work_handler()
1334 adev->pm.dpm.thermal_active = false; in amdgpu_dpm_thermal_work_handler()
1335 adev->pm.dpm.state = dpm_state; in amdgpu_dpm_thermal_work_handler()
1336 mutex_unlock(&adev->pm.mutex); in amdgpu_dpm_thermal_work_handler()
1347 bool single_display = (adev->pm.dpm.new_active_crtc_count < 2) ? in amdgpu_dpm_pick_power_state()
1367 for (i = 0; i < adev->pm.dpm.num_ps; i++) { in amdgpu_dpm_pick_power_state()
1368 ps = &adev->pm.dpm.ps[i]; in amdgpu_dpm_pick_power_state()
1401 if (adev->pm.dpm.uvd_ps) in amdgpu_dpm_pick_power_state()
1402 return adev->pm.dpm.uvd_ps; in amdgpu_dpm_pick_power_state()
1422 return adev->pm.dpm.boot_ps; in amdgpu_dpm_pick_power_state()
1451 if (adev->pm.dpm.uvd_ps) { in amdgpu_dpm_pick_power_state()
1452 return adev->pm.dpm.uvd_ps; in amdgpu_dpm_pick_power_state()
1483 if (!adev->pm.dpm_enabled) in amdgpu_dpm_change_power_state_locked()
1486 if (adev->pm.dpm.user_state != adev->pm.dpm.state) { in amdgpu_dpm_change_power_state_locked()
1488 if ((!adev->pm.dpm.thermal_active) && in amdgpu_dpm_change_power_state_locked()
1489 (!adev->pm.dpm.uvd_active)) in amdgpu_dpm_change_power_state_locked()
1490 adev->pm.dpm.state = adev->pm.dpm.user_state; in amdgpu_dpm_change_power_state_locked()
1492 dpm_state = adev->pm.dpm.state; in amdgpu_dpm_change_power_state_locked()
1496 adev->pm.dpm.requested_ps = ps; in amdgpu_dpm_change_power_state_locked()
1502 amdgpu_dpm_print_power_state(adev, adev->pm.dpm.current_ps); in amdgpu_dpm_change_power_state_locked()
1504 amdgpu_dpm_print_power_state(adev, adev->pm.dpm.requested_ps); in amdgpu_dpm_change_power_state_locked()
1508 ps->vce_active = adev->pm.dpm.vce_active; in amdgpu_dpm_change_power_state_locked()
1517 …if (0 != amdgpu_dpm_check_state_equal(adev, adev->pm.dpm.current_ps, adev->pm.dpm.requested_ps, &e… in amdgpu_dpm_change_power_state_locked()
1527 adev->pm.dpm.current_active_crtcs = adev->pm.dpm.new_active_crtcs; in amdgpu_dpm_change_power_state_locked()
1528 adev->pm.dpm.current_active_crtc_count = adev->pm.dpm.new_active_crtc_count; in amdgpu_dpm_change_power_state_locked()
1531 if (adev->pm.dpm.thermal_active) { in amdgpu_dpm_change_power_state_locked()
1532 enum amd_dpm_forced_level level = adev->pm.dpm.forced_level; in amdgpu_dpm_change_power_state_locked()
1536 adev->pm.dpm.forced_level = level; in amdgpu_dpm_change_power_state_locked()
1539 amdgpu_dpm_force_performance_level(adev, adev->pm.dpm.forced_level); in amdgpu_dpm_change_power_state_locked()
1548 if (!adev->pm.dpm_enabled) in amdgpu_pm_compute_clocks()
1569 mutex_lock(&adev->pm.mutex); in amdgpu_pm_compute_clocks()
1571 adev->pm.pm_display_cfg.num_display = adev->pm.dpm.new_active_crtc_count; in amdgpu_pm_compute_clocks()
1572 adev->pm.pm_display_cfg.vrefresh = amdgpu_dpm_get_vrefresh(adev); in amdgpu_pm_compute_clocks()
1573 adev->pm.pm_display_cfg.min_vblank_time = amdgpu_dpm_get_vblank_time(adev); in amdgpu_pm_compute_clocks()
1575 if (adev->pm.pm_display_cfg.vrefresh > 120) in amdgpu_pm_compute_clocks()
1576 adev->pm.pm_display_cfg.min_vblank_time = 0; in amdgpu_pm_compute_clocks()
1580 &adev->pm.pm_display_cfg); in amdgpu_pm_compute_clocks()
1581 mutex_unlock(&adev->pm.mutex); in amdgpu_pm_compute_clocks()
1585 mutex_lock(&adev->pm.mutex); in amdgpu_pm_compute_clocks()
1588 mutex_unlock(&adev->pm.mutex); in amdgpu_pm_compute_clocks()
1598 mutex_lock(&adev->pm.mutex); in amdgpu_dpm_enable_uvd()
1600 adev->pm.dpm.uvd_active = true; in amdgpu_dpm_enable_uvd()
1601 adev->pm.dpm.state = POWER_STATE_TYPE_INTERNAL_UVD; in amdgpu_dpm_enable_uvd()
1603 adev->pm.dpm.uvd_active = false; in amdgpu_dpm_enable_uvd()
1605 mutex_unlock(&adev->pm.mutex); in amdgpu_dpm_enable_uvd()
1633 mutex_lock(&adev->pm.mutex); in amdgpu_dpm_enable_vce()
1635 adev->pm.dpm.vce_active = true; in amdgpu_dpm_enable_vce()
1637 adev->pm.dpm.vce_level = AMD_VCE_LEVEL_AC_ALL; in amdgpu_dpm_enable_vce()
1639 adev->pm.dpm.vce_active = false; in amdgpu_dpm_enable_vce()
1641 mutex_unlock(&adev->pm.mutex); in amdgpu_dpm_enable_vce()
1659 for (i = 0; i < adev->pm.dpm.num_ps; i++) in amdgpu_pm_print_power_states()
1660 amdgpu_dpm_print_power_state(adev, &adev->pm.dpm.ps[i]); in amdgpu_pm_print_power_states()
1684 *smu_version = adev->pm.fw_version; in amdgpu_pm_load_smu_firmware()