Lines Matching +full:adt7473 +full:- +full:d
114 if (rps == adev->pm.dpm.current_ps) in amdgpu_dpm_print_ps_status()
116 if (rps == adev->pm.dpm.requested_ps) in amdgpu_dpm_print_ps_status()
118 if (rps == adev->pm.dpm.boot_ps) in amdgpu_dpm_print_ps_status()
129 adev->pm.dpm.new_active_crtcs = 0; in amdgpu_dpm_get_active_displays()
130 adev->pm.dpm.new_active_crtc_count = 0; in amdgpu_dpm_get_active_displays()
131 if (adev->mode_info.num_crtc && adev->mode_info.mode_config_initialized) { in amdgpu_dpm_get_active_displays()
133 &ddev->mode_config.crtc_list, head) { in amdgpu_dpm_get_active_displays()
135 if (amdgpu_crtc->enabled) { in amdgpu_dpm_get_active_displays()
136 adev->pm.dpm.new_active_crtcs |= (1 << amdgpu_crtc->crtc_id); in amdgpu_dpm_get_active_displays()
137 adev->pm.dpm.new_active_crtc_count++; in amdgpu_dpm_get_active_displays()
152 if (adev->mode_info.num_crtc && adev->mode_info.mode_config_initialized) { in amdgpu_dpm_get_vblank_time()
153 list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) { in amdgpu_dpm_get_vblank_time()
155 if (crtc->enabled && amdgpu_crtc->enabled && amdgpu_crtc->hw_mode.clock) { in amdgpu_dpm_get_vblank_time()
157 amdgpu_crtc->hw_mode.crtc_htotal * in amdgpu_dpm_get_vblank_time()
158 (amdgpu_crtc->hw_mode.crtc_vblank_end - in amdgpu_dpm_get_vblank_time()
159 amdgpu_crtc->hw_mode.crtc_vdisplay + in amdgpu_dpm_get_vblank_time()
160 (amdgpu_crtc->v_border * 2)); in amdgpu_dpm_get_vblank_time()
162 vblank_time_us = vblank_in_pixels * 1000 / amdgpu_crtc->hw_mode.clock; in amdgpu_dpm_get_vblank_time()
178 if (adev->mode_info.num_crtc && adev->mode_info.mode_config_initialized) { in amdgpu_dpm_get_vrefresh()
179 list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) { in amdgpu_dpm_get_vrefresh()
181 if (crtc->enabled && amdgpu_crtc->enabled && amdgpu_crtc->hw_mode.clock) { in amdgpu_dpm_get_vrefresh()
182 vrefresh = drm_mode_vrefresh(&amdgpu_crtc->hw_mode); in amdgpu_dpm_get_vrefresh()
234 u32 size = atom_table->ucNumEntries * in amdgpu_parse_clk_voltage_dep_table()
239 amdgpu_table->entries = kzalloc(size, GFP_KERNEL); in amdgpu_parse_clk_voltage_dep_table()
240 if (!amdgpu_table->entries) in amdgpu_parse_clk_voltage_dep_table()
241 return -ENOMEM; in amdgpu_parse_clk_voltage_dep_table()
243 entry = &atom_table->entries[0]; in amdgpu_parse_clk_voltage_dep_table()
244 for (i = 0; i < atom_table->ucNumEntries; i++) { in amdgpu_parse_clk_voltage_dep_table()
245 amdgpu_table->entries[i].clk = le16_to_cpu(entry->usClockLow) | in amdgpu_parse_clk_voltage_dep_table()
246 (entry->ucClockHigh << 16); in amdgpu_parse_clk_voltage_dep_table()
247 amdgpu_table->entries[i].v = le16_to_cpu(entry->usVoltage); in amdgpu_parse_clk_voltage_dep_table()
251 amdgpu_table->count = atom_table->ucNumEntries; in amdgpu_parse_clk_voltage_dep_table()
258 struct amdgpu_mode_info *mode_info = &adev->mode_info; in amdgpu_get_platform_caps()
264 if (!amdgpu_atom_parse_data_header(mode_info->atom_context, index, NULL, in amdgpu_get_platform_caps()
266 return -EINVAL; in amdgpu_get_platform_caps()
267 power_info = (union power_info *)(mode_info->atom_context->bios + data_offset); in amdgpu_get_platform_caps()
269 adev->pm.dpm.platform_caps = le32_to_cpu(power_info->pplib.ulPlatformCaps); in amdgpu_get_platform_caps()
270 adev->pm.dpm.backbias_response_time = le16_to_cpu(power_info->pplib.usBackbiasTime); in amdgpu_get_platform_caps()
271 adev->pm.dpm.voltage_response_time = le16_to_cpu(power_info->pplib.usVoltageTime); in amdgpu_get_platform_caps()
288 struct amdgpu_mode_info *mode_info = &adev->mode_info; in amdgpu_parse_extended_power_table()
297 if (!amdgpu_atom_parse_data_header(mode_info->atom_context, index, NULL, in amdgpu_parse_extended_power_table()
299 return -EINVAL; in amdgpu_parse_extended_power_table()
300 power_info = (union power_info *)(mode_info->atom_context->bios + data_offset); in amdgpu_parse_extended_power_table()
303 if (le16_to_cpu(power_info->pplib.usTableSize) >= in amdgpu_parse_extended_power_table()
305 if (power_info->pplib3.usFanTableOffset) { in amdgpu_parse_extended_power_table()
306 fan_info = (union fan_info *)(mode_info->atom_context->bios + data_offset + in amdgpu_parse_extended_power_table()
307 le16_to_cpu(power_info->pplib3.usFanTableOffset)); in amdgpu_parse_extended_power_table()
308 adev->pm.dpm.fan.t_hyst = fan_info->fan.ucTHyst; in amdgpu_parse_extended_power_table()
309 adev->pm.dpm.fan.t_min = le16_to_cpu(fan_info->fan.usTMin); in amdgpu_parse_extended_power_table()
310 adev->pm.dpm.fan.t_med = le16_to_cpu(fan_info->fan.usTMed); in amdgpu_parse_extended_power_table()
311 adev->pm.dpm.fan.t_high = le16_to_cpu(fan_info->fan.usTHigh); in amdgpu_parse_extended_power_table()
312 adev->pm.dpm.fan.pwm_min = le16_to_cpu(fan_info->fan.usPWMMin); in amdgpu_parse_extended_power_table()
313 adev->pm.dpm.fan.pwm_med = le16_to_cpu(fan_info->fan.usPWMMed); in amdgpu_parse_extended_power_table()
314 adev->pm.dpm.fan.pwm_high = le16_to_cpu(fan_info->fan.usPWMHigh); in amdgpu_parse_extended_power_table()
315 if (fan_info->fan.ucFanTableFormat >= 2) in amdgpu_parse_extended_power_table()
316 adev->pm.dpm.fan.t_max = le16_to_cpu(fan_info->fan2.usTMax); in amdgpu_parse_extended_power_table()
318 adev->pm.dpm.fan.t_max = 10900; in amdgpu_parse_extended_power_table()
319 adev->pm.dpm.fan.cycle_delay = 100000; in amdgpu_parse_extended_power_table()
320 if (fan_info->fan.ucFanTableFormat >= 3) { in amdgpu_parse_extended_power_table()
321 adev->pm.dpm.fan.control_mode = fan_info->fan3.ucFanControlMode; in amdgpu_parse_extended_power_table()
322 adev->pm.dpm.fan.default_max_fan_pwm = in amdgpu_parse_extended_power_table()
323 le16_to_cpu(fan_info->fan3.usFanPWMMax); in amdgpu_parse_extended_power_table()
324 adev->pm.dpm.fan.default_fan_output_sensitivity = 4836; in amdgpu_parse_extended_power_table()
325 adev->pm.dpm.fan.fan_output_sensitivity = in amdgpu_parse_extended_power_table()
326 le16_to_cpu(fan_info->fan3.usFanOutputSensitivity); in amdgpu_parse_extended_power_table()
328 adev->pm.dpm.fan.ucode_fan_control = true; in amdgpu_parse_extended_power_table()
333 if (le16_to_cpu(power_info->pplib.usTableSize) >= in amdgpu_parse_extended_power_table()
335 if (power_info->pplib4.usVddcDependencyOnSCLKOffset) { in amdgpu_parse_extended_power_table()
337 (mode_info->atom_context->bios + data_offset + in amdgpu_parse_extended_power_table()
338 le16_to_cpu(power_info->pplib4.usVddcDependencyOnSCLKOffset)); in amdgpu_parse_extended_power_table()
339 ret = amdgpu_parse_clk_voltage_dep_table(&adev->pm.dpm.dyn_state.vddc_dependency_on_sclk, in amdgpu_parse_extended_power_table()
346 if (power_info->pplib4.usVddciDependencyOnMCLKOffset) { in amdgpu_parse_extended_power_table()
348 (mode_info->atom_context->bios + data_offset + in amdgpu_parse_extended_power_table()
349 le16_to_cpu(power_info->pplib4.usVddciDependencyOnMCLKOffset)); in amdgpu_parse_extended_power_table()
350 ret = amdgpu_parse_clk_voltage_dep_table(&adev->pm.dpm.dyn_state.vddci_dependency_on_mclk, in amdgpu_parse_extended_power_table()
357 if (power_info->pplib4.usVddcDependencyOnMCLKOffset) { in amdgpu_parse_extended_power_table()
359 (mode_info->atom_context->bios + data_offset + in amdgpu_parse_extended_power_table()
360 le16_to_cpu(power_info->pplib4.usVddcDependencyOnMCLKOffset)); in amdgpu_parse_extended_power_table()
361 ret = amdgpu_parse_clk_voltage_dep_table(&adev->pm.dpm.dyn_state.vddc_dependency_on_mclk, in amdgpu_parse_extended_power_table()
368 if (power_info->pplib4.usMvddDependencyOnMCLKOffset) { in amdgpu_parse_extended_power_table()
370 (mode_info->atom_context->bios + data_offset + in amdgpu_parse_extended_power_table()
371 le16_to_cpu(power_info->pplib4.usMvddDependencyOnMCLKOffset)); in amdgpu_parse_extended_power_table()
372 ret = amdgpu_parse_clk_voltage_dep_table(&adev->pm.dpm.dyn_state.mvdd_dependency_on_mclk, in amdgpu_parse_extended_power_table()
379 if (power_info->pplib4.usMaxClockVoltageOnDCOffset) { in amdgpu_parse_extended_power_table()
382 (mode_info->atom_context->bios + data_offset + in amdgpu_parse_extended_power_table()
383 le16_to_cpu(power_info->pplib4.usMaxClockVoltageOnDCOffset)); in amdgpu_parse_extended_power_table()
384 if (clk_v->ucNumEntries) { in amdgpu_parse_extended_power_table()
385 adev->pm.dpm.dyn_state.max_clock_voltage_on_dc.sclk = in amdgpu_parse_extended_power_table()
386 le16_to_cpu(clk_v->entries[0].usSclkLow) | in amdgpu_parse_extended_power_table()
387 (clk_v->entries[0].ucSclkHigh << 16); in amdgpu_parse_extended_power_table()
388 adev->pm.dpm.dyn_state.max_clock_voltage_on_dc.mclk = in amdgpu_parse_extended_power_table()
389 le16_to_cpu(clk_v->entries[0].usMclkLow) | in amdgpu_parse_extended_power_table()
390 (clk_v->entries[0].ucMclkHigh << 16); in amdgpu_parse_extended_power_table()
391 adev->pm.dpm.dyn_state.max_clock_voltage_on_dc.vddc = in amdgpu_parse_extended_power_table()
392 le16_to_cpu(clk_v->entries[0].usVddc); in amdgpu_parse_extended_power_table()
393 adev->pm.dpm.dyn_state.max_clock_voltage_on_dc.vddci = in amdgpu_parse_extended_power_table()
394 le16_to_cpu(clk_v->entries[0].usVddci); in amdgpu_parse_extended_power_table()
397 if (power_info->pplib4.usVddcPhaseShedLimitsTableOffset) { in amdgpu_parse_extended_power_table()
400 (mode_info->atom_context->bios + data_offset + in amdgpu_parse_extended_power_table()
401 le16_to_cpu(power_info->pplib4.usVddcPhaseShedLimitsTableOffset)); in amdgpu_parse_extended_power_table()
404 adev->pm.dpm.dyn_state.phase_shedding_limits_table.entries = in amdgpu_parse_extended_power_table()
405 kcalloc(psl->ucNumEntries, in amdgpu_parse_extended_power_table()
408 if (!adev->pm.dpm.dyn_state.phase_shedding_limits_table.entries) { in amdgpu_parse_extended_power_table()
410 return -ENOMEM; in amdgpu_parse_extended_power_table()
413 entry = &psl->entries[0]; in amdgpu_parse_extended_power_table()
414 for (i = 0; i < psl->ucNumEntries; i++) { in amdgpu_parse_extended_power_table()
415 adev->pm.dpm.dyn_state.phase_shedding_limits_table.entries[i].sclk = in amdgpu_parse_extended_power_table()
416 le16_to_cpu(entry->usSclkLow) | (entry->ucSclkHigh << 16); in amdgpu_parse_extended_power_table()
417 adev->pm.dpm.dyn_state.phase_shedding_limits_table.entries[i].mclk = in amdgpu_parse_extended_power_table()
418 le16_to_cpu(entry->usMclkLow) | (entry->ucMclkHigh << 16); in amdgpu_parse_extended_power_table()
419 adev->pm.dpm.dyn_state.phase_shedding_limits_table.entries[i].voltage = in amdgpu_parse_extended_power_table()
420 le16_to_cpu(entry->usVoltage); in amdgpu_parse_extended_power_table()
424 adev->pm.dpm.dyn_state.phase_shedding_limits_table.count = in amdgpu_parse_extended_power_table()
425 psl->ucNumEntries; in amdgpu_parse_extended_power_table()
430 if (le16_to_cpu(power_info->pplib.usTableSize) >= in amdgpu_parse_extended_power_table()
432 adev->pm.dpm.tdp_limit = le32_to_cpu(power_info->pplib5.ulTDPLimit); in amdgpu_parse_extended_power_table()
433 adev->pm.dpm.near_tdp_limit = le32_to_cpu(power_info->pplib5.ulNearTDPLimit); in amdgpu_parse_extended_power_table()
434 adev->pm.dpm.near_tdp_limit_adjusted = adev->pm.dpm.near_tdp_limit; in amdgpu_parse_extended_power_table()
435 adev->pm.dpm.tdp_od_limit = le16_to_cpu(power_info->pplib5.usTDPODLimit); in amdgpu_parse_extended_power_table()
436 if (adev->pm.dpm.tdp_od_limit) in amdgpu_parse_extended_power_table()
437 adev->pm.dpm.power_control = true; in amdgpu_parse_extended_power_table()
439 adev->pm.dpm.power_control = false; in amdgpu_parse_extended_power_table()
440 adev->pm.dpm.tdp_adjustment = 0; in amdgpu_parse_extended_power_table()
441 adev->pm.dpm.sq_ramping_threshold = le32_to_cpu(power_info->pplib5.ulSQRampingThreshold); in amdgpu_parse_extended_power_table()
442 adev->pm.dpm.cac_leakage = le32_to_cpu(power_info->pplib5.ulCACLeakage); in amdgpu_parse_extended_power_table()
443 adev->pm.dpm.load_line_slope = le16_to_cpu(power_info->pplib5.usLoadLineSlope); in amdgpu_parse_extended_power_table()
444 if (power_info->pplib5.usCACLeakageTableOffset) { in amdgpu_parse_extended_power_table()
447 (mode_info->atom_context->bios + data_offset + in amdgpu_parse_extended_power_table()
448 le16_to_cpu(power_info->pplib5.usCACLeakageTableOffset)); in amdgpu_parse_extended_power_table()
450 u32 size = cac_table->ucNumEntries * sizeof(struct amdgpu_cac_leakage_table); in amdgpu_parse_extended_power_table()
451 adev->pm.dpm.dyn_state.cac_leakage_table.entries = kzalloc(size, GFP_KERNEL); in amdgpu_parse_extended_power_table()
452 if (!adev->pm.dpm.dyn_state.cac_leakage_table.entries) { in amdgpu_parse_extended_power_table()
454 return -ENOMEM; in amdgpu_parse_extended_power_table()
456 entry = &cac_table->entries[0]; in amdgpu_parse_extended_power_table()
457 for (i = 0; i < cac_table->ucNumEntries; i++) { in amdgpu_parse_extended_power_table()
458 if (adev->pm.dpm.platform_caps & ATOM_PP_PLATFORM_CAP_EVV) { in amdgpu_parse_extended_power_table()
459 adev->pm.dpm.dyn_state.cac_leakage_table.entries[i].vddc1 = in amdgpu_parse_extended_power_table()
460 le16_to_cpu(entry->usVddc1); in amdgpu_parse_extended_power_table()
461 adev->pm.dpm.dyn_state.cac_leakage_table.entries[i].vddc2 = in amdgpu_parse_extended_power_table()
462 le16_to_cpu(entry->usVddc2); in amdgpu_parse_extended_power_table()
463 adev->pm.dpm.dyn_state.cac_leakage_table.entries[i].vddc3 = in amdgpu_parse_extended_power_table()
464 le16_to_cpu(entry->usVddc3); in amdgpu_parse_extended_power_table()
466 adev->pm.dpm.dyn_state.cac_leakage_table.entries[i].vddc = in amdgpu_parse_extended_power_table()
467 le16_to_cpu(entry->usVddc); in amdgpu_parse_extended_power_table()
468 adev->pm.dpm.dyn_state.cac_leakage_table.entries[i].leakage = in amdgpu_parse_extended_power_table()
469 le32_to_cpu(entry->ulLeakageValue); in amdgpu_parse_extended_power_table()
474 adev->pm.dpm.dyn_state.cac_leakage_table.count = cac_table->ucNumEntries; in amdgpu_parse_extended_power_table()
479 if (le16_to_cpu(power_info->pplib.usTableSize) >= in amdgpu_parse_extended_power_table()
482 (mode_info->atom_context->bios + data_offset + in amdgpu_parse_extended_power_table()
483 le16_to_cpu(power_info->pplib3.usExtendendedHeaderOffset)); in amdgpu_parse_extended_power_table()
484 if ((le16_to_cpu(ext_hdr->usSize) >= SIZE_OF_ATOM_PPLIB_EXTENDEDHEADER_V2) && in amdgpu_parse_extended_power_table()
485 ext_hdr->usVCETableOffset) { in amdgpu_parse_extended_power_table()
487 (mode_info->atom_context->bios + data_offset + in amdgpu_parse_extended_power_table()
488 le16_to_cpu(ext_hdr->usVCETableOffset) + 1); in amdgpu_parse_extended_power_table()
491 (mode_info->atom_context->bios + data_offset + in amdgpu_parse_extended_power_table()
492 le16_to_cpu(ext_hdr->usVCETableOffset) + 1 + in amdgpu_parse_extended_power_table()
493 1 + array->ucNumEntries * sizeof(VCEClockInfo)); in amdgpu_parse_extended_power_table()
496 (mode_info->atom_context->bios + data_offset + in amdgpu_parse_extended_power_table()
497 le16_to_cpu(ext_hdr->usVCETableOffset) + 1 + in amdgpu_parse_extended_power_table()
498 1 + (array->ucNumEntries * sizeof (VCEClockInfo)) + in amdgpu_parse_extended_power_table()
499 1 + (limits->numEntries * sizeof(ATOM_PPLIB_VCE_Clock_Voltage_Limit_Record))); in amdgpu_parse_extended_power_table()
503 u32 size = limits->numEntries * in amdgpu_parse_extended_power_table()
505 adev->pm.dpm.dyn_state.vce_clock_voltage_dependency_table.entries = in amdgpu_parse_extended_power_table()
507 if (!adev->pm.dpm.dyn_state.vce_clock_voltage_dependency_table.entries) { in amdgpu_parse_extended_power_table()
509 return -ENOMEM; in amdgpu_parse_extended_power_table()
511 adev->pm.dpm.dyn_state.vce_clock_voltage_dependency_table.count = in amdgpu_parse_extended_power_table()
512 limits->numEntries; in amdgpu_parse_extended_power_table()
513 entry = &limits->entries[0]; in amdgpu_parse_extended_power_table()
514 state_entry = &states->entries[0]; in amdgpu_parse_extended_power_table()
515 for (i = 0; i < limits->numEntries; i++) { in amdgpu_parse_extended_power_table()
517 ((u8 *)&array->entries[0] + in amdgpu_parse_extended_power_table()
518 (entry->ucVCEClockInfoIndex * sizeof(VCEClockInfo))); in amdgpu_parse_extended_power_table()
519 adev->pm.dpm.dyn_state.vce_clock_voltage_dependency_table.entries[i].evclk = in amdgpu_parse_extended_power_table()
520 le16_to_cpu(vce_clk->usEVClkLow) | (vce_clk->ucEVClkHigh << 16); in amdgpu_parse_extended_power_table()
521 adev->pm.dpm.dyn_state.vce_clock_voltage_dependency_table.entries[i].ecclk = in amdgpu_parse_extended_power_table()
522 le16_to_cpu(vce_clk->usECClkLow) | (vce_clk->ucECClkHigh << 16); in amdgpu_parse_extended_power_table()
523 adev->pm.dpm.dyn_state.vce_clock_voltage_dependency_table.entries[i].v = in amdgpu_parse_extended_power_table()
524 le16_to_cpu(entry->usVoltage); in amdgpu_parse_extended_power_table()
528 adev->pm.dpm.num_of_vce_states = in amdgpu_parse_extended_power_table()
529 states->numEntries > AMD_MAX_VCE_LEVELS ? in amdgpu_parse_extended_power_table()
530 AMD_MAX_VCE_LEVELS : states->numEntries; in amdgpu_parse_extended_power_table()
531 for (i = 0; i < adev->pm.dpm.num_of_vce_states; i++) { in amdgpu_parse_extended_power_table()
533 ((u8 *)&array->entries[0] + in amdgpu_parse_extended_power_table()
534 (state_entry->ucVCEClockInfoIndex * sizeof(VCEClockInfo))); in amdgpu_parse_extended_power_table()
535 adev->pm.dpm.vce_states[i].evclk = in amdgpu_parse_extended_power_table()
536 le16_to_cpu(vce_clk->usEVClkLow) | (vce_clk->ucEVClkHigh << 16); in amdgpu_parse_extended_power_table()
537 adev->pm.dpm.vce_states[i].ecclk = in amdgpu_parse_extended_power_table()
538 le16_to_cpu(vce_clk->usECClkLow) | (vce_clk->ucECClkHigh << 16); in amdgpu_parse_extended_power_table()
539 adev->pm.dpm.vce_states[i].clk_idx = in amdgpu_parse_extended_power_table()
540 state_entry->ucClockInfoIndex & 0x3f; in amdgpu_parse_extended_power_table()
541 adev->pm.dpm.vce_states[i].pstate = in amdgpu_parse_extended_power_table()
542 (state_entry->ucClockInfoIndex & 0xc0) >> 6; in amdgpu_parse_extended_power_table()
547 if ((le16_to_cpu(ext_hdr->usSize) >= SIZE_OF_ATOM_PPLIB_EXTENDEDHEADER_V3) && in amdgpu_parse_extended_power_table()
548 ext_hdr->usUVDTableOffset) { in amdgpu_parse_extended_power_table()
550 (mode_info->atom_context->bios + data_offset + in amdgpu_parse_extended_power_table()
551 le16_to_cpu(ext_hdr->usUVDTableOffset) + 1); in amdgpu_parse_extended_power_table()
554 (mode_info->atom_context->bios + data_offset + in amdgpu_parse_extended_power_table()
555 le16_to_cpu(ext_hdr->usUVDTableOffset) + 1 + in amdgpu_parse_extended_power_table()
556 1 + (array->ucNumEntries * sizeof (UVDClockInfo))); in amdgpu_parse_extended_power_table()
558 u32 size = limits->numEntries * in amdgpu_parse_extended_power_table()
560 adev->pm.dpm.dyn_state.uvd_clock_voltage_dependency_table.entries = in amdgpu_parse_extended_power_table()
562 if (!adev->pm.dpm.dyn_state.uvd_clock_voltage_dependency_table.entries) { in amdgpu_parse_extended_power_table()
564 return -ENOMEM; in amdgpu_parse_extended_power_table()
566 adev->pm.dpm.dyn_state.uvd_clock_voltage_dependency_table.count = in amdgpu_parse_extended_power_table()
567 limits->numEntries; in amdgpu_parse_extended_power_table()
568 entry = &limits->entries[0]; in amdgpu_parse_extended_power_table()
569 for (i = 0; i < limits->numEntries; i++) { in amdgpu_parse_extended_power_table()
571 ((u8 *)&array->entries[0] + in amdgpu_parse_extended_power_table()
572 (entry->ucUVDClockInfoIndex * sizeof(UVDClockInfo))); in amdgpu_parse_extended_power_table()
573 adev->pm.dpm.dyn_state.uvd_clock_voltage_dependency_table.entries[i].vclk = in amdgpu_parse_extended_power_table()
574 le16_to_cpu(uvd_clk->usVClkLow) | (uvd_clk->ucVClkHigh << 16); in amdgpu_parse_extended_power_table()
575 adev->pm.dpm.dyn_state.uvd_clock_voltage_dependency_table.entries[i].dclk = in amdgpu_parse_extended_power_table()
576 le16_to_cpu(uvd_clk->usDClkLow) | (uvd_clk->ucDClkHigh << 16); in amdgpu_parse_extended_power_table()
577 adev->pm.dpm.dyn_state.uvd_clock_voltage_dependency_table.entries[i].v = in amdgpu_parse_extended_power_table()
578 le16_to_cpu(entry->usVoltage); in amdgpu_parse_extended_power_table()
583 if ((le16_to_cpu(ext_hdr->usSize) >= SIZE_OF_ATOM_PPLIB_EXTENDEDHEADER_V4) && in amdgpu_parse_extended_power_table()
584 ext_hdr->usSAMUTableOffset) { in amdgpu_parse_extended_power_table()
587 (mode_info->atom_context->bios + data_offset + in amdgpu_parse_extended_power_table()
588 le16_to_cpu(ext_hdr->usSAMUTableOffset) + 1); in amdgpu_parse_extended_power_table()
590 u32 size = limits->numEntries * in amdgpu_parse_extended_power_table()
592 adev->pm.dpm.dyn_state.samu_clock_voltage_dependency_table.entries = in amdgpu_parse_extended_power_table()
594 if (!adev->pm.dpm.dyn_state.samu_clock_voltage_dependency_table.entries) { in amdgpu_parse_extended_power_table()
596 return -ENOMEM; in amdgpu_parse_extended_power_table()
598 adev->pm.dpm.dyn_state.samu_clock_voltage_dependency_table.count = in amdgpu_parse_extended_power_table()
599 limits->numEntries; in amdgpu_parse_extended_power_table()
600 entry = &limits->entries[0]; in amdgpu_parse_extended_power_table()
601 for (i = 0; i < limits->numEntries; i++) { in amdgpu_parse_extended_power_table()
602 adev->pm.dpm.dyn_state.samu_clock_voltage_dependency_table.entries[i].clk = in amdgpu_parse_extended_power_table()
603 le16_to_cpu(entry->usSAMClockLow) | (entry->ucSAMClockHigh << 16); in amdgpu_parse_extended_power_table()
604 adev->pm.dpm.dyn_state.samu_clock_voltage_dependency_table.entries[i].v = in amdgpu_parse_extended_power_table()
605 le16_to_cpu(entry->usVoltage); in amdgpu_parse_extended_power_table()
610 if ((le16_to_cpu(ext_hdr->usSize) >= SIZE_OF_ATOM_PPLIB_EXTENDEDHEADER_V5) && in amdgpu_parse_extended_power_table()
611 ext_hdr->usPPMTableOffset) { in amdgpu_parse_extended_power_table()
613 (mode_info->atom_context->bios + data_offset + in amdgpu_parse_extended_power_table()
614 le16_to_cpu(ext_hdr->usPPMTableOffset)); in amdgpu_parse_extended_power_table()
615 adev->pm.dpm.dyn_state.ppm_table = in amdgpu_parse_extended_power_table()
617 if (!adev->pm.dpm.dyn_state.ppm_table) { in amdgpu_parse_extended_power_table()
619 return -ENOMEM; in amdgpu_parse_extended_power_table()
621 adev->pm.dpm.dyn_state.ppm_table->ppm_design = ppm->ucPpmDesign; in amdgpu_parse_extended_power_table()
622 adev->pm.dpm.dyn_state.ppm_table->cpu_core_number = in amdgpu_parse_extended_power_table()
623 le16_to_cpu(ppm->usCpuCoreNumber); in amdgpu_parse_extended_power_table()
624 adev->pm.dpm.dyn_state.ppm_table->platform_tdp = in amdgpu_parse_extended_power_table()
625 le32_to_cpu(ppm->ulPlatformTDP); in amdgpu_parse_extended_power_table()
626 adev->pm.dpm.dyn_state.ppm_table->small_ac_platform_tdp = in amdgpu_parse_extended_power_table()
627 le32_to_cpu(ppm->ulSmallACPlatformTDP); in amdgpu_parse_extended_power_table()
628 adev->pm.dpm.dyn_state.ppm_table->platform_tdc = in amdgpu_parse_extended_power_table()
629 le32_to_cpu(ppm->ulPlatformTDC); in amdgpu_parse_extended_power_table()
630 adev->pm.dpm.dyn_state.ppm_table->small_ac_platform_tdc = in amdgpu_parse_extended_power_table()
631 le32_to_cpu(ppm->ulSmallACPlatformTDC); in amdgpu_parse_extended_power_table()
632 adev->pm.dpm.dyn_state.ppm_table->apu_tdp = in amdgpu_parse_extended_power_table()
633 le32_to_cpu(ppm->ulApuTDP); in amdgpu_parse_extended_power_table()
634 adev->pm.dpm.dyn_state.ppm_table->dgpu_tdp = in amdgpu_parse_extended_power_table()
635 le32_to_cpu(ppm->ulDGpuTDP); in amdgpu_parse_extended_power_table()
636 adev->pm.dpm.dyn_state.ppm_table->dgpu_ulv_power = in amdgpu_parse_extended_power_table()
637 le32_to_cpu(ppm->ulDGpuUlvPower); in amdgpu_parse_extended_power_table()
638 adev->pm.dpm.dyn_state.ppm_table->tj_max = in amdgpu_parse_extended_power_table()
639 le32_to_cpu(ppm->ulTjmax); in amdgpu_parse_extended_power_table()
641 if ((le16_to_cpu(ext_hdr->usSize) >= SIZE_OF_ATOM_PPLIB_EXTENDEDHEADER_V6) && in amdgpu_parse_extended_power_table()
642 ext_hdr->usACPTableOffset) { in amdgpu_parse_extended_power_table()
645 (mode_info->atom_context->bios + data_offset + in amdgpu_parse_extended_power_table()
646 le16_to_cpu(ext_hdr->usACPTableOffset) + 1); in amdgpu_parse_extended_power_table()
648 u32 size = limits->numEntries * in amdgpu_parse_extended_power_table()
650 adev->pm.dpm.dyn_state.acp_clock_voltage_dependency_table.entries = in amdgpu_parse_extended_power_table()
652 if (!adev->pm.dpm.dyn_state.acp_clock_voltage_dependency_table.entries) { in amdgpu_parse_extended_power_table()
654 return -ENOMEM; in amdgpu_parse_extended_power_table()
656 adev->pm.dpm.dyn_state.acp_clock_voltage_dependency_table.count = in amdgpu_parse_extended_power_table()
657 limits->numEntries; in amdgpu_parse_extended_power_table()
658 entry = &limits->entries[0]; in amdgpu_parse_extended_power_table()
659 for (i = 0; i < limits->numEntries; i++) { in amdgpu_parse_extended_power_table()
660 adev->pm.dpm.dyn_state.acp_clock_voltage_dependency_table.entries[i].clk = in amdgpu_parse_extended_power_table()
661 le16_to_cpu(entry->usACPClockLow) | (entry->ucACPClockHigh << 16); in amdgpu_parse_extended_power_table()
662 adev->pm.dpm.dyn_state.acp_clock_voltage_dependency_table.entries[i].v = in amdgpu_parse_extended_power_table()
663 le16_to_cpu(entry->usVoltage); in amdgpu_parse_extended_power_table()
668 if ((le16_to_cpu(ext_hdr->usSize) >= SIZE_OF_ATOM_PPLIB_EXTENDEDHEADER_V7) && in amdgpu_parse_extended_power_table()
669 ext_hdr->usPowerTuneTableOffset) { in amdgpu_parse_extended_power_table()
670 u8 rev = *(u8 *)(mode_info->atom_context->bios + data_offset + in amdgpu_parse_extended_power_table()
671 le16_to_cpu(ext_hdr->usPowerTuneTableOffset)); in amdgpu_parse_extended_power_table()
673 adev->pm.dpm.dyn_state.cac_tdp_table = in amdgpu_parse_extended_power_table()
675 if (!adev->pm.dpm.dyn_state.cac_tdp_table) { in amdgpu_parse_extended_power_table()
677 return -ENOMEM; in amdgpu_parse_extended_power_table()
681 (mode_info->atom_context->bios + data_offset + in amdgpu_parse_extended_power_table()
682 le16_to_cpu(ext_hdr->usPowerTuneTableOffset)); in amdgpu_parse_extended_power_table()
683 adev->pm.dpm.dyn_state.cac_tdp_table->maximum_power_delivery_limit = in amdgpu_parse_extended_power_table()
684 ppt->usMaximumPowerDeliveryLimit; in amdgpu_parse_extended_power_table()
685 pt = &ppt->power_tune_table; in amdgpu_parse_extended_power_table()
688 (mode_info->atom_context->bios + data_offset + in amdgpu_parse_extended_power_table()
689 le16_to_cpu(ext_hdr->usPowerTuneTableOffset)); in amdgpu_parse_extended_power_table()
690 adev->pm.dpm.dyn_state.cac_tdp_table->maximum_power_delivery_limit = 255; in amdgpu_parse_extended_power_table()
691 pt = &ppt->power_tune_table; in amdgpu_parse_extended_power_table()
693 adev->pm.dpm.dyn_state.cac_tdp_table->tdp = le16_to_cpu(pt->usTDP); in amdgpu_parse_extended_power_table()
694 adev->pm.dpm.dyn_state.cac_tdp_table->configurable_tdp = in amdgpu_parse_extended_power_table()
695 le16_to_cpu(pt->usConfigurableTDP); in amdgpu_parse_extended_power_table()
696 adev->pm.dpm.dyn_state.cac_tdp_table->tdc = le16_to_cpu(pt->usTDC); in amdgpu_parse_extended_power_table()
697 adev->pm.dpm.dyn_state.cac_tdp_table->battery_power_limit = in amdgpu_parse_extended_power_table()
698 le16_to_cpu(pt->usBatteryPowerLimit); in amdgpu_parse_extended_power_table()
699 adev->pm.dpm.dyn_state.cac_tdp_table->small_power_limit = in amdgpu_parse_extended_power_table()
700 le16_to_cpu(pt->usSmallPowerLimit); in amdgpu_parse_extended_power_table()
701 adev->pm.dpm.dyn_state.cac_tdp_table->low_cac_leakage = in amdgpu_parse_extended_power_table()
702 le16_to_cpu(pt->usLowCACLeakage); in amdgpu_parse_extended_power_table()
703 adev->pm.dpm.dyn_state.cac_tdp_table->high_cac_leakage = in amdgpu_parse_extended_power_table()
704 le16_to_cpu(pt->usHighCACLeakage); in amdgpu_parse_extended_power_table()
706 if ((le16_to_cpu(ext_hdr->usSize) >= SIZE_OF_ATOM_PPLIB_EXTENDEDHEADER_V8) && in amdgpu_parse_extended_power_table()
707 ext_hdr->usSclkVddgfxTableOffset) { in amdgpu_parse_extended_power_table()
709 (mode_info->atom_context->bios + data_offset + in amdgpu_parse_extended_power_table()
710 le16_to_cpu(ext_hdr->usSclkVddgfxTableOffset)); in amdgpu_parse_extended_power_table()
712 &adev->pm.dpm.dyn_state.vddgfx_dependency_on_sclk, in amdgpu_parse_extended_power_table()
715 kfree(adev->pm.dpm.dyn_state.vddgfx_dependency_on_sclk.entries); in amdgpu_parse_extended_power_table()
726 struct amdgpu_dpm_dynamic_state *dyn_state = &adev->pm.dpm.dyn_state; in amdgpu_free_extended_power_table()
728 kfree(dyn_state->vddc_dependency_on_sclk.entries); in amdgpu_free_extended_power_table()
729 kfree(dyn_state->vddci_dependency_on_mclk.entries); in amdgpu_free_extended_power_table()
730 kfree(dyn_state->vddc_dependency_on_mclk.entries); in amdgpu_free_extended_power_table()
731 kfree(dyn_state->mvdd_dependency_on_mclk.entries); in amdgpu_free_extended_power_table()
732 kfree(dyn_state->cac_leakage_table.entries); in amdgpu_free_extended_power_table()
733 kfree(dyn_state->phase_shedding_limits_table.entries); in amdgpu_free_extended_power_table()
734 kfree(dyn_state->ppm_table); in amdgpu_free_extended_power_table()
735 kfree(dyn_state->cac_tdp_table); in amdgpu_free_extended_power_table()
736 kfree(dyn_state->vce_clock_voltage_dependency_table.entries); in amdgpu_free_extended_power_table()
737 kfree(dyn_state->uvd_clock_voltage_dependency_table.entries); in amdgpu_free_extended_power_table()
738 kfree(dyn_state->samu_clock_voltage_dependency_table.entries); in amdgpu_free_extended_power_table()
739 kfree(dyn_state->acp_clock_voltage_dependency_table.entries); in amdgpu_free_extended_power_table()
740 kfree(dyn_state->vddgfx_dependency_on_sclk.entries); in amdgpu_free_extended_power_table()
753 "adt7473",
768 struct amdgpu_mode_info *mode_info = &adev->mode_info; in amdgpu_add_thermal_controller()
776 if (!amdgpu_atom_parse_data_header(mode_info->atom_context, index, NULL, in amdgpu_add_thermal_controller()
780 (mode_info->atom_context->bios + data_offset); in amdgpu_add_thermal_controller()
781 controller = &power_table->sThermalController; in amdgpu_add_thermal_controller()
784 if (controller->ucType > 0) { in amdgpu_add_thermal_controller()
785 if (controller->ucFanParameters & ATOM_PP_FANPARAMETERS_NOFAN) in amdgpu_add_thermal_controller()
786 adev->pm.no_fan = true; in amdgpu_add_thermal_controller()
787 adev->pm.fan_pulses_per_revolution = in amdgpu_add_thermal_controller()
788 controller->ucFanParameters & ATOM_PP_FANPARAMETERS_TACHOMETER_PULSES_PER_REVOLUTION_MASK; in amdgpu_add_thermal_controller()
789 if (adev->pm.fan_pulses_per_revolution) { in amdgpu_add_thermal_controller()
790 adev->pm.fan_min_rpm = controller->ucFanMinRPM; in amdgpu_add_thermal_controller()
791 adev->pm.fan_max_rpm = controller->ucFanMaxRPM; in amdgpu_add_thermal_controller()
793 if (controller->ucType == ATOM_PP_THERMALCONTROLLER_RV6xx) { in amdgpu_add_thermal_controller()
795 (controller->ucFanParameters & in amdgpu_add_thermal_controller()
797 adev->pm.int_thermal_type = THERMAL_TYPE_RV6XX; in amdgpu_add_thermal_controller()
798 } else if (controller->ucType == ATOM_PP_THERMALCONTROLLER_RV770) { in amdgpu_add_thermal_controller()
800 (controller->ucFanParameters & in amdgpu_add_thermal_controller()
802 adev->pm.int_thermal_type = THERMAL_TYPE_RV770; in amdgpu_add_thermal_controller()
803 } else if (controller->ucType == ATOM_PP_THERMALCONTROLLER_EVERGREEN) { in amdgpu_add_thermal_controller()
805 (controller->ucFanParameters & in amdgpu_add_thermal_controller()
807 adev->pm.int_thermal_type = THERMAL_TYPE_EVERGREEN; in amdgpu_add_thermal_controller()
808 } else if (controller->ucType == ATOM_PP_THERMALCONTROLLER_SUMO) { in amdgpu_add_thermal_controller()
810 (controller->ucFanParameters & in amdgpu_add_thermal_controller()
812 adev->pm.int_thermal_type = THERMAL_TYPE_SUMO; in amdgpu_add_thermal_controller()
813 } else if (controller->ucType == ATOM_PP_THERMALCONTROLLER_NISLANDS) { in amdgpu_add_thermal_controller()
815 (controller->ucFanParameters & in amdgpu_add_thermal_controller()
817 adev->pm.int_thermal_type = THERMAL_TYPE_NI; in amdgpu_add_thermal_controller()
818 } else if (controller->ucType == ATOM_PP_THERMALCONTROLLER_SISLANDS) { in amdgpu_add_thermal_controller()
820 (controller->ucFanParameters & in amdgpu_add_thermal_controller()
822 adev->pm.int_thermal_type = THERMAL_TYPE_SI; in amdgpu_add_thermal_controller()
823 } else if (controller->ucType == ATOM_PP_THERMALCONTROLLER_CISLANDS) { in amdgpu_add_thermal_controller()
825 (controller->ucFanParameters & in amdgpu_add_thermal_controller()
827 adev->pm.int_thermal_type = THERMAL_TYPE_CI; in amdgpu_add_thermal_controller()
828 } else if (controller->ucType == ATOM_PP_THERMALCONTROLLER_KAVERI) { in amdgpu_add_thermal_controller()
830 (controller->ucFanParameters & in amdgpu_add_thermal_controller()
832 adev->pm.int_thermal_type = THERMAL_TYPE_KV; in amdgpu_add_thermal_controller()
833 } else if (controller->ucType == ATOM_PP_THERMALCONTROLLER_EXTERNAL_GPIO) { in amdgpu_add_thermal_controller()
835 (controller->ucFanParameters & in amdgpu_add_thermal_controller()
837 adev->pm.int_thermal_type = THERMAL_TYPE_EXTERNAL_GPIO; in amdgpu_add_thermal_controller()
838 } else if (controller->ucType == in amdgpu_add_thermal_controller()
840 DRM_INFO("ADT7473 with internal thermal controller %s fan control\n", in amdgpu_add_thermal_controller()
841 (controller->ucFanParameters & in amdgpu_add_thermal_controller()
843 adev->pm.int_thermal_type = THERMAL_TYPE_ADT7473_WITH_INTERNAL; in amdgpu_add_thermal_controller()
844 } else if (controller->ucType == in amdgpu_add_thermal_controller()
847 (controller->ucFanParameters & in amdgpu_add_thermal_controller()
849 adev->pm.int_thermal_type = THERMAL_TYPE_EMC2103_WITH_INTERNAL; in amdgpu_add_thermal_controller()
850 } else if (controller->ucType < ARRAY_SIZE(pp_lib_thermal_controller_names)) { in amdgpu_add_thermal_controller()
852 pp_lib_thermal_controller_names[controller->ucType], in amdgpu_add_thermal_controller()
853 controller->ucI2cAddress >> 1, in amdgpu_add_thermal_controller()
854 (controller->ucFanParameters & in amdgpu_add_thermal_controller()
856 adev->pm.int_thermal_type = THERMAL_TYPE_EXTERNAL; in amdgpu_add_thermal_controller()
857 i2c_bus = amdgpu_atombios_lookup_i2c_gpio(adev, controller->ucI2cLine); in amdgpu_add_thermal_controller()
858 adev->pm.i2c_bus = amdgpu_i2c_lookup(adev, &i2c_bus); in amdgpu_add_thermal_controller()
859 if (adev->pm.i2c_bus) { in amdgpu_add_thermal_controller()
861 const char *name = pp_lib_thermal_controller_names[controller->ucType]; in amdgpu_add_thermal_controller()
862 info.addr = controller->ucI2cAddress >> 1; in amdgpu_add_thermal_controller()
864 i2c_new_client_device(&adev->pm.i2c_bus->adapter, &info); in amdgpu_add_thermal_controller()
867 DRM_INFO("Unknown thermal controller type %d at 0x%02x %s fan control\n", in amdgpu_add_thermal_controller()
868 controller->ucType, in amdgpu_add_thermal_controller()
869 controller->ucI2cAddress >> 1, in amdgpu_add_thermal_controller()
870 (controller->ucFanParameters & in amdgpu_add_thermal_controller()
906 if (idx < adev->pm.dpm.num_of_vce_states) in amdgpu_get_vce_clock_state()
907 return &adev->pm.dpm.vce_states[idx]; in amdgpu_get_vce_clock_state()
917 ret = smu_get_dpm_freq_range(&adev->smu, SMU_GFXCLK, in amdgpu_dpm_get_sclk()
925 return (adev)->powerplay.pp_funcs->get_sclk((adev)->powerplay.pp_handle, (low)); in amdgpu_dpm_get_sclk()
934 ret = smu_get_dpm_freq_range(&adev->smu, SMU_UCLK, in amdgpu_dpm_get_mclk()
942 return (adev)->powerplay.pp_funcs->get_mclk((adev)->powerplay.pp_handle, (low)); in amdgpu_dpm_get_mclk()
955 ret = smu_dpm_set_power_gate(&adev->smu, block_type, gate); in amdgpu_dpm_set_powergating_by_smu()
956 } else if (adev->powerplay.pp_funcs && in amdgpu_dpm_set_powergating_by_smu()
957 adev->powerplay.pp_funcs->set_powergating_by_smu) { in amdgpu_dpm_set_powergating_by_smu()
961 * Here adev->pm.mutex lock protection is enforced on in amdgpu_dpm_set_powergating_by_smu()
966 * Tainted: G OE 5.0.0-37-generic #40~18.04.1-Ubuntu in amdgpu_dpm_set_powergating_by_smu()
968 * cltst D 0 2028 2026 0x00000000 in amdgpu_dpm_set_powergating_by_smu()
984 mutex_lock(&adev->pm.mutex); in amdgpu_dpm_set_powergating_by_smu()
985 ret = ((adev)->powerplay.pp_funcs->set_powergating_by_smu( in amdgpu_dpm_set_powergating_by_smu()
986 (adev)->powerplay.pp_handle, block_type, gate)); in amdgpu_dpm_set_powergating_by_smu()
987 mutex_unlock(&adev->pm.mutex); in amdgpu_dpm_set_powergating_by_smu()
994 ret = smu_dpm_set_power_gate(&adev->smu, block_type, gate); in amdgpu_dpm_set_powergating_by_smu()
995 else if (adev->powerplay.pp_funcs && in amdgpu_dpm_set_powergating_by_smu()
996 adev->powerplay.pp_funcs->set_powergating_by_smu) in amdgpu_dpm_set_powergating_by_smu()
997 ret = ((adev)->powerplay.pp_funcs->set_powergating_by_smu( in amdgpu_dpm_set_powergating_by_smu()
998 (adev)->powerplay.pp_handle, block_type, gate)); in amdgpu_dpm_set_powergating_by_smu()
1002 ret = smu_dpm_set_power_gate(&adev->smu, block_type, gate); in amdgpu_dpm_set_powergating_by_smu()
1006 if (adev->powerplay.pp_funcs && in amdgpu_dpm_set_powergating_by_smu()
1007 adev->powerplay.pp_funcs->set_powergating_by_smu) in amdgpu_dpm_set_powergating_by_smu()
1008 ret = ((adev)->powerplay.pp_funcs->set_powergating_by_smu( in amdgpu_dpm_set_powergating_by_smu()
1009 (adev)->powerplay.pp_handle, block_type, gate)); in amdgpu_dpm_set_powergating_by_smu()
1020 const struct amd_pm_funcs *pp_funcs = adev->powerplay.pp_funcs; in amdgpu_dpm_baco_enter()
1021 void *pp_handle = adev->powerplay.pp_handle; in amdgpu_dpm_baco_enter()
1022 struct smu_context *smu = &adev->smu; in amdgpu_dpm_baco_enter()
1028 if (!pp_funcs || !pp_funcs->set_asic_baco_state) in amdgpu_dpm_baco_enter()
1029 return -ENOENT; in amdgpu_dpm_baco_enter()
1032 ret = pp_funcs->set_asic_baco_state(pp_handle, 1); in amdgpu_dpm_baco_enter()
1040 const struct amd_pm_funcs *pp_funcs = adev->powerplay.pp_funcs; in amdgpu_dpm_baco_exit()
1041 void *pp_handle = adev->powerplay.pp_handle; in amdgpu_dpm_baco_exit()
1042 struct smu_context *smu = &adev->smu; in amdgpu_dpm_baco_exit()
1048 if (!pp_funcs || !pp_funcs->set_asic_baco_state) in amdgpu_dpm_baco_exit()
1049 return -ENOENT; in amdgpu_dpm_baco_exit()
1052 ret = pp_funcs->set_asic_baco_state(pp_handle, 0); in amdgpu_dpm_baco_exit()
1064 ret = smu_set_mp1_state(&adev->smu, mp1_state); in amdgpu_dpm_set_mp1_state()
1065 } else if (adev->powerplay.pp_funcs && in amdgpu_dpm_set_mp1_state()
1066 adev->powerplay.pp_funcs->set_mp1_state) { in amdgpu_dpm_set_mp1_state()
1067 ret = adev->powerplay.pp_funcs->set_mp1_state( in amdgpu_dpm_set_mp1_state()
1068 adev->powerplay.pp_handle, in amdgpu_dpm_set_mp1_state()
1077 const struct amd_pm_funcs *pp_funcs = adev->powerplay.pp_funcs; in amdgpu_dpm_is_baco_supported()
1078 void *pp_handle = adev->powerplay.pp_handle; in amdgpu_dpm_is_baco_supported()
1079 struct smu_context *smu = &adev->smu; in amdgpu_dpm_is_baco_supported()
1085 if (!pp_funcs || !pp_funcs->get_asic_baco_capability) in amdgpu_dpm_is_baco_supported()
1088 if (pp_funcs->get_asic_baco_capability(pp_handle, &baco_cap)) in amdgpu_dpm_is_baco_supported()
1097 const struct amd_pm_funcs *pp_funcs = adev->powerplay.pp_funcs; in amdgpu_dpm_mode2_reset()
1098 void *pp_handle = adev->powerplay.pp_handle; in amdgpu_dpm_mode2_reset()
1099 struct smu_context *smu = &adev->smu; in amdgpu_dpm_mode2_reset()
1104 if (!pp_funcs || !pp_funcs->asic_reset_mode_2) in amdgpu_dpm_mode2_reset()
1105 return -ENOENT; in amdgpu_dpm_mode2_reset()
1107 return pp_funcs->asic_reset_mode_2(pp_handle); in amdgpu_dpm_mode2_reset()
1113 const struct amd_pm_funcs *pp_funcs = adev->powerplay.pp_funcs; in amdgpu_dpm_baco_reset()
1114 void *pp_handle = adev->powerplay.pp_handle; in amdgpu_dpm_baco_reset()
1115 struct smu_context *smu = &adev->smu; in amdgpu_dpm_baco_reset()
1128 || !pp_funcs->set_asic_baco_state) in amdgpu_dpm_baco_reset()
1129 return -ENOENT; in amdgpu_dpm_baco_reset()
1132 ret = pp_funcs->set_asic_baco_state(pp_handle, 1); in amdgpu_dpm_baco_reset()
1137 ret = pp_funcs->set_asic_baco_state(pp_handle, 0); in amdgpu_dpm_baco_reset()
1147 struct smu_context *smu = &adev->smu; in amdgpu_dpm_is_mode1_reset_supported()
1157 struct smu_context *smu = &adev->smu; in amdgpu_dpm_mode1_reset()
1162 return -EOPNOTSUPP; in amdgpu_dpm_mode1_reset()
1172 ret = smu_switch_power_profile(&adev->smu, type, en); in amdgpu_dpm_switch_power_profile()
1173 else if (adev->powerplay.pp_funcs && in amdgpu_dpm_switch_power_profile()
1174 adev->powerplay.pp_funcs->switch_power_profile) in amdgpu_dpm_switch_power_profile()
1175 ret = adev->powerplay.pp_funcs->switch_power_profile( in amdgpu_dpm_switch_power_profile()
1176 adev->powerplay.pp_handle, type, en); in amdgpu_dpm_switch_power_profile()
1187 ret = smu_set_xgmi_pstate(&adev->smu, pstate); in amdgpu_dpm_set_xgmi_pstate()
1188 else if (adev->powerplay.pp_funcs && in amdgpu_dpm_set_xgmi_pstate()
1189 adev->powerplay.pp_funcs->set_xgmi_pstate) in amdgpu_dpm_set_xgmi_pstate()
1190 ret = adev->powerplay.pp_funcs->set_xgmi_pstate(adev->powerplay.pp_handle, in amdgpu_dpm_set_xgmi_pstate()
1200 const struct amd_pm_funcs *pp_funcs = adev->powerplay.pp_funcs; in amdgpu_dpm_set_df_cstate()
1201 void *pp_handle = adev->powerplay.pp_handle; in amdgpu_dpm_set_df_cstate()
1202 struct smu_context *smu = &adev->smu; in amdgpu_dpm_set_df_cstate()
1207 pp_funcs->set_df_cstate) in amdgpu_dpm_set_df_cstate()
1208 ret = pp_funcs->set_df_cstate(pp_handle, cstate); in amdgpu_dpm_set_df_cstate()
1215 struct smu_context *smu = &adev->smu; in amdgpu_dpm_allow_xgmi_power_down()
1225 void *pp_handle = adev->powerplay.pp_handle; in amdgpu_dpm_enable_mgpu_fan_boost()
1227 adev->powerplay.pp_funcs; in amdgpu_dpm_enable_mgpu_fan_boost()
1228 struct smu_context *smu = &adev->smu; in amdgpu_dpm_enable_mgpu_fan_boost()
1233 else if (pp_funcs && pp_funcs->enable_mgpu_fan_boost) in amdgpu_dpm_enable_mgpu_fan_boost()
1234 ret = pp_funcs->enable_mgpu_fan_boost(pp_handle); in amdgpu_dpm_enable_mgpu_fan_boost()
1242 void *pp_handle = adev->powerplay.pp_handle; in amdgpu_dpm_set_clockgating_by_smu()
1244 adev->powerplay.pp_funcs; in amdgpu_dpm_set_clockgating_by_smu()
1247 if (pp_funcs && pp_funcs->set_clockgating_by_smu) in amdgpu_dpm_set_clockgating_by_smu()
1248 ret = pp_funcs->set_clockgating_by_smu(pp_handle, in amdgpu_dpm_set_clockgating_by_smu()
1257 void *pp_handle = adev->powerplay.pp_handle; in amdgpu_dpm_smu_i2c_bus_access()
1259 adev->powerplay.pp_funcs; in amdgpu_dpm_smu_i2c_bus_access()
1260 int ret = -EOPNOTSUPP; in amdgpu_dpm_smu_i2c_bus_access()
1262 if (pp_funcs && pp_funcs->smu_i2c_bus_access) in amdgpu_dpm_smu_i2c_bus_access()
1263 ret = pp_funcs->smu_i2c_bus_access(pp_handle, in amdgpu_dpm_smu_i2c_bus_access()
1271 if (adev->pm.dpm_enabled) { in amdgpu_pm_acpi_event_handler()
1272 mutex_lock(&adev->pm.mutex); in amdgpu_pm_acpi_event_handler()
1274 adev->pm.ac_power = true; in amdgpu_pm_acpi_event_handler()
1276 adev->pm.ac_power = false; in amdgpu_pm_acpi_event_handler()
1277 if (adev->powerplay.pp_funcs && in amdgpu_pm_acpi_event_handler()
1278 adev->powerplay.pp_funcs->enable_bapm) in amdgpu_pm_acpi_event_handler()
1279 amdgpu_dpm_enable_bapm(adev, adev->pm.ac_power); in amdgpu_pm_acpi_event_handler()
1280 mutex_unlock(&adev->pm.mutex); in amdgpu_pm_acpi_event_handler()
1283 smu_set_ac_dc(&adev->smu); in amdgpu_pm_acpi_event_handler()
1293 return -EINVAL; in amdgpu_dpm_read_sensor()
1296 ret = smu_read_sensor(&adev->smu, sensor, data, size); in amdgpu_dpm_read_sensor()
1298 if (adev->powerplay.pp_funcs && adev->powerplay.pp_funcs->read_sensor) in amdgpu_dpm_read_sensor()
1299 ret = adev->powerplay.pp_funcs->read_sensor((adev)->powerplay.pp_handle, in amdgpu_dpm_read_sensor()
1302 ret = -EINVAL; in amdgpu_dpm_read_sensor()
1317 if (!adev->pm.dpm_enabled) in amdgpu_dpm_thermal_work_handler()
1322 if (temp < adev->pm.dpm.thermal.min_temp) in amdgpu_dpm_thermal_work_handler()
1324 dpm_state = adev->pm.dpm.user_state; in amdgpu_dpm_thermal_work_handler()
1326 if (adev->pm.dpm.thermal.high_to_low) in amdgpu_dpm_thermal_work_handler()
1328 dpm_state = adev->pm.dpm.user_state; in amdgpu_dpm_thermal_work_handler()
1330 mutex_lock(&adev->pm.mutex); in amdgpu_dpm_thermal_work_handler()
1332 adev->pm.dpm.thermal_active = true; in amdgpu_dpm_thermal_work_handler()
1334 adev->pm.dpm.thermal_active = false; in amdgpu_dpm_thermal_work_handler()
1335 adev->pm.dpm.state = dpm_state; in amdgpu_dpm_thermal_work_handler()
1336 mutex_unlock(&adev->pm.mutex); in amdgpu_dpm_thermal_work_handler()
1347 bool single_display = (adev->pm.dpm.new_active_crtc_count < 2) ? in amdgpu_dpm_pick_power_state()
1351 if (single_display && adev->powerplay.pp_funcs->vblank_too_short) { in amdgpu_dpm_pick_power_state()
1356 /* certain older asics have a separare 3D performance state, in amdgpu_dpm_pick_power_state()
1367 for (i = 0; i < adev->pm.dpm.num_ps; i++) { in amdgpu_dpm_pick_power_state()
1368 ps = &adev->pm.dpm.ps[i]; in amdgpu_dpm_pick_power_state()
1369 ui_class = ps->class & ATOM_PPLIB_CLASSIFICATION_UI_MASK; in amdgpu_dpm_pick_power_state()
1374 if (ps->caps & ATOM_PPLIB_SINGLE_DISPLAY_ONLY) { in amdgpu_dpm_pick_power_state()
1383 if (ps->caps & ATOM_PPLIB_SINGLE_DISPLAY_ONLY) { in amdgpu_dpm_pick_power_state()
1392 if (ps->caps & ATOM_PPLIB_SINGLE_DISPLAY_ONLY) { in amdgpu_dpm_pick_power_state()
1401 if (adev->pm.dpm.uvd_ps) in amdgpu_dpm_pick_power_state()
1402 return adev->pm.dpm.uvd_ps; in amdgpu_dpm_pick_power_state()
1406 if (ps->class & ATOM_PPLIB_CLASSIFICATION_SDSTATE) in amdgpu_dpm_pick_power_state()
1410 if (ps->class & ATOM_PPLIB_CLASSIFICATION_HDSTATE) in amdgpu_dpm_pick_power_state()
1414 if (ps->class & ATOM_PPLIB_CLASSIFICATION_HD2STATE) in amdgpu_dpm_pick_power_state()
1418 if (ps->class2 & ATOM_PPLIB_CLASSIFICATION2_MVC) in amdgpu_dpm_pick_power_state()
1422 return adev->pm.dpm.boot_ps; in amdgpu_dpm_pick_power_state()
1424 if (ps->class & ATOM_PPLIB_CLASSIFICATION_THERMAL) in amdgpu_dpm_pick_power_state()
1428 if (ps->class & ATOM_PPLIB_CLASSIFICATION_ACPI) in amdgpu_dpm_pick_power_state()
1432 if (ps->class2 & ATOM_PPLIB_CLASSIFICATION2_ULV) in amdgpu_dpm_pick_power_state()
1436 if (ps->class & ATOM_PPLIB_CLASSIFICATION_3DPERFORMANCE) in amdgpu_dpm_pick_power_state()
1451 if (adev->pm.dpm.uvd_ps) { in amdgpu_dpm_pick_power_state()
1452 return adev->pm.dpm.uvd_ps; in amdgpu_dpm_pick_power_state()
1483 if (!adev->pm.dpm_enabled) in amdgpu_dpm_change_power_state_locked()
1486 if (adev->pm.dpm.user_state != adev->pm.dpm.state) { in amdgpu_dpm_change_power_state_locked()
1488 if ((!adev->pm.dpm.thermal_active) && in amdgpu_dpm_change_power_state_locked()
1489 (!adev->pm.dpm.uvd_active)) in amdgpu_dpm_change_power_state_locked()
1490 adev->pm.dpm.state = adev->pm.dpm.user_state; in amdgpu_dpm_change_power_state_locked()
1492 dpm_state = adev->pm.dpm.state; in amdgpu_dpm_change_power_state_locked()
1496 adev->pm.dpm.requested_ps = ps; in amdgpu_dpm_change_power_state_locked()
1500 if (amdgpu_dpm == 1 && adev->powerplay.pp_funcs->print_power_state) { in amdgpu_dpm_change_power_state_locked()
1502 amdgpu_dpm_print_power_state(adev, adev->pm.dpm.current_ps); in amdgpu_dpm_change_power_state_locked()
1504 amdgpu_dpm_print_power_state(adev, adev->pm.dpm.requested_ps); in amdgpu_dpm_change_power_state_locked()
1508 ps->vce_active = adev->pm.dpm.vce_active; in amdgpu_dpm_change_power_state_locked()
1509 if (adev->powerplay.pp_funcs->display_configuration_changed) in amdgpu_dpm_change_power_state_locked()
1516 if (adev->powerplay.pp_funcs->check_state_equal) { in amdgpu_dpm_change_power_state_locked()
1517 …if (0 != amdgpu_dpm_check_state_equal(adev, adev->pm.dpm.current_ps, adev->pm.dpm.requested_ps, &e… in amdgpu_dpm_change_power_state_locked()
1527 adev->pm.dpm.current_active_crtcs = adev->pm.dpm.new_active_crtcs; in amdgpu_dpm_change_power_state_locked()
1528 adev->pm.dpm.current_active_crtc_count = adev->pm.dpm.new_active_crtc_count; in amdgpu_dpm_change_power_state_locked()
1530 if (adev->powerplay.pp_funcs->force_performance_level) { in amdgpu_dpm_change_power_state_locked()
1531 if (adev->pm.dpm.thermal_active) { in amdgpu_dpm_change_power_state_locked()
1532 enum amd_dpm_forced_level level = adev->pm.dpm.forced_level; in amdgpu_dpm_change_power_state_locked()
1536 adev->pm.dpm.forced_level = level; in amdgpu_dpm_change_power_state_locked()
1539 amdgpu_dpm_force_performance_level(adev, adev->pm.dpm.forced_level); in amdgpu_dpm_change_power_state_locked()
1548 if (!adev->pm.dpm_enabled) in amdgpu_pm_compute_clocks()
1551 if (adev->mode_info.num_crtc) in amdgpu_pm_compute_clocks()
1555 struct amdgpu_ring *ring = adev->rings[i]; in amdgpu_pm_compute_clocks()
1556 if (ring && ring->sched.ready) in amdgpu_pm_compute_clocks()
1561 struct smu_dpm_context *smu_dpm = &adev->smu.smu_dpm; in amdgpu_pm_compute_clocks()
1562 smu_handle_task(&adev->smu, in amdgpu_pm_compute_clocks()
1563 smu_dpm->dpm_level, in amdgpu_pm_compute_clocks()
1567 if (adev->powerplay.pp_funcs->dispatch_tasks) { in amdgpu_pm_compute_clocks()
1569 mutex_lock(&adev->pm.mutex); in amdgpu_pm_compute_clocks()
1571 adev->pm.pm_display_cfg.num_display = adev->pm.dpm.new_active_crtc_count; in amdgpu_pm_compute_clocks()
1572 adev->pm.pm_display_cfg.vrefresh = amdgpu_dpm_get_vrefresh(adev); in amdgpu_pm_compute_clocks()
1573 adev->pm.pm_display_cfg.min_vblank_time = amdgpu_dpm_get_vblank_time(adev); in amdgpu_pm_compute_clocks()
1574 /* we have issues with mclk switching with refresh rates over 120 hz on the non-DC code. */ in amdgpu_pm_compute_clocks()
1575 if (adev->pm.pm_display_cfg.vrefresh > 120) in amdgpu_pm_compute_clocks()
1576 adev->pm.pm_display_cfg.min_vblank_time = 0; in amdgpu_pm_compute_clocks()
1577 if (adev->powerplay.pp_funcs->display_configuration_change) in amdgpu_pm_compute_clocks()
1578 adev->powerplay.pp_funcs->display_configuration_change( in amdgpu_pm_compute_clocks()
1579 adev->powerplay.pp_handle, in amdgpu_pm_compute_clocks()
1580 &adev->pm.pm_display_cfg); in amdgpu_pm_compute_clocks()
1581 mutex_unlock(&adev->pm.mutex); in amdgpu_pm_compute_clocks()
1585 mutex_lock(&adev->pm.mutex); in amdgpu_pm_compute_clocks()
1588 mutex_unlock(&adev->pm.mutex); in amdgpu_pm_compute_clocks()
1597 if (adev->family == AMDGPU_FAMILY_SI) { in amdgpu_dpm_enable_uvd()
1598 mutex_lock(&adev->pm.mutex); in amdgpu_dpm_enable_uvd()
1600 adev->pm.dpm.uvd_active = true; in amdgpu_dpm_enable_uvd()
1601 adev->pm.dpm.state = POWER_STATE_TYPE_INTERNAL_UVD; in amdgpu_dpm_enable_uvd()
1603 adev->pm.dpm.uvd_active = false; in amdgpu_dpm_enable_uvd()
1605 mutex_unlock(&adev->pm.mutex); in amdgpu_dpm_enable_uvd()
1611 DRM_ERROR("Dpm %s uvd failed, ret = %d. \n", in amdgpu_dpm_enable_uvd()
1615 if (adev->asic_type == CHIP_STONEY && in amdgpu_dpm_enable_uvd()
1616 adev->uvd.decode_image_width >= WIDTH_4K) { in amdgpu_dpm_enable_uvd()
1617 struct pp_hwmgr *hwmgr = adev->powerplay.pp_handle; in amdgpu_dpm_enable_uvd()
1619 if (hwmgr && hwmgr->hwmgr_func && in amdgpu_dpm_enable_uvd()
1620 hwmgr->hwmgr_func->update_nbdpm_pstate) in amdgpu_dpm_enable_uvd()
1621 hwmgr->hwmgr_func->update_nbdpm_pstate(hwmgr, in amdgpu_dpm_enable_uvd()
1632 if (adev->family == AMDGPU_FAMILY_SI) { in amdgpu_dpm_enable_vce()
1633 mutex_lock(&adev->pm.mutex); in amdgpu_dpm_enable_vce()
1635 adev->pm.dpm.vce_active = true; in amdgpu_dpm_enable_vce()
1637 adev->pm.dpm.vce_level = AMD_VCE_LEVEL_AC_ALL; in amdgpu_dpm_enable_vce()
1639 adev->pm.dpm.vce_active = false; in amdgpu_dpm_enable_vce()
1641 mutex_unlock(&adev->pm.mutex); in amdgpu_dpm_enable_vce()
1647 DRM_ERROR("Dpm %s vce failed, ret = %d. \n", in amdgpu_dpm_enable_vce()
1656 if (adev->powerplay.pp_funcs->print_power_state == NULL) in amdgpu_pm_print_power_states()
1659 for (i = 0; i < adev->pm.dpm.num_ps; i++) in amdgpu_pm_print_power_states()
1660 amdgpu_dpm_print_power_state(adev, &adev->pm.dpm.ps[i]); in amdgpu_pm_print_power_states()
1670 DRM_ERROR("Dpm %s jpeg failed, ret = %d. \n", in amdgpu_dpm_enable_jpeg()
1678 if (adev->powerplay.pp_funcs && adev->powerplay.pp_funcs->load_firmware) { in amdgpu_pm_load_smu_firmware()
1679 r = adev->powerplay.pp_funcs->load_firmware(adev->powerplay.pp_handle); in amdgpu_pm_load_smu_firmware()
1684 *smu_version = adev->pm.fw_version; in amdgpu_pm_load_smu_firmware()