dc/dml/dc_features.h

29 #define DC__PRESENT 1
30 #define DC__PRESENT__1 1
33 #define DC__NUM_DPP__4 1
34 #define DC__NUM_DPP__0_PRESENT 1
35 #define DC__NUM_DPP__1_PRESENT 1
36 #define DC__NUM_DPP__2_PRESENT 1
37 #define DC__NUM_DPP__3_PRESENT 1
39 #define DC__NUM_DPP__MAX__8 1
41 #define DC__PIPE_10BIT__0 1
42 #define DC__PIPE_10BIT__MAX 1
43 #define DC__PIPE_10BIT__MAX__1 1
45 #define DC__NUM_OPP__4 1
46 #define DC__NUM_OPP__0_PRESENT 1
47 #define DC__NUM_OPP__1_PRESENT 1
48 #define DC__NUM_OPP__2_PRESENT 1
49 #define DC__NUM_OPP__3_PRESENT 1
51 #define DC__NUM_OPP__MAX__6 1
53 #define DC__NUM_DSC__0 1
55 #define DC__NUM_DSC__MAX__6 1
56 #define DC__NUM_ABM 1
57 #define DC__NUM_ABM__1 1
58 #define DC__NUM_ABM__0_PRESENT 1
60 #define DC__NUM_ABM__MAX__2 1
62 #define DC__ODM_PRESENT__0 1
64 #define DC__NUM_OTG__4 1
65 #define DC__NUM_OTG__0_PRESENT 1
66 #define DC__NUM_OTG__1_PRESENT 1
67 #define DC__NUM_OTG__2_PRESENT 1
68 #define DC__NUM_OTG__3_PRESENT 1
70 #define DC__NUM_OTG__MAX__6 1
72 #define DC__NUM_DWB__2 1
73 #define DC__NUM_DWB__0_PRESENT 1
74 #define DC__NUM_DWB__1_PRESENT 1
76 #define DC__NUM_DWB__MAX__2 1
78 #define DC__NUM_DIG__4 1
79 #define DC__NUM_DIG__0_PRESENT 1
80 #define DC__NUM_DIG__1_PRESENT 1
81 #define DC__NUM_DIG__2_PRESENT 1
82 #define DC__NUM_DIG__3_PRESENT 1
84 #define DC__NUM_DIG__MAX__6 1
86 #define DC__NUM_AUX__4 1
87 #define DC__NUM_AUX__0_PRESENT 1
88 #define DC__NUM_AUX__1_PRESENT 1
89 #define DC__NUM_AUX__2_PRESENT 1
90 #define DC__NUM_AUX__3_PRESENT 1
92 #define DC__NUM_AUX__MAX__6 1
94 #define DC__NUM_AUDIO_STREAMS__4 1
95 #define DC__NUM_AUDIO_STREAMS__0_PRESENT 1
96 #define DC__NUM_AUDIO_STREAMS__1_PRESENT 1
97 #define DC__NUM_AUDIO_STREAMS__2_PRESENT 1
98 #define DC__NUM_AUDIO_STREAMS__3_PRESENT 1
100 #define DC__NUM_AUDIO_STREAMS__MAX__8 1
102 #define DC__NUM_AUDIO_ENDPOINTS__6 1
103 #define DC__NUM_AUDIO_ENDPOINTS__0_PRESENT 1
104 #define DC__NUM_AUDIO_ENDPOINTS__1_PRESENT 1
105 #define DC__NUM_AUDIO_ENDPOINTS__2_PRESENT 1
106 #define DC__NUM_AUDIO_ENDPOINTS__3_PRESENT 1
107 #define DC__NUM_AUDIO_ENDPOINTS__4_PRESENT 1
108 #define DC__NUM_AUDIO_ENDPOINTS__5_PRESENT 1
110 #define DC__NUM_AUDIO_ENDPOINTS__MAX__8 1
112 #define DC__NUM_AUDIO_INPUT_STREAMS__0 1
114 #define DC__NUM_AUDIO_INPUT_STREAMS__MAX__8 1
116 #define DC__NUM_AUDIO_INPUT_ENDPOINTS__0 1
118 #define DC__NUM_AUDIO_INPUT_ENDPOINTS__MAX__8 1
119 #define DC__NUM_CURSOR 1
120 #define DC__NUM_CURSOR__1 1
121 #define DC__NUM_CURSOR__0_PRESENT 1
123 #define DC__NUM_CURSOR__MAX__2 1
125 #define DC__DIGITAL_BYPASS_PRESENT__0 1
126 #define DC__HCID_HWMAJVER 1
127 #define DC__HCID_HWMAJVER__1 1
129 #define DC__HCID_HWMINVER__0 1
131 #define DC__HCID_HWREV__0 1
133 #define DC__ROMSTRAP_PRESENT__0 1
135 #define DC__NUM_RBBMIF_DECODES__30 1
137 #define DC__NUM_DBG_REGS__36 1
139 #define DC__NUM_PIPES_UNDERLAY__0 1
141 #define DC__NUM_PIPES_UNDERLAY__MAX__2 1
142 #define DC__NUM_VCE_ENGINE 1
143 #define DC__NUM_VCE_ENGINE__1 1
144 #define DC__NUM_VCE_ENGINE__0_PRESENT 1
146 #define DC__NUM_VCE_ENGINE__MAX__2 1
148 #define DC__OTG_EXTERNAL_SYNC_PRESENT__0 1
149 #define DC__OTG_CRC_PRESENT 1
150 #define DC__OTG_CRC_PRESENT__1 1
152 #define DC__VIP_PRESENT__0 1
154 #define DC__DTMTEST_PRESENT__0 1
155 #define DC__POWER_GATE_PRESENT 1
156 #define DC__POWER_GATE_PRESENT__1 1
157 #define DC__MEM_PG 1
158 #define DC__MEM_PG__1 1
160 #define DC__FMT_SRC_SEL_PRESENT__0 1
161 #define DC__DIG_FEATURES__HDMI_PRESENT 1
162 #define DC__DIG_FEATURES__HDMI_PRESENT__1 1
163 #define DC__DIG_FEATURES__DP_PRESENT 1
164 #define DC__DIG_FEATURES__DP_PRESENT__1 1
165 #define DC__DIG_FEATURES__DP_MST_PRESENT 1
166 #define DC__DIG_FEATURES__DP_MST_PRESENT__1 1
168 #define DC__DIG_LP_FEATURES__HDMI_PRESENT__0 1
169 #define DC__DIG_LP_FEATURES__DP_PRESENT 1
170 #define DC__DIG_LP_FEATURES__DP_PRESENT__1 1
172 #define DC__DIG_LP_FEATURES__DP_MST_PRESENT__0 1
174 #define DC__DIG_RESYNC_FIFO_SIZE__14 1
175 #define DC__DIG_RESYNC_FIFO_SIZE__0_PRESENT 1
176 #define DC__DIG_RESYNC_FIFO_SIZE__1_PRESENT 1
177 #define DC__DIG_RESYNC_FIFO_SIZE__2_PRESENT 1
178 #define DC__DIG_RESYNC_FIFO_SIZE__3_PRESENT 1
179 #define DC__DIG_RESYNC_FIFO_SIZE__4_PRESENT 1
180 #define DC__DIG_RESYNC_FIFO_SIZE__5_PRESENT 1
181 #define DC__DIG_RESYNC_FIFO_SIZE__6_PRESENT 1
182 #define DC__DIG_RESYNC_FIFO_SIZE__7_PRESENT 1
183 #define DC__DIG_RESYNC_FIFO_SIZE__8_PRESENT 1
184 #define DC__DIG_RESYNC_FIFO_SIZE__9_PRESENT 1
185 #define DC__DIG_RESYNC_FIFO_SIZE__10_PRESENT 1
186 #define DC__DIG_RESYNC_FIFO_SIZE__11_PRESENT 1
187 #define DC__DIG_RESYNC_FIFO_SIZE__12_PRESENT 1
188 #define DC__DIG_RESYNC_FIFO_SIZE__13_PRESENT 1
190 #define DC__DIG_RESYNC_FIFO_SIZE__MAX__16 1
192 #define DC__DAC_RESYNC_FIFO_SIZE__12 1
193 #define DC__DAC_RESYNC_FIFO_SIZE__0_PRESENT 1
194 #define DC__DAC_RESYNC_FIFO_SIZE__1_PRESENT 1
195 #define DC__DAC_RESYNC_FIFO_SIZE__2_PRESENT 1
196 #define DC__DAC_RESYNC_FIFO_SIZE__3_PRESENT 1
197 #define DC__DAC_RESYNC_FIFO_SIZE__4_PRESENT 1
198 #define DC__DAC_RESYNC_FIFO_SIZE__5_PRESENT 1
199 #define DC__DAC_RESYNC_FIFO_SIZE__6_PRESENT 1
200 #define DC__DAC_RESYNC_FIFO_SIZE__7_PRESENT 1
201 #define DC__DAC_RESYNC_FIFO_SIZE__8_PRESENT 1
202 #define DC__DAC_RESYNC_FIFO_SIZE__9_PRESENT 1
203 #define DC__DAC_RESYNC_FIFO_SIZE__10_PRESENT 1
204 #define DC__DAC_RESYNC_FIFO_SIZE__11_PRESENT 1
206 #define DC__DAC_RESYNC_FIFO_SIZE__MAX__16 1
208 #define DC__DVO_RESYNC_FIFO_SIZE__12 1
209 #define DC__DVO_RESYNC_FIFO_SIZE__0_PRESENT 1
210 #define DC__DVO_RESYNC_FIFO_SIZE__1_PRESENT 1
211 #define DC__DVO_RESYNC_FIFO_SIZE__2_PRESENT 1
212 #define DC__DVO_RESYNC_FIFO_SIZE__3_PRESENT 1
213 #define DC__DVO_RESYNC_FIFO_SIZE__4_PRESENT 1
214 #define DC__DVO_RESYNC_FIFO_SIZE__5_PRESENT 1
215 #define DC__DVO_RESYNC_FIFO_SIZE__6_PRESENT 1
216 #define DC__DVO_RESYNC_FIFO_SIZE__7_PRESENT 1
217 #define DC__DVO_RESYNC_FIFO_SIZE__8_PRESENT 1
218 #define DC__DVO_RESYNC_FIFO_SIZE__9_PRESENT 1
219 #define DC__DVO_RESYNC_FIFO_SIZE__10_PRESENT 1
220 #define DC__DVO_RESYNC_FIFO_SIZE__11_PRESENT 1
222 #define DC__DVO_RESYNC_FIFO_SIZE__MAX__16 1
223 #define DC__MEM_CDC_PRESENT 1
224 #define DC__MEM_CDC_PRESENT__1 1
226 #define DC__NUM_HPD__4 1
227 #define DC__NUM_HPD__0_PRESENT 1
228 #define DC__NUM_HPD__1_PRESENT 1
229 #define DC__NUM_HPD__2_PRESENT 1
230 #define DC__NUM_HPD__3_PRESENT 1
232 #define DC__NUM_HPD__MAX__6 1
234 #define DC__NUM_DDC_PAIRS__4 1
235 #define DC__NUM_DDC_PAIRS__0_PRESENT 1
236 #define DC__NUM_DDC_PAIRS__1_PRESENT 1
237 #define DC__NUM_DDC_PAIRS__2_PRESENT 1
238 #define DC__NUM_DDC_PAIRS__3_PRESENT 1
240 #define DC__NUM_DDC_PAIRS__MAX__6 1
242 #define DC__NUM_AUDIO_PLL__0 1
244 #define DC__NUM_AUDIO_PLL__MAX__2 1
245 #define DC__NUM_PIXEL_PLL 1
246 #define DC__NUM_PIXEL_PLL__1 1
247 #define DC__NUM_PIXEL_PLL__0_PRESENT 1
249 #define DC__NUM_PIXEL_PLL__MAX__4 1
251 #define DC__NUM_CASCADED_PLL__0 1
253 #define DC__NUM_CASCADED_PLL__MAX__3 1
254 #define DC__PIXCLK_FROM_PHYPLL 1
255 #define DC__PIXCLK_FROM_PHYPLL__1 1
257 #define DC__NB_STUTTER_MODE_PRESENT__0 1
259 #define DC__I2S0_AND_SPDIF0_PRESENT__0 1
261 #define DC__I2S1_PRESENT__0 1
263 #define DC__SPDIF1_PRESENT__0 1
265 #define DC__DSI_PRESENT__0 1
267 #define DC__DACA_PRESENT__0 1
269 #define DC__DACB_PRESENT__0 1
271 #define DC__NUM_PIPES__4 1
272 #define DC__NUM_PIPES__0_PRESENT 1
273 #define DC__NUM_PIPES__1_PRESENT 1
274 #define DC__NUM_PIPES__2_PRESENT 1
275 #define DC__NUM_PIPES__3_PRESENT 1
277 #define DC__NUM_PIPES__MAX__6 1
279 #define DC__NUM_DIG_LP__0 1
281 #define DC__NUM_DIG_LP__MAX__2 1
283 #define DC__DPDEBUG_PRESENT__0 1
284 #define DC__DISPLAY_WB_PRESENT 1
285 #define DC__DISPLAY_WB_PRESENT__1 1
287 #define DC__NUM_CWB__0 1
289 #define DC__NUM_CWB__MAX__2 1
291 #define DC__MVP_PRESENT__0 1
293 #define DC__DVO_PRESENT__0 1
295 #define DC__ABM_PRESENT__0 1
297 #define DC__BPHYC_PLL_PRESENT__0 1
299 #define DC__BPHYC_UNIPHY_PRESENT__0 1
301 #define DC__PHY_BROADCAST_PRESENT__0 1
303 #define DC__NUM_OF_DCRX_SD__0 1
305 #define DC__DVO_17BIT_MAPPING__0 1
307 #define DC__AVSYNC_PRESENT__0 1
309 #define DC__NUM_OF_DCRX_PORTS__0 1
310 #define DC__NUM_OF_DCRX_PORTS__MAX 1
311 #define DC__NUM_OF_DCRX_PORTS__MAX__1 1
313 #define DC__NUM_PHY__4 1
314 #define DC__NUM_PHY__0_PRESENT 1
315 #define DC__NUM_PHY__1_PRESENT 1
316 #define DC__NUM_PHY__2_PRESENT 1
317 #define DC__NUM_PHY__3_PRESENT 1
319 #define DC__NUM_PHY__MAX__7 1
321 #define DC__NUM_PHY_LP__0 1
323 #define DC__NUM_PHY_LP__MAX__2 1
325 #define DC__SYNC_CELL__VID_SYNC_GF14LPP 1
326 #define DC__USE_NEW_VSS 1
327 #define DC__USE_NEW_VSS__1 1
329 #define DC__SYNC_CELL_DISPCLK_NUM_LATCHES__6 1
331 #define DC__SYNC_CELL_DVOCLK_NUM_LATCHES__6 1
333 #define DC__SYNC_CELL_PIXCLK_NUM_LATCHES__6 1
335 #define DC__SYNC_CELL_SYMCLK_NUM_LATCHES__6 1
337 #define DC__SYNC_CELL_DPPCLK_NUM_LATCHES__6 1
339 #define DC__SYNC_CELL_DPREFCLK_NUM_LATCHES__6 1
341 #define DC__SYNC_CELL_REFCLK_NUM_LATCHES__6 1
343 #define DC__SYNC_CELL_PCIE_REFCLK_NUM_LATCHES__6 1
345 #define DC__SYNC_CELL_MVPCLK_NUM_LATCHES__6 1
347 #define DC__SYNC_CELL_SCLK_NUM_LATCHES__6 1
349 #define DC__SYNC_CELL_DCEFCLK_NUM_LATCHES__6 1
351 #define DC__SYNC_CELL_AMCLK_NUM_LATCHES__6 1
353 #define DC__SYNC_CELL_DSICLK_NUM_LATCHES__6 1
355 #define DC__SYNC_CELL_BYTECLK_NUM_LATCHES__6 1
357 #define DC__SYNC_CELL_ESCCLK_NUM_LATCHES__6 1
359 #define DC__SYNC_CELL_DB_CLK_NUM_LATCHES__6 1
360 #define UNIPHYA_PRESENT 1
361 #define UNIPHYA_PRESENT__1 1
362 #define DC__UNIPHYA_PRESENT 1
363 #define DC__UNIPHYA_PRESENT__1 1
364 #define UNIPHYB_PRESENT 1
365 #define UNIPHYB_PRESENT__1 1
366 #define DC__UNIPHYB_PRESENT 1
367 #define DC__UNIPHYB_PRESENT__1 1
368 #define UNIPHYC_PRESENT 1
369 #define UNIPHYC_PRESENT__1 1
370 #define DC__UNIPHYC_PRESENT 1
371 #define DC__UNIPHYC_PRESENT__1 1
372 #define UNIPHYD_PRESENT 1
373 #define UNIPHYD_PRESENT__1 1
374 #define DC__UNIPHYD_PRESENT 1
375 #define DC__UNIPHYD_PRESENT__1 1
377 #define UNIPHYE_PRESENT__0 1
379 #define DC__UNIPHYE_PRESENT__0 1
381 #define UNIPHYF_PRESENT__0 1
383 #define DC__UNIPHYF_PRESENT__0 1
385 #define UNIPHYG_PRESENT__0 1
387 #define DC__UNIPHYG_PRESENT__0 1
389 #define DC__TMDS_LINK__TMDS_LINK_DUAL 1
391 #define DC__WBSCL_PIXBW__8 1
393 #define DC__DWB_CSC_PRESENT__0 1
395 #define DC__DWB_LUMA_SCL_PRESENT__0 1
396 #define DC__DENTIST_INTERFACE_PRESENT 1
397 #define DC__DENTIST_INTERFACE_PRESENT__1 1
398 #define DC__GENERICA_PRESENT 1
399 #define DC__GENERICA_PRESENT__1 1
400 #define DC__GENERICB_PRESENT 1
401 #define DC__GENERICB_PRESENT__1 1
403 #define DC__GENERICC_PRESENT__0 1
405 #define DC__GENERICD_PRESENT__0 1
407 #define DC__GENERICE_PRESENT__0 1
409 #define DC__GENERICF_PRESENT__0 1
411 #define DC__GENERICG_PRESENT__0 1
412 #define DC__UNIPHY_VOLTAGE_MODE 1
413 #define DC__UNIPHY_VOLTAGE_MODE__1 1
415 #define DC__BLON_TYPE__DEDICATED 1
416 #define DC__UNIPHY_STAGGER_CH_PRESENT 1
417 #define DC__UNIPHY_STAGGER_CH_PRESENT__1 1
419 #define DC__XDMA_PRESENT__0 1
421 #define XDMA__PRESENT__0 1
423 #define DC__DP_MEM_PG__0 1
425 #define DP__MEM_PG__0 1
427 #define DC__AFMT_MEM_PG__0 1
429 #define AFMT__MEM_PG__0 1
431 #define DC__HDMI_MEM_PG__0 1
433 #define HDMI__MEM_PG__0 1
435 #define DC__I2C_MEM_PG__0 1
437 #define I2C__MEM_PG__0 1
439 #define DC__DSCL_MEM_PG__0 1
441 #define DSCL__MEM_PG__0 1
443 #define DC__CM_MEM_PG__0 1
445 #define CM__MEM_PG__0 1
447 #define DC__OBUF_MEM_PG__0 1
449 #define OBUF__MEM_PG__0 1
450 #define DC__WBIF_MEM_PG 1
451 #define DC__WBIF_MEM_PG__1 1
452 #define WBIF__MEM_PG 1
453 #define WBIF__MEM_PG__1 1
455 #define DC__VGA_MEM_PG__0 1
457 #define VGA__MEM_PG__0 1
459 #define DC__FMT_MEM_PG__0 1
461 #define FMT__MEM_PG__0 1
463 #define DC__ODM_MEM_PG__0 1
465 #define ODM__MEM_PG__0 1
467 #define DC__DSI_MEM_PG__0 1
469 #define DSI__MEM_PG__0 1
470 #define DC__AZ_MEM_PG 1
471 #define DC__AZ_MEM_PG__1 1
472 #define AZ__MEM_PG 1
473 #define AZ__MEM_PG__1 1
474 #define DC__WBSCL_MEM1P1024X64QS_MEM_PG 1
475 #define DC__WBSCL_MEM1P1024X64QS_MEM_PG__1 1
476 #define WBSCL_MEM1P1024X64QS__MEM_PG 1
477 #define WBSCL_MEM1P1024X64QS__MEM_PG__1 1
478 #define DC__WBSCL_MEM1P528X64QS_MEM_PG 1
479 #define DC__WBSCL_MEM1P528X64QS_MEM_PG__1 1
480 #define WBSCL_MEM1P528X64QS__MEM_PG 1
481 #define WBSCL_MEM1P528X64QS__MEM_PG__1 1
482 #define DC__DMCU_MEM1P1024X32BQS_MEM_PG 1
483 #define DC__DMCU_MEM1P1024X32BQS_MEM_PG__1 1
484 #define DMCU_MEM1P1024X32BQS__MEM_PG 1
485 #define DMCU_MEM1P1024X32BQS__MEM_PG__1 1
487 #define DC__HUBBUB_SDP_TAG_INT_MEM_PG__0 1
489 #define HUBBUB_SDP_TAG_INT__MEM_PG__0 1
491 #define DC__HUBBUB_SDP_TAG_EXT_MEM_PG__0 1
493 #define HUBBUB_SDP_TAG_EXT__MEM_PG__0 1
495 #define DC__HUBBUB_RET_ZERO_MEM_PG__0 1
497 #define HUBBUB_RET_ZERO__MEM_PG__0 1
499 #define DC__HUBBUB_RET_ROB_MEM_PG__0 1
501 #define HUBBUB_RET_ROB__MEM_PG__0 1
503 #define DC__HUBPRET_CUR_ROB_MEM_PG__0 1
505 #define HUBPRET_CUR_ROB__MEM_PG__0 1
507 #define DC__HUBPRET_CUR_CDC_MEM_PG__0 1
509 #define HUBPRET_CUR_CDC__MEM_PG__0 1
511 #define DC__HUBPREQ_MPTE_MEM_PG__0 1
513 #define HUBPREQ_MPTE__MEM_PG__0 1
515 #define DC__HUBPREQ_META_MEM_PG__0 1
517 #define HUBPREQ_META__MEM_PG__0 1
519 #define DC__HUBPREQ_DPTE_MEM_PG__0 1
521 #define HUBPREQ_DPTE__MEM_PG__0 1
523 #define DC__HUBPRET_DET_MEM_PG__0 1
525 #define HUBPRET_DET__MEM_PG__0 1
527 #define DC__HUBPRET_PIX_CDC_MEM_PG__0 1
529 #define HUBPRET_PIX_CDC__MEM_PG__0 1
530 #define DC__TOP_BLKS__DCCG 1
531 #define DC__TOP_BLKS__DCHUBBUB 1
532 #define DC__TOP_BLKS__DCHUBP 1
533 #define DC__TOP_BLKS__HDA 1
534 #define DC__TOP_BLKS__DIO 1
535 #define DC__TOP_BLKS__DCIO 1
536 #define DC__TOP_BLKS__DMU 1
537 #define DC__TOP_BLKS__DPP 1
538 #define DC__TOP_BLKS__MPC 1
539 #define DC__TOP_BLKS__OPP 1
540 #define DC__TOP_BLKS__OPTC 1
541 #define DC__TOP_BLKS__MMHUBBUB 1
542 #define DC__TOP_BLKS__WB 1
544 #define DC__TOP_BLKS__MAX__13 1
546 #define DC__DCHUBP_DPP_SF_PIXEL_CREDITS__9 1
548 #define DC__DPP_MPC_SF_PIXEL_CREDITS__9 1
550 #define DC__MPC_OPP_SF_PIXEL_CREDITS__8 1
552 #define DC__OPP_OPTC_SF_PIXEL_CREDITS__8 1
554 #define DC__SFR_SFT_ROUND_TRIP_DELAY__5 1
556 #define DC__REPEATER_PROJECT_MAX__8 1
558 #define DC__SURFACE_422_CAPABLE__0 1