Lines Matching full:pool
806 static void dce80_resource_destruct(struct dce110_resource_pool *pool) in dce80_resource_destruct() argument
810 for (i = 0; i < pool->base.pipe_count; i++) { in dce80_resource_destruct()
811 if (pool->base.opps[i] != NULL) in dce80_resource_destruct()
812 dce110_opp_destroy(&pool->base.opps[i]); in dce80_resource_destruct()
814 if (pool->base.transforms[i] != NULL) in dce80_resource_destruct()
815 dce80_transform_destroy(&pool->base.transforms[i]); in dce80_resource_destruct()
817 if (pool->base.ipps[i] != NULL) in dce80_resource_destruct()
818 dce_ipp_destroy(&pool->base.ipps[i]); in dce80_resource_destruct()
820 if (pool->base.mis[i] != NULL) { in dce80_resource_destruct()
821 kfree(TO_DCE_MEM_INPUT(pool->base.mis[i])); in dce80_resource_destruct()
822 pool->base.mis[i] = NULL; in dce80_resource_destruct()
825 if (pool->base.timing_generators[i] != NULL) { in dce80_resource_destruct()
826 kfree(DCE110TG_FROM_TG(pool->base.timing_generators[i])); in dce80_resource_destruct()
827 pool->base.timing_generators[i] = NULL; in dce80_resource_destruct()
831 for (i = 0; i < pool->base.res_cap->num_ddc; i++) { in dce80_resource_destruct()
832 if (pool->base.engines[i] != NULL) in dce80_resource_destruct()
833 dce110_engine_destroy(&pool->base.engines[i]); in dce80_resource_destruct()
834 if (pool->base.hw_i2cs[i] != NULL) { in dce80_resource_destruct()
835 kfree(pool->base.hw_i2cs[i]); in dce80_resource_destruct()
836 pool->base.hw_i2cs[i] = NULL; in dce80_resource_destruct()
838 if (pool->base.sw_i2cs[i] != NULL) { in dce80_resource_destruct()
839 kfree(pool->base.sw_i2cs[i]); in dce80_resource_destruct()
840 pool->base.sw_i2cs[i] = NULL; in dce80_resource_destruct()
844 for (i = 0; i < pool->base.stream_enc_count; i++) { in dce80_resource_destruct()
845 if (pool->base.stream_enc[i] != NULL) in dce80_resource_destruct()
846 kfree(DCE110STRENC_FROM_STRENC(pool->base.stream_enc[i])); in dce80_resource_destruct()
849 for (i = 0; i < pool->base.clk_src_count; i++) { in dce80_resource_destruct()
850 if (pool->base.clock_sources[i] != NULL) { in dce80_resource_destruct()
851 dce80_clock_source_destroy(&pool->base.clock_sources[i]); in dce80_resource_destruct()
855 if (pool->base.abm != NULL) in dce80_resource_destruct()
856 dce_abm_destroy(&pool->base.abm); in dce80_resource_destruct()
858 if (pool->base.dmcu != NULL) in dce80_resource_destruct()
859 dce_dmcu_destroy(&pool->base.dmcu); in dce80_resource_destruct()
861 if (pool->base.dp_clock_source != NULL) in dce80_resource_destruct()
862 dce80_clock_source_destroy(&pool->base.dp_clock_source); in dce80_resource_destruct()
864 for (i = 0; i < pool->base.audio_count; i++) { in dce80_resource_destruct()
865 if (pool->base.audios[i] != NULL) { in dce80_resource_destruct()
866 dce_aud_destroy(&pool->base.audios[i]); in dce80_resource_destruct()
870 if (pool->base.irqs != NULL) { in dce80_resource_destruct()
871 dal_irq_service_destroy(&pool->base.irqs); in dce80_resource_destruct()
930 static void dce80_destroy_resource_pool(struct resource_pool **pool) in dce80_destroy_resource_pool() argument
932 struct dce110_resource_pool *dce110_pool = TO_DCE110_RES_POOL(*pool); in dce80_destroy_resource_pool()
936 *pool = NULL; in dce80_destroy_resource_pool()
953 struct dce110_resource_pool *pool) in dce80_construct() argument
961 pool->base.res_cap = &res_cap; in dce80_construct()
962 pool->base.funcs = &dce80_res_pool_funcs; in dce80_construct()
968 pool->base.underlay_pipe_index = NO_UNDERLAY_PIPE; in dce80_construct()
969 pool->base.pipe_count = res_cap.num_timing_generator; in dce80_construct()
970 pool->base.timing_generator_count = res_cap.num_timing_generator; in dce80_construct()
984 pool->base.dp_clock_source = in dce80_construct()
987 pool->base.clock_sources[0] = in dce80_construct()
989 pool->base.clock_sources[1] = in dce80_construct()
991 pool->base.clock_sources[2] = in dce80_construct()
993 pool->base.clk_src_count = 3; in dce80_construct()
996 pool->base.dp_clock_source = in dce80_construct()
999 pool->base.clock_sources[0] = in dce80_construct()
1001 pool->base.clock_sources[1] = in dce80_construct()
1003 pool->base.clk_src_count = 2; in dce80_construct()
1006 if (pool->base.dp_clock_source == NULL) { in dce80_construct()
1012 for (i = 0; i < pool->base.clk_src_count; i++) { in dce80_construct()
1013 if (pool->base.clock_sources[i] == NULL) { in dce80_construct()
1020 pool->base.dmcu = dce_dmcu_create(ctx, in dce80_construct()
1024 if (pool->base.dmcu == NULL) { in dce80_construct()
1030 pool->base.abm = dce_abm_create(ctx, in dce80_construct()
1034 if (pool->base.abm == NULL) { in dce80_construct()
1043 pool->base.irqs = dal_irq_service_dce80_create(&init_data); in dce80_construct()
1044 if (!pool->base.irqs) in dce80_construct()
1048 for (i = 0; i < pool->base.pipe_count; i++) { in dce80_construct()
1049 pool->base.timing_generators[i] = dce80_timing_generator_create( in dce80_construct()
1051 if (pool->base.timing_generators[i] == NULL) { in dce80_construct()
1057 pool->base.mis[i] = dce80_mem_input_create(ctx, i); in dce80_construct()
1058 if (pool->base.mis[i] == NULL) { in dce80_construct()
1064 pool->base.ipps[i] = dce80_ipp_create(ctx, i); in dce80_construct()
1065 if (pool->base.ipps[i] == NULL) { in dce80_construct()
1071 pool->base.transforms[i] = dce80_transform_create(ctx, i); in dce80_construct()
1072 if (pool->base.transforms[i] == NULL) { in dce80_construct()
1078 pool->base.opps[i] = dce80_opp_create(ctx, i); in dce80_construct()
1079 if (pool->base.opps[i] == NULL) { in dce80_construct()
1086 for (i = 0; i < pool->base.res_cap->num_ddc; i++) { in dce80_construct()
1087 pool->base.engines[i] = dce80_aux_engine_create(ctx, i); in dce80_construct()
1088 if (pool->base.engines[i] == NULL) { in dce80_construct()
1094 pool->base.hw_i2cs[i] = dce80_i2c_hw_create(ctx, i); in dce80_construct()
1095 if (pool->base.hw_i2cs[i] == NULL) { in dce80_construct()
1101 pool->base.sw_i2cs[i] = dce80_i2c_sw_create(ctx); in dce80_construct()
1102 if (pool->base.sw_i2cs[i] == NULL) { in dce80_construct()
1110 dc->caps.max_planes = pool->base.pipe_count; in dce80_construct()
1117 if (!resource_construct(num_virtual_links, dc, &pool->base, in dce80_construct()
1127 dce80_resource_destruct(pool); in dce80_construct()
1135 struct dce110_resource_pool *pool = in dce80_create_resource_pool() local
1138 if (!pool) in dce80_create_resource_pool()
1141 if (dce80_construct(num_virtual_links, dc, pool)) in dce80_create_resource_pool()
1142 return &pool->base; in dce80_create_resource_pool()
1151 struct dce110_resource_pool *pool) in dce81_construct() argument
1159 pool->base.res_cap = &res_cap_81; in dce81_construct()
1160 pool->base.funcs = &dce80_res_pool_funcs; in dce81_construct()
1166 pool->base.underlay_pipe_index = NO_UNDERLAY_PIPE; in dce81_construct()
1167 pool->base.pipe_count = res_cap_81.num_timing_generator; in dce81_construct()
1168 pool->base.timing_generator_count = res_cap_81.num_timing_generator; in dce81_construct()
1181 pool->base.dp_clock_source = in dce81_construct()
1184 pool->base.clock_sources[0] = in dce81_construct()
1186 pool->base.clock_sources[1] = in dce81_construct()
1188 pool->base.clock_sources[2] = in dce81_construct()
1190 pool->base.clk_src_count = 3; in dce81_construct()
1193 pool->base.dp_clock_source = in dce81_construct()
1196 pool->base.clock_sources[0] = in dce81_construct()
1198 pool->base.clock_sources[1] = in dce81_construct()
1200 pool->base.clk_src_count = 2; in dce81_construct()
1203 if (pool->base.dp_clock_source == NULL) { in dce81_construct()
1209 for (i = 0; i < pool->base.clk_src_count; i++) { in dce81_construct()
1210 if (pool->base.clock_sources[i] == NULL) { in dce81_construct()
1217 pool->base.dmcu = dce_dmcu_create(ctx, in dce81_construct()
1221 if (pool->base.dmcu == NULL) { in dce81_construct()
1227 pool->base.abm = dce_abm_create(ctx, in dce81_construct()
1231 if (pool->base.abm == NULL) { in dce81_construct()
1240 pool->base.irqs = dal_irq_service_dce80_create(&init_data); in dce81_construct()
1241 if (!pool->base.irqs) in dce81_construct()
1245 for (i = 0; i < pool->base.pipe_count; i++) { in dce81_construct()
1246 pool->base.timing_generators[i] = dce80_timing_generator_create( in dce81_construct()
1248 if (pool->base.timing_generators[i] == NULL) { in dce81_construct()
1254 pool->base.mis[i] = dce80_mem_input_create(ctx, i); in dce81_construct()
1255 if (pool->base.mis[i] == NULL) { in dce81_construct()
1261 pool->base.ipps[i] = dce80_ipp_create(ctx, i); in dce81_construct()
1262 if (pool->base.ipps[i] == NULL) { in dce81_construct()
1268 pool->base.transforms[i] = dce80_transform_create(ctx, i); in dce81_construct()
1269 if (pool->base.transforms[i] == NULL) { in dce81_construct()
1275 pool->base.opps[i] = dce80_opp_create(ctx, i); in dce81_construct()
1276 if (pool->base.opps[i] == NULL) { in dce81_construct()
1283 for (i = 0; i < pool->base.res_cap->num_ddc; i++) { in dce81_construct()
1284 pool->base.engines[i] = dce80_aux_engine_create(ctx, i); in dce81_construct()
1285 if (pool->base.engines[i] == NULL) { in dce81_construct()
1291 pool->base.hw_i2cs[i] = dce80_i2c_hw_create(ctx, i); in dce81_construct()
1292 if (pool->base.hw_i2cs[i] == NULL) { in dce81_construct()
1298 pool->base.sw_i2cs[i] = dce80_i2c_sw_create(ctx); in dce81_construct()
1299 if (pool->base.sw_i2cs[i] == NULL) { in dce81_construct()
1307 dc->caps.max_planes = pool->base.pipe_count; in dce81_construct()
1314 if (!resource_construct(num_virtual_links, dc, &pool->base, in dce81_construct()
1324 dce80_resource_destruct(pool); in dce81_construct()
1332 struct dce110_resource_pool *pool = in dce81_create_resource_pool() local
1335 if (!pool) in dce81_create_resource_pool()
1338 if (dce81_construct(num_virtual_links, dc, pool)) in dce81_create_resource_pool()
1339 return &pool->base; in dce81_create_resource_pool()
1348 struct dce110_resource_pool *pool) in dce83_construct() argument
1356 pool->base.res_cap = &res_cap_83; in dce83_construct()
1357 pool->base.funcs = &dce80_res_pool_funcs; in dce83_construct()
1363 pool->base.underlay_pipe_index = NO_UNDERLAY_PIPE; in dce83_construct()
1364 pool->base.pipe_count = res_cap_83.num_timing_generator; in dce83_construct()
1365 pool->base.timing_generator_count = res_cap_83.num_timing_generator; in dce83_construct()
1378 pool->base.dp_clock_source = in dce83_construct()
1381 pool->base.clock_sources[0] = in dce83_construct()
1383 pool->base.clock_sources[1] = in dce83_construct()
1385 pool->base.clk_src_count = 2; in dce83_construct()
1388 pool->base.dp_clock_source = in dce83_construct()
1391 pool->base.clock_sources[0] = in dce83_construct()
1393 pool->base.clk_src_count = 1; in dce83_construct()
1396 if (pool->base.dp_clock_source == NULL) { in dce83_construct()
1402 for (i = 0; i < pool->base.clk_src_count; i++) { in dce83_construct()
1403 if (pool->base.clock_sources[i] == NULL) { in dce83_construct()
1410 pool->base.dmcu = dce_dmcu_create(ctx, in dce83_construct()
1414 if (pool->base.dmcu == NULL) { in dce83_construct()
1420 pool->base.abm = dce_abm_create(ctx, in dce83_construct()
1424 if (pool->base.abm == NULL) { in dce83_construct()
1433 pool->base.irqs = dal_irq_service_dce80_create(&init_data); in dce83_construct()
1434 if (!pool->base.irqs) in dce83_construct()
1438 for (i = 0; i < pool->base.pipe_count; i++) { in dce83_construct()
1439 pool->base.timing_generators[i] = dce80_timing_generator_create( in dce83_construct()
1441 if (pool->base.timing_generators[i] == NULL) { in dce83_construct()
1447 pool->base.mis[i] = dce80_mem_input_create(ctx, i); in dce83_construct()
1448 if (pool->base.mis[i] == NULL) { in dce83_construct()
1454 pool->base.ipps[i] = dce80_ipp_create(ctx, i); in dce83_construct()
1455 if (pool->base.ipps[i] == NULL) { in dce83_construct()
1461 pool->base.transforms[i] = dce80_transform_create(ctx, i); in dce83_construct()
1462 if (pool->base.transforms[i] == NULL) { in dce83_construct()
1468 pool->base.opps[i] = dce80_opp_create(ctx, i); in dce83_construct()
1469 if (pool->base.opps[i] == NULL) { in dce83_construct()
1476 for (i = 0; i < pool->base.res_cap->num_ddc; i++) { in dce83_construct()
1477 pool->base.engines[i] = dce80_aux_engine_create(ctx, i); in dce83_construct()
1478 if (pool->base.engines[i] == NULL) { in dce83_construct()
1484 pool->base.hw_i2cs[i] = dce80_i2c_hw_create(ctx, i); in dce83_construct()
1485 if (pool->base.hw_i2cs[i] == NULL) { in dce83_construct()
1491 pool->base.sw_i2cs[i] = dce80_i2c_sw_create(ctx); in dce83_construct()
1492 if (pool->base.sw_i2cs[i] == NULL) { in dce83_construct()
1500 dc->caps.max_planes = pool->base.pipe_count; in dce83_construct()
1507 if (!resource_construct(num_virtual_links, dc, &pool->base, in dce83_construct()
1517 dce80_resource_destruct(pool); in dce83_construct()
1525 struct dce110_resource_pool *pool = in dce83_create_resource_pool() local
1528 if (!pool) in dce83_create_resource_pool()
1531 if (dce83_construct(num_virtual_links, dc, pool)) in dce83_create_resource_pool()
1532 return &pool->base; in dce83_create_resource_pool()