Lines Matching full:pool
801 static void dce60_resource_destruct(struct dce110_resource_pool *pool) in dce60_resource_destruct() argument
805 for (i = 0; i < pool->base.pipe_count; i++) { in dce60_resource_destruct()
806 if (pool->base.opps[i] != NULL) in dce60_resource_destruct()
807 dce110_opp_destroy(&pool->base.opps[i]); in dce60_resource_destruct()
809 if (pool->base.transforms[i] != NULL) in dce60_resource_destruct()
810 dce60_transform_destroy(&pool->base.transforms[i]); in dce60_resource_destruct()
812 if (pool->base.ipps[i] != NULL) in dce60_resource_destruct()
813 dce_ipp_destroy(&pool->base.ipps[i]); in dce60_resource_destruct()
815 if (pool->base.mis[i] != NULL) { in dce60_resource_destruct()
816 kfree(TO_DCE_MEM_INPUT(pool->base.mis[i])); in dce60_resource_destruct()
817 pool->base.mis[i] = NULL; in dce60_resource_destruct()
820 if (pool->base.timing_generators[i] != NULL) { in dce60_resource_destruct()
821 kfree(DCE110TG_FROM_TG(pool->base.timing_generators[i])); in dce60_resource_destruct()
822 pool->base.timing_generators[i] = NULL; in dce60_resource_destruct()
826 for (i = 0; i < pool->base.res_cap->num_ddc; i++) { in dce60_resource_destruct()
827 if (pool->base.engines[i] != NULL) in dce60_resource_destruct()
828 dce110_engine_destroy(&pool->base.engines[i]); in dce60_resource_destruct()
829 if (pool->base.hw_i2cs[i] != NULL) { in dce60_resource_destruct()
830 kfree(pool->base.hw_i2cs[i]); in dce60_resource_destruct()
831 pool->base.hw_i2cs[i] = NULL; in dce60_resource_destruct()
833 if (pool->base.sw_i2cs[i] != NULL) { in dce60_resource_destruct()
834 kfree(pool->base.sw_i2cs[i]); in dce60_resource_destruct()
835 pool->base.sw_i2cs[i] = NULL; in dce60_resource_destruct()
839 for (i = 0; i < pool->base.stream_enc_count; i++) { in dce60_resource_destruct()
840 if (pool->base.stream_enc[i] != NULL) in dce60_resource_destruct()
841 kfree(DCE110STRENC_FROM_STRENC(pool->base.stream_enc[i])); in dce60_resource_destruct()
844 for (i = 0; i < pool->base.clk_src_count; i++) { in dce60_resource_destruct()
845 if (pool->base.clock_sources[i] != NULL) { in dce60_resource_destruct()
846 dce60_clock_source_destroy(&pool->base.clock_sources[i]); in dce60_resource_destruct()
850 if (pool->base.abm != NULL) in dce60_resource_destruct()
851 dce_abm_destroy(&pool->base.abm); in dce60_resource_destruct()
853 if (pool->base.dmcu != NULL) in dce60_resource_destruct()
854 dce_dmcu_destroy(&pool->base.dmcu); in dce60_resource_destruct()
856 if (pool->base.dp_clock_source != NULL) in dce60_resource_destruct()
857 dce60_clock_source_destroy(&pool->base.dp_clock_source); in dce60_resource_destruct()
859 for (i = 0; i < pool->base.audio_count; i++) { in dce60_resource_destruct()
860 if (pool->base.audios[i] != NULL) { in dce60_resource_destruct()
861 dce_aud_destroy(&pool->base.audios[i]); in dce60_resource_destruct()
865 if (pool->base.irqs != NULL) { in dce60_resource_destruct()
866 dal_irq_service_destroy(&pool->base.irqs); in dce60_resource_destruct()
925 static void dce60_destroy_resource_pool(struct resource_pool **pool) in dce60_destroy_resource_pool() argument
927 struct dce110_resource_pool *dce110_pool = TO_DCE110_RES_POOL(*pool); in dce60_destroy_resource_pool()
931 *pool = NULL; in dce60_destroy_resource_pool()
948 struct dce110_resource_pool *pool) in dce60_construct() argument
956 pool->base.res_cap = &res_cap; in dce60_construct()
957 pool->base.funcs = &dce60_res_pool_funcs; in dce60_construct()
963 pool->base.underlay_pipe_index = NO_UNDERLAY_PIPE; in dce60_construct()
964 pool->base.pipe_count = res_cap.num_timing_generator; in dce60_construct()
965 pool->base.timing_generator_count = res_cap.num_timing_generator; in dce60_construct()
979 pool->base.dp_clock_source = in dce60_construct()
982 pool->base.clock_sources[0] = in dce60_construct()
984 pool->base.clock_sources[1] = in dce60_construct()
986 pool->base.clk_src_count = 2; in dce60_construct()
989 pool->base.dp_clock_source = in dce60_construct()
992 pool->base.clock_sources[0] = in dce60_construct()
994 pool->base.clk_src_count = 1; in dce60_construct()
997 if (pool->base.dp_clock_source == NULL) { in dce60_construct()
1003 for (i = 0; i < pool->base.clk_src_count; i++) { in dce60_construct()
1004 if (pool->base.clock_sources[i] == NULL) { in dce60_construct()
1011 pool->base.dmcu = dce_dmcu_create(ctx, in dce60_construct()
1015 if (pool->base.dmcu == NULL) { in dce60_construct()
1021 pool->base.abm = dce_abm_create(ctx, in dce60_construct()
1025 if (pool->base.abm == NULL) { in dce60_construct()
1034 pool->base.irqs = dal_irq_service_dce60_create(&init_data); in dce60_construct()
1035 if (!pool->base.irqs) in dce60_construct()
1039 for (i = 0; i < pool->base.pipe_count; i++) { in dce60_construct()
1040 pool->base.timing_generators[i] = dce60_timing_generator_create( in dce60_construct()
1042 if (pool->base.timing_generators[i] == NULL) { in dce60_construct()
1048 pool->base.mis[i] = dce60_mem_input_create(ctx, i); in dce60_construct()
1049 if (pool->base.mis[i] == NULL) { in dce60_construct()
1055 pool->base.ipps[i] = dce60_ipp_create(ctx, i); in dce60_construct()
1056 if (pool->base.ipps[i] == NULL) { in dce60_construct()
1062 pool->base.transforms[i] = dce60_transform_create(ctx, i); in dce60_construct()
1063 if (pool->base.transforms[i] == NULL) { in dce60_construct()
1069 pool->base.opps[i] = dce60_opp_create(ctx, i); in dce60_construct()
1070 if (pool->base.opps[i] == NULL) { in dce60_construct()
1077 for (i = 0; i < pool->base.res_cap->num_ddc; i++) { in dce60_construct()
1078 pool->base.engines[i] = dce60_aux_engine_create(ctx, i); in dce60_construct()
1079 if (pool->base.engines[i] == NULL) { in dce60_construct()
1085 pool->base.hw_i2cs[i] = dce60_i2c_hw_create(ctx, i); in dce60_construct()
1086 if (pool->base.hw_i2cs[i] == NULL) { in dce60_construct()
1092 pool->base.sw_i2cs[i] = dce60_i2c_sw_create(ctx); in dce60_construct()
1093 if (pool->base.sw_i2cs[i] == NULL) { in dce60_construct()
1101 dc->caps.max_planes = pool->base.pipe_count; in dce60_construct()
1108 if (!resource_construct(num_virtual_links, dc, &pool->base, in dce60_construct()
1118 dce60_resource_destruct(pool); in dce60_construct()
1126 struct dce110_resource_pool *pool = in dce60_create_resource_pool() local
1129 if (!pool) in dce60_create_resource_pool()
1132 if (dce60_construct(num_virtual_links, dc, pool)) in dce60_create_resource_pool()
1133 return &pool->base; in dce60_create_resource_pool()
1142 struct dce110_resource_pool *pool) in dce61_construct() argument
1150 pool->base.res_cap = &res_cap_61; in dce61_construct()
1151 pool->base.funcs = &dce60_res_pool_funcs; in dce61_construct()
1157 pool->base.underlay_pipe_index = NO_UNDERLAY_PIPE; in dce61_construct()
1158 pool->base.pipe_count = res_cap_61.num_timing_generator; in dce61_construct()
1159 pool->base.timing_generator_count = res_cap_61.num_timing_generator; in dce61_construct()
1172 pool->base.dp_clock_source = in dce61_construct()
1175 pool->base.clock_sources[0] = in dce61_construct()
1177 pool->base.clock_sources[1] = in dce61_construct()
1179 pool->base.clock_sources[2] = in dce61_construct()
1181 pool->base.clk_src_count = 3; in dce61_construct()
1184 pool->base.dp_clock_source = in dce61_construct()
1187 pool->base.clock_sources[0] = in dce61_construct()
1189 pool->base.clock_sources[1] = in dce61_construct()
1191 pool->base.clk_src_count = 2; in dce61_construct()
1194 if (pool->base.dp_clock_source == NULL) { in dce61_construct()
1200 for (i = 0; i < pool->base.clk_src_count; i++) { in dce61_construct()
1201 if (pool->base.clock_sources[i] == NULL) { in dce61_construct()
1208 pool->base.dmcu = dce_dmcu_create(ctx, in dce61_construct()
1212 if (pool->base.dmcu == NULL) { in dce61_construct()
1218 pool->base.abm = dce_abm_create(ctx, in dce61_construct()
1222 if (pool->base.abm == NULL) { in dce61_construct()
1231 pool->base.irqs = dal_irq_service_dce60_create(&init_data); in dce61_construct()
1232 if (!pool->base.irqs) in dce61_construct()
1236 for (i = 0; i < pool->base.pipe_count; i++) { in dce61_construct()
1237 pool->base.timing_generators[i] = dce60_timing_generator_create( in dce61_construct()
1239 if (pool->base.timing_generators[i] == NULL) { in dce61_construct()
1245 pool->base.mis[i] = dce60_mem_input_create(ctx, i); in dce61_construct()
1246 if (pool->base.mis[i] == NULL) { in dce61_construct()
1252 pool->base.ipps[i] = dce60_ipp_create(ctx, i); in dce61_construct()
1253 if (pool->base.ipps[i] == NULL) { in dce61_construct()
1259 pool->base.transforms[i] = dce60_transform_create(ctx, i); in dce61_construct()
1260 if (pool->base.transforms[i] == NULL) { in dce61_construct()
1266 pool->base.opps[i] = dce60_opp_create(ctx, i); in dce61_construct()
1267 if (pool->base.opps[i] == NULL) { in dce61_construct()
1274 for (i = 0; i < pool->base.res_cap->num_ddc; i++) { in dce61_construct()
1275 pool->base.engines[i] = dce60_aux_engine_create(ctx, i); in dce61_construct()
1276 if (pool->base.engines[i] == NULL) { in dce61_construct()
1282 pool->base.hw_i2cs[i] = dce60_i2c_hw_create(ctx, i); in dce61_construct()
1283 if (pool->base.hw_i2cs[i] == NULL) { in dce61_construct()
1289 pool->base.sw_i2cs[i] = dce60_i2c_sw_create(ctx); in dce61_construct()
1290 if (pool->base.sw_i2cs[i] == NULL) { in dce61_construct()
1298 dc->caps.max_planes = pool->base.pipe_count; in dce61_construct()
1305 if (!resource_construct(num_virtual_links, dc, &pool->base, in dce61_construct()
1315 dce60_resource_destruct(pool); in dce61_construct()
1323 struct dce110_resource_pool *pool = in dce61_create_resource_pool() local
1326 if (!pool) in dce61_create_resource_pool()
1329 if (dce61_construct(num_virtual_links, dc, pool)) in dce61_create_resource_pool()
1330 return &pool->base; in dce61_create_resource_pool()
1339 struct dce110_resource_pool *pool) in dce64_construct() argument
1347 pool->base.res_cap = &res_cap_64; in dce64_construct()
1348 pool->base.funcs = &dce60_res_pool_funcs; in dce64_construct()
1354 pool->base.underlay_pipe_index = NO_UNDERLAY_PIPE; in dce64_construct()
1355 pool->base.pipe_count = res_cap_64.num_timing_generator; in dce64_construct()
1356 pool->base.timing_generator_count = res_cap_64.num_timing_generator; in dce64_construct()
1369 pool->base.dp_clock_source = in dce64_construct()
1372 pool->base.clock_sources[0] = in dce64_construct()
1374 pool->base.clock_sources[1] = in dce64_construct()
1376 pool->base.clk_src_count = 2; in dce64_construct()
1379 pool->base.dp_clock_source = in dce64_construct()
1382 pool->base.clock_sources[0] = in dce64_construct()
1384 pool->base.clk_src_count = 1; in dce64_construct()
1387 if (pool->base.dp_clock_source == NULL) { in dce64_construct()
1393 for (i = 0; i < pool->base.clk_src_count; i++) { in dce64_construct()
1394 if (pool->base.clock_sources[i] == NULL) { in dce64_construct()
1401 pool->base.dmcu = dce_dmcu_create(ctx, in dce64_construct()
1405 if (pool->base.dmcu == NULL) { in dce64_construct()
1411 pool->base.abm = dce_abm_create(ctx, in dce64_construct()
1415 if (pool->base.abm == NULL) { in dce64_construct()
1424 pool->base.irqs = dal_irq_service_dce60_create(&init_data); in dce64_construct()
1425 if (!pool->base.irqs) in dce64_construct()
1429 for (i = 0; i < pool->base.pipe_count; i++) { in dce64_construct()
1430 pool->base.timing_generators[i] = dce60_timing_generator_create( in dce64_construct()
1432 if (pool->base.timing_generators[i] == NULL) { in dce64_construct()
1438 pool->base.mis[i] = dce60_mem_input_create(ctx, i); in dce64_construct()
1439 if (pool->base.mis[i] == NULL) { in dce64_construct()
1445 pool->base.ipps[i] = dce60_ipp_create(ctx, i); in dce64_construct()
1446 if (pool->base.ipps[i] == NULL) { in dce64_construct()
1452 pool->base.transforms[i] = dce60_transform_create(ctx, i); in dce64_construct()
1453 if (pool->base.transforms[i] == NULL) { in dce64_construct()
1459 pool->base.opps[i] = dce60_opp_create(ctx, i); in dce64_construct()
1460 if (pool->base.opps[i] == NULL) { in dce64_construct()
1467 for (i = 0; i < pool->base.res_cap->num_ddc; i++) { in dce64_construct()
1468 pool->base.engines[i] = dce60_aux_engine_create(ctx, i); in dce64_construct()
1469 if (pool->base.engines[i] == NULL) { in dce64_construct()
1475 pool->base.hw_i2cs[i] = dce60_i2c_hw_create(ctx, i); in dce64_construct()
1476 if (pool->base.hw_i2cs[i] == NULL) { in dce64_construct()
1482 pool->base.sw_i2cs[i] = dce60_i2c_sw_create(ctx); in dce64_construct()
1483 if (pool->base.sw_i2cs[i] == NULL) { in dce64_construct()
1491 dc->caps.max_planes = pool->base.pipe_count; in dce64_construct()
1498 if (!resource_construct(num_virtual_links, dc, &pool->base, in dce64_construct()
1508 dce60_resource_destruct(pool); in dce64_construct()
1516 struct dce110_resource_pool *pool = in dce64_create_resource_pool() local
1519 if (!pool) in dce64_create_resource_pool()
1522 if (dce64_construct(num_virtual_links, dc, pool)) in dce64_create_resource_pool()
1523 return &pool->base; in dce64_create_resource_pool()