Lines Matching defs:dc_debug_options
415 struct dc_debug_options { struct
416 enum visual_confirm visual_confirm;
417 bool sanity_checks;
418 bool max_disp_clk;
419 bool surface_trace;
420 bool timing_trace;
421 bool clock_trace;
422 bool validation_trace;
423 bool bandwidth_calcs_trace;
424 int max_downscale_src_width;
427 bool disable_stutter;
428 bool use_max_lb;
429 enum dcc_option disable_dcc;
430 enum pipe_split_policy pipe_split_policy;
431 bool force_single_disp_pipe_split;
432 bool voltage_align_fclk;
434 bool disable_dfs_bypass;
435 bool disable_dpp_power_gate;
436 bool disable_hubp_power_gate;
437 bool disable_dsc_power_gate;
438 int dsc_min_slice_height_override;
439 int dsc_bpp_increment_div;
440 bool native422_support;
441 bool disable_pplib_wm_range;
442 enum wm_report_mode pplib_wm_report_mode;
443 unsigned int min_disp_clk_khz;
444 unsigned int min_dpp_clk_khz;
445 int sr_exit_time_dpm0_ns;
446 int sr_enter_plus_exit_time_dpm0_ns;
447 int sr_exit_time_ns;
448 int sr_enter_plus_exit_time_ns;
449 int urgent_latency_ns;
450 uint32_t underflow_assert_delay_us;
451 int percent_of_ideal_drambw;
452 int dram_clock_change_latency_ns;
453 bool optimized_watermark;
454 int always_scale;
455 bool disable_pplib_clock_request;
456 bool disable_clock_gate;
457 bool disable_mem_low_power;
458 bool disable_dmcu;
459 bool disable_psr;
460 bool force_abm_enable;
461 bool disable_stereo_support;
462 bool vsr_support;
463 bool performance_trace;
464 bool az_endpoint_mute_only;
465 bool always_use_regamma;
466 bool p010_mpo_support;
467 bool recovery_enabled;
468 bool avoid_vbios_exec_table;
469 bool scl_reset_length10;
470 bool hdmi20_disable;
471 bool skip_detection_link_training;
472 bool edid_read_retry_times;
473 bool remove_disconnect_edp;
474 unsigned int force_odm_combine; //bit vector based on otg inst
476 unsigned int force_odm_combine_4to1; //bit vector based on otg inst
478 unsigned int force_fclk_khz;
479 bool enable_tri_buf;
480 bool dmub_offload_enabled;
481 bool dmcub_emulation;
483 bool disable_idle_power_optimizations;
485 bool dmub_command_table; /* for testing only */
486 struct dc_bw_validation_profile bw_val_profile;
487 bool disable_fec;
488 bool disable_48mhz_pwrdwn;
492 unsigned int force_min_dcfclk_mhz;
494 int dwb_fi_phase;
496 bool disable_timing_sync;
497 bool cm_in_bypass;
498 int force_clock_mode;/*every mode change.*/
500 bool disable_dram_clock_change_vactive_support;
501 bool validate_dml_output;
502 bool enable_dmcub_surface_flip;
503 bool usbc_combo_phy_reset_wa;
504 bool disable_dsc;
505 bool enable_dram_clock_change_one_display_vactive;
506 bool force_ignore_link_settings;