Lines Matching +full:2 +full:v
45 #define WM_C 2
111 .number_of_channels = 2,
132 .pte_chunk_size = 2, /*kbytes*/
133 .meta_chunk_size = 2, /*kbytes*/
134 .writeback_chunk_size = 2, /*kbytes*/
144 .max_num_writeback = 2,
146 .max_pscl_tolb_throughput = 2, /*pixels/dppclk*/
270 /* For 64bpp 2 high tiles */ in swizzle_mode_to_macro_tile_size()
368 input->src.viewport_width_c = input->src.viewport_width / 2; in pipe_ctx_to_e2e_pipe_params()
369 input->src.viewport_height_c = input->src.viewport_height / 2; in pipe_ctx_to_e2e_pipe_params()
374 input->src.viewport_width_c = input->src.viewport_width / 2; in pipe_ctx_to_e2e_pipe_params()
375 input->src.viewport_height_c = input->src.viewport_height / 2; in pipe_ctx_to_e2e_pipe_params()
401 input->scale_ratio_depth.vinit = pipe->plane_res.scl_data.inits.v.value/4294967296.0; in pipe_ctx_to_e2e_pipe_params()
454 const struct dcn_bw_internal_vars *v, in dcn_bw_calc_rq_dlg_ttu() argument
475 total_active_bw += v->read_bandwidth[i]; in dcn_bw_calc_rq_dlg_ttu()
476 total_prefetch_bw += v->prefetch_bandwidth[i]; in dcn_bw_calc_rq_dlg_ttu()
477 total_flip_bytes += v->total_immediate_flip_bytes[i]; in dcn_bw_calc_rq_dlg_ttu()
479 dlg_sys_param.total_flip_bw = v->return_bw - dcn_bw_max2(total_active_bw, total_prefetch_bw); in dcn_bw_calc_rq_dlg_ttu()
483 dlg_sys_param.t_mclk_wm_us = v->dram_clock_change_watermark; in dcn_bw_calc_rq_dlg_ttu()
484 dlg_sys_param.t_sr_wm_us = v->stutter_enter_plus_exit_watermark; in dcn_bw_calc_rq_dlg_ttu()
485 dlg_sys_param.t_urg_wm_us = v->urgent_watermark; in dcn_bw_calc_rq_dlg_ttu()
486 dlg_sys_param.t_extra_us = v->urgent_extra_latency; in dcn_bw_calc_rq_dlg_ttu()
487 dlg_sys_param.deepsleep_dcfclk_mhz = v->dcf_clk_deep_sleep; in dcn_bw_calc_rq_dlg_ttu()
491 input.clks_cfg.dcfclk_mhz = v->dcfclk; in dcn_bw_calc_rq_dlg_ttu()
492 input.clks_cfg.dispclk_mhz = v->dispclk; in dcn_bw_calc_rq_dlg_ttu()
493 input.clks_cfg.dppclk_mhz = v->dppclk; in dcn_bw_calc_rq_dlg_ttu()
495 input.clks_cfg.socclk_mhz = v->socclk; in dcn_bw_calc_rq_dlg_ttu()
496 input.clks_cfg.voltage = v->voltage_level; in dcn_bw_calc_rq_dlg_ttu()
498 input.dout.output_format = (v->output_format[in_idx] == dcn_bw_420) ? dm_420 : dm_444; in dcn_bw_calc_rq_dlg_ttu()
499 input.dout.output_type = (v->output[in_idx] == dcn_bw_hdmi) ? dm_hdmi : dm_dp; in dcn_bw_calc_rq_dlg_ttu()
503 dlg_sys_param.t_srx_delay_us = dc->dcn_ip->dcfclk_cstate_latency / v->dcf_clk_deep_sleep; in dcn_bw_calc_rq_dlg_ttu()
516 v->pte_enable == dcn_bw_yes, in dcn_bw_calc_rq_dlg_ttu()
555 struct dcn_bw_internal_vars *v)
558 if (v->voltage_level < 2) {
559 v->fabric_and_dram_bandwidth_per_state[1] = v->fabric_and_dram_bandwidth_vnom0p8;
560 v->fabric_and_dram_bandwidth_per_state[0] = v->fabric_and_dram_bandwidth_vnom0p8;
561 v->fabric_and_dram_bandwidth = v->fabric_and_dram_bandwidth_vnom0p8;
562 dispclkdppclkdcfclk_deep_sleep_prefetch_parameters_watermarks_and_performance_calculation(v);
565 v->stutter_exit_watermark * 1000;
567 v->stutter_enter_plus_exit_watermark * 1000;
569 v->dram_clock_change_watermark * 1000;
570 context->bw_ctx.bw.dcn.watermarks.b.pte_meta_urgent_ns = v->ptemeta_urgent_watermark * 1000;
571 context->bw_ctx.bw.dcn.watermarks.b.urgent_ns = v->urgent_watermark * 1000;
573 v->dcfclk_per_state[1] = v->dcfclkv_nom0p8;
574 v->dcfclk_per_state[0] = v->dcfclkv_nom0p8;
575 v->dcfclk = v->dcfclkv_nom0p8;
576 dispclkdppclkdcfclk_deep_sleep_prefetch_parameters_watermarks_and_performance_calculation(v);
579 v->stutter_exit_watermark * 1000;
581 v->stutter_enter_plus_exit_watermark * 1000;
583 v->dram_clock_change_watermark * 1000;
584 context->bw_ctx.bw.dcn.watermarks.c.pte_meta_urgent_ns = v->ptemeta_urgent_watermark * 1000;
585 context->bw_ctx.bw.dcn.watermarks.c.urgent_ns = v->urgent_watermark * 1000;
588 if (v->voltage_level < 3) {
589 v->fabric_and_dram_bandwidth_per_state[2] = v->fabric_and_dram_bandwidth_vmax0p9;
590 v->fabric_and_dram_bandwidth_per_state[1] = v->fabric_and_dram_bandwidth_vmax0p9;
591 v->fabric_and_dram_bandwidth_per_state[0] = v->fabric_and_dram_bandwidth_vmax0p9;
592 v->fabric_and_dram_bandwidth = v->fabric_and_dram_bandwidth_vmax0p9;
593 v->dcfclk_per_state[2] = v->dcfclkv_max0p9;
594 v->dcfclk_per_state[1] = v->dcfclkv_max0p9;
595 v->dcfclk_per_state[0] = v->dcfclkv_max0p9;
596 v->dcfclk = v->dcfclkv_max0p9;
597 dispclkdppclkdcfclk_deep_sleep_prefetch_parameters_watermarks_and_performance_calculation(v);
600 v->stutter_exit_watermark * 1000;
602 v->stutter_enter_plus_exit_watermark * 1000;
604 v->dram_clock_change_watermark * 1000;
605 context->bw_ctx.bw.dcn.watermarks.d.pte_meta_urgent_ns = v->ptemeta_urgent_watermark * 1000;
606 context->bw_ctx.bw.dcn.watermarks.d.urgent_ns = v->urgent_watermark * 1000;
609 v->fabric_and_dram_bandwidth_per_state[2] = v->fabric_and_dram_bandwidth_vnom0p8;
610 v->fabric_and_dram_bandwidth_per_state[1] = v->fabric_and_dram_bandwidth_vmid0p72;
611 v->fabric_and_dram_bandwidth_per_state[0] = v->fabric_and_dram_bandwidth_vmin0p65;
612 v->fabric_and_dram_bandwidth = v->fabric_and_dram_bandwidth_per_state[v->voltage_level];
613 v->dcfclk_per_state[2] = v->dcfclkv_nom0p8;
614 v->dcfclk_per_state[1] = v->dcfclkv_mid0p72;
615 v->dcfclk_per_state[0] = v->dcfclkv_min0p65;
616 v->dcfclk = v->dcfclk_per_state[v->voltage_level];
617 dispclkdppclkdcfclk_deep_sleep_prefetch_parameters_watermarks_and_performance_calculation(v);
620 v->stutter_exit_watermark * 1000;
622 v->stutter_enter_plus_exit_watermark * 1000;
624 v->dram_clock_change_watermark * 1000;
625 context->bw_ctx.bw.dcn.watermarks.a.pte_meta_urgent_ns = v->ptemeta_urgent_watermark * 1000;
626 context->bw_ctx.bw.dcn.watermarks.a.urgent_ns = v->urgent_watermark * 1000;
627 if (v->voltage_level >= 2) {
631 if (v->voltage_level >= 3)
681 static void hack_disable_optional_pipe_split(struct dcn_bw_internal_vars *v) in hack_disable_optional_pipe_split() argument
687 v->max_dispclk[0] = v->max_dppclk_vmin0p65; in hack_disable_optional_pipe_split()
690 static void hack_force_pipe_split(struct dcn_bw_internal_vars *v, in hack_force_pipe_split() argument
699 if (pixel_rate_mhz < v->max_dppclk[0]) in hack_force_pipe_split()
700 v->max_dppclk[0] = pixel_rate_mhz; in hack_force_pipe_split()
703 static void hack_bounding_box(struct dcn_bw_internal_vars *v, in hack_bounding_box() argument
722 hack_disable_optional_pipe_split(v); in hack_bounding_box()
728 hack_disable_optional_pipe_split(v); in hack_bounding_box()
731 context->stream_count >= 2) in hack_bounding_box()
732 hack_disable_optional_pipe_split(v); in hack_bounding_box()
736 hack_force_pipe_split(v, context->streams[0]->timing.pix_clk_100hz); in hack_bounding_box()
774 struct dcn_bw_internal_vars *v = &context->dcn_bw_vars; in dcn_validate_bandwidth() local
787 memset(v, 0, sizeof(*v)); in dcn_validate_bandwidth()
790 v->sr_exit_time = dc->dcn_soc->sr_exit_time; in dcn_validate_bandwidth()
791 v->sr_enter_plus_exit_time = dc->dcn_soc->sr_enter_plus_exit_time; in dcn_validate_bandwidth()
792 v->urgent_latency = dc->dcn_soc->urgent_latency; in dcn_validate_bandwidth()
793 v->write_back_latency = dc->dcn_soc->write_back_latency; in dcn_validate_bandwidth()
794 v->percent_of_ideal_drambw_received_after_urg_latency = in dcn_validate_bandwidth()
797 v->dcfclkv_min0p65 = dc->dcn_soc->dcfclkv_min0p65; in dcn_validate_bandwidth()
798 v->dcfclkv_mid0p72 = dc->dcn_soc->dcfclkv_mid0p72; in dcn_validate_bandwidth()
799 v->dcfclkv_nom0p8 = dc->dcn_soc->dcfclkv_nom0p8; in dcn_validate_bandwidth()
800 v->dcfclkv_max0p9 = dc->dcn_soc->dcfclkv_max0p9; in dcn_validate_bandwidth()
802 v->max_dispclk_vmin0p65 = dc->dcn_soc->max_dispclk_vmin0p65; in dcn_validate_bandwidth()
803 v->max_dispclk_vmid0p72 = dc->dcn_soc->max_dispclk_vmid0p72; in dcn_validate_bandwidth()
804 v->max_dispclk_vnom0p8 = dc->dcn_soc->max_dispclk_vnom0p8; in dcn_validate_bandwidth()
805 v->max_dispclk_vmax0p9 = dc->dcn_soc->max_dispclk_vmax0p9; in dcn_validate_bandwidth()
807 v->max_dppclk_vmin0p65 = dc->dcn_soc->max_dppclk_vmin0p65; in dcn_validate_bandwidth()
808 v->max_dppclk_vmid0p72 = dc->dcn_soc->max_dppclk_vmid0p72; in dcn_validate_bandwidth()
809 v->max_dppclk_vnom0p8 = dc->dcn_soc->max_dppclk_vnom0p8; in dcn_validate_bandwidth()
810 v->max_dppclk_vmax0p9 = dc->dcn_soc->max_dppclk_vmax0p9; in dcn_validate_bandwidth()
812 v->socclk = dc->dcn_soc->socclk; in dcn_validate_bandwidth()
814 v->fabric_and_dram_bandwidth_vmin0p65 = dc->dcn_soc->fabric_and_dram_bandwidth_vmin0p65; in dcn_validate_bandwidth()
815 v->fabric_and_dram_bandwidth_vmid0p72 = dc->dcn_soc->fabric_and_dram_bandwidth_vmid0p72; in dcn_validate_bandwidth()
816 v->fabric_and_dram_bandwidth_vnom0p8 = dc->dcn_soc->fabric_and_dram_bandwidth_vnom0p8; in dcn_validate_bandwidth()
817 v->fabric_and_dram_bandwidth_vmax0p9 = dc->dcn_soc->fabric_and_dram_bandwidth_vmax0p9; in dcn_validate_bandwidth()
819 v->phyclkv_min0p65 = dc->dcn_soc->phyclkv_min0p65; in dcn_validate_bandwidth()
820 v->phyclkv_mid0p72 = dc->dcn_soc->phyclkv_mid0p72; in dcn_validate_bandwidth()
821 v->phyclkv_nom0p8 = dc->dcn_soc->phyclkv_nom0p8; in dcn_validate_bandwidth()
822 v->phyclkv_max0p9 = dc->dcn_soc->phyclkv_max0p9; in dcn_validate_bandwidth()
824 v->downspreading = dc->dcn_soc->downspreading; in dcn_validate_bandwidth()
825 v->round_trip_ping_latency_cycles = dc->dcn_soc->round_trip_ping_latency_cycles; in dcn_validate_bandwidth()
826 v->urgent_out_of_order_return_per_channel = dc->dcn_soc->urgent_out_of_order_return_per_channel; in dcn_validate_bandwidth()
827 v->number_of_channels = dc->dcn_soc->number_of_channels; in dcn_validate_bandwidth()
828 v->vmm_page_size = dc->dcn_soc->vmm_page_size; in dcn_validate_bandwidth()
829 v->dram_clock_change_latency = dc->dcn_soc->dram_clock_change_latency; in dcn_validate_bandwidth()
830 v->return_bus_width = dc->dcn_soc->return_bus_width; in dcn_validate_bandwidth()
832 v->rob_buffer_size_in_kbyte = dc->dcn_ip->rob_buffer_size_in_kbyte; in dcn_validate_bandwidth()
833 v->det_buffer_size_in_kbyte = dc->dcn_ip->det_buffer_size_in_kbyte; in dcn_validate_bandwidth()
834 v->dpp_output_buffer_pixels = dc->dcn_ip->dpp_output_buffer_pixels; in dcn_validate_bandwidth()
835 v->opp_output_buffer_lines = dc->dcn_ip->opp_output_buffer_lines; in dcn_validate_bandwidth()
836 v->pixel_chunk_size_in_kbyte = dc->dcn_ip->pixel_chunk_size_in_kbyte; in dcn_validate_bandwidth()
837 v->pte_enable = dc->dcn_ip->pte_enable; in dcn_validate_bandwidth()
838 v->pte_chunk_size = dc->dcn_ip->pte_chunk_size; in dcn_validate_bandwidth()
839 v->meta_chunk_size = dc->dcn_ip->meta_chunk_size; in dcn_validate_bandwidth()
840 v->writeback_chunk_size = dc->dcn_ip->writeback_chunk_size; in dcn_validate_bandwidth()
841 v->odm_capability = dc->dcn_ip->odm_capability; in dcn_validate_bandwidth()
842 v->dsc_capability = dc->dcn_ip->dsc_capability; in dcn_validate_bandwidth()
843 v->line_buffer_size = dc->dcn_ip->line_buffer_size; in dcn_validate_bandwidth()
844 v->is_line_buffer_bpp_fixed = dc->dcn_ip->is_line_buffer_bpp_fixed; in dcn_validate_bandwidth()
845 v->line_buffer_fixed_bpp = dc->dcn_ip->line_buffer_fixed_bpp; in dcn_validate_bandwidth()
846 v->max_line_buffer_lines = dc->dcn_ip->max_line_buffer_lines; in dcn_validate_bandwidth()
847 v->writeback_luma_buffer_size = dc->dcn_ip->writeback_luma_buffer_size; in dcn_validate_bandwidth()
848 v->writeback_chroma_buffer_size = dc->dcn_ip->writeback_chroma_buffer_size; in dcn_validate_bandwidth()
849 v->max_num_dpp = dc->dcn_ip->max_num_dpp; in dcn_validate_bandwidth()
850 v->max_num_writeback = dc->dcn_ip->max_num_writeback; in dcn_validate_bandwidth()
851 v->max_dchub_topscl_throughput = dc->dcn_ip->max_dchub_topscl_throughput; in dcn_validate_bandwidth()
852 v->max_pscl_tolb_throughput = dc->dcn_ip->max_pscl_tolb_throughput; in dcn_validate_bandwidth()
853 v->max_lb_tovscl_throughput = dc->dcn_ip->max_lb_tovscl_throughput; in dcn_validate_bandwidth()
854 v->max_vscl_tohscl_throughput = dc->dcn_ip->max_vscl_tohscl_throughput; in dcn_validate_bandwidth()
855 v->max_hscl_ratio = dc->dcn_ip->max_hscl_ratio; in dcn_validate_bandwidth()
856 v->max_vscl_ratio = dc->dcn_ip->max_vscl_ratio; in dcn_validate_bandwidth()
857 v->max_hscl_taps = dc->dcn_ip->max_hscl_taps; in dcn_validate_bandwidth()
858 v->max_vscl_taps = dc->dcn_ip->max_vscl_taps; in dcn_validate_bandwidth()
859 v->under_scan_factor = dc->dcn_ip->under_scan_factor; in dcn_validate_bandwidth()
860 v->pte_buffer_size_in_requests = dc->dcn_ip->pte_buffer_size_in_requests; in dcn_validate_bandwidth()
861 v->dispclk_ramping_margin = dc->dcn_ip->dispclk_ramping_margin; in dcn_validate_bandwidth()
862 v->max_inter_dcn_tile_repeaters = dc->dcn_ip->max_inter_dcn_tile_repeaters; in dcn_validate_bandwidth()
863 v->can_vstartup_lines_exceed_vsync_plus_back_porch_lines_minus_one = in dcn_validate_bandwidth()
865 v->bug_forcing_luma_and_chroma_request_to_same_size_fixed = in dcn_validate_bandwidth()
868 v->voltage[5] = dcn_bw_no_support; in dcn_validate_bandwidth()
869 v->voltage[4] = dcn_bw_v_max0p9; in dcn_validate_bandwidth()
870 v->voltage[3] = dcn_bw_v_max0p9; in dcn_validate_bandwidth()
871 v->voltage[2] = dcn_bw_v_nom0p8; in dcn_validate_bandwidth()
872 v->voltage[1] = dcn_bw_v_mid0p72; in dcn_validate_bandwidth()
873 v->voltage[0] = dcn_bw_v_min0p65; in dcn_validate_bandwidth()
874 v->fabric_and_dram_bandwidth_per_state[5] = v->fabric_and_dram_bandwidth_vmax0p9; in dcn_validate_bandwidth()
875 v->fabric_and_dram_bandwidth_per_state[4] = v->fabric_and_dram_bandwidth_vmax0p9; in dcn_validate_bandwidth()
876 v->fabric_and_dram_bandwidth_per_state[3] = v->fabric_and_dram_bandwidth_vmax0p9; in dcn_validate_bandwidth()
877 v->fabric_and_dram_bandwidth_per_state[2] = v->fabric_and_dram_bandwidth_vnom0p8; in dcn_validate_bandwidth()
878 v->fabric_and_dram_bandwidth_per_state[1] = v->fabric_and_dram_bandwidth_vmid0p72; in dcn_validate_bandwidth()
879 v->fabric_and_dram_bandwidth_per_state[0] = v->fabric_and_dram_bandwidth_vmin0p65; in dcn_validate_bandwidth()
880 v->dcfclk_per_state[5] = v->dcfclkv_max0p9; in dcn_validate_bandwidth()
881 v->dcfclk_per_state[4] = v->dcfclkv_max0p9; in dcn_validate_bandwidth()
882 v->dcfclk_per_state[3] = v->dcfclkv_max0p9; in dcn_validate_bandwidth()
883 v->dcfclk_per_state[2] = v->dcfclkv_nom0p8; in dcn_validate_bandwidth()
884 v->dcfclk_per_state[1] = v->dcfclkv_mid0p72; in dcn_validate_bandwidth()
885 v->dcfclk_per_state[0] = v->dcfclkv_min0p65; in dcn_validate_bandwidth()
886 v->max_dispclk[5] = v->max_dispclk_vmax0p9; in dcn_validate_bandwidth()
887 v->max_dispclk[4] = v->max_dispclk_vmax0p9; in dcn_validate_bandwidth()
888 v->max_dispclk[3] = v->max_dispclk_vmax0p9; in dcn_validate_bandwidth()
889 v->max_dispclk[2] = v->max_dispclk_vnom0p8; in dcn_validate_bandwidth()
890 v->max_dispclk[1] = v->max_dispclk_vmid0p72; in dcn_validate_bandwidth()
891 v->max_dispclk[0] = v->max_dispclk_vmin0p65; in dcn_validate_bandwidth()
892 v->max_dppclk[5] = v->max_dppclk_vmax0p9; in dcn_validate_bandwidth()
893 v->max_dppclk[4] = v->max_dppclk_vmax0p9; in dcn_validate_bandwidth()
894 v->max_dppclk[3] = v->max_dppclk_vmax0p9; in dcn_validate_bandwidth()
895 v->max_dppclk[2] = v->max_dppclk_vnom0p8; in dcn_validate_bandwidth()
896 v->max_dppclk[1] = v->max_dppclk_vmid0p72; in dcn_validate_bandwidth()
897 v->max_dppclk[0] = v->max_dppclk_vmin0p65; in dcn_validate_bandwidth()
898 v->phyclk_per_state[5] = v->phyclkv_max0p9; in dcn_validate_bandwidth()
899 v->phyclk_per_state[4] = v->phyclkv_max0p9; in dcn_validate_bandwidth()
900 v->phyclk_per_state[3] = v->phyclkv_max0p9; in dcn_validate_bandwidth()
901 v->phyclk_per_state[2] = v->phyclkv_nom0p8; in dcn_validate_bandwidth()
902 v->phyclk_per_state[1] = v->phyclkv_mid0p72; in dcn_validate_bandwidth()
903 v->phyclk_per_state[0] = v->phyclkv_min0p65; in dcn_validate_bandwidth()
904 v->synchronized_vblank = dcn_bw_no; in dcn_validate_bandwidth()
905 v->ta_pscalculation = dcn_bw_override; in dcn_validate_bandwidth()
906 v->allow_different_hratio_vratio = dcn_bw_yes; in dcn_validate_bandwidth()
917 v->underscan_output[input_idx] = false; /* taken care of in recout already*/ in dcn_validate_bandwidth()
918 v->interlace_output[input_idx] = false; in dcn_validate_bandwidth()
920 v->htotal[input_idx] = pipe->stream->timing.h_total; in dcn_validate_bandwidth()
921 v->vtotal[input_idx] = pipe->stream->timing.v_total; in dcn_validate_bandwidth()
922 v->vactive[input_idx] = pipe->stream->timing.v_addressable + in dcn_validate_bandwidth()
924 v->v_sync_plus_back_porch[input_idx] = pipe->stream->timing.v_total in dcn_validate_bandwidth()
925 - v->vactive[input_idx] in dcn_validate_bandwidth()
927 v->pixel_clock[input_idx] = pipe->stream->timing.pix_clk_100hz/10000.0; in dcn_validate_bandwidth()
929 v->pixel_clock[input_idx] *= 2; in dcn_validate_bandwidth()
931 v->dcc_enable[input_idx] = dcn_bw_yes; in dcn_validate_bandwidth()
932 v->source_pixel_format[input_idx] = dcn_bw_rgb_sub_32; in dcn_validate_bandwidth()
933 v->source_surface_mode[input_idx] = dcn_bw_sw_4_kb_s; in dcn_validate_bandwidth()
934 v->lb_bit_per_pixel[input_idx] = 30; in dcn_validate_bandwidth()
935 v->viewport_width[input_idx] = pipe->stream->timing.h_addressable; in dcn_validate_bandwidth()
936 v->viewport_height[input_idx] = pipe->stream->timing.v_addressable; in dcn_validate_bandwidth()
944 if (v->viewport_width[input_idx] > 1920) in dcn_validate_bandwidth()
945 v->viewport_width[input_idx] = 1920; in dcn_validate_bandwidth()
946 if (v->viewport_height[input_idx] > 1080) in dcn_validate_bandwidth()
947 v->viewport_height[input_idx] = 1080; in dcn_validate_bandwidth()
948 v->scaler_rec_out_width[input_idx] = v->viewport_width[input_idx]; in dcn_validate_bandwidth()
949 v->scaler_recout_height[input_idx] = v->viewport_height[input_idx]; in dcn_validate_bandwidth()
950 v->override_hta_ps[input_idx] = 1; in dcn_validate_bandwidth()
951 v->override_vta_ps[input_idx] = 1; in dcn_validate_bandwidth()
952 v->override_hta_pschroma[input_idx] = 1; in dcn_validate_bandwidth()
953 v->override_vta_pschroma[input_idx] = 1; in dcn_validate_bandwidth()
954 v->source_scan[input_idx] = dcn_bw_hor; in dcn_validate_bandwidth()
957 v->viewport_height[input_idx] = pipe->plane_res.scl_data.viewport.height; in dcn_validate_bandwidth()
958 v->viewport_width[input_idx] = pipe->plane_res.scl_data.viewport.width; in dcn_validate_bandwidth()
959 v->scaler_rec_out_width[input_idx] = pipe->plane_res.scl_data.recout.width; in dcn_validate_bandwidth()
960 v->scaler_recout_height[input_idx] = pipe->plane_res.scl_data.recout.height; in dcn_validate_bandwidth()
962 if (pipe->plane_state->rotation % 2 == 0) { in dcn_validate_bandwidth()
969 v->viewport_width[input_idx] = viewport_end in dcn_validate_bandwidth()
972 v->viewport_width[input_idx] = viewport_b_end in dcn_validate_bandwidth()
981 v->viewport_height[input_idx] = viewport_end in dcn_validate_bandwidth()
984 v->viewport_height[input_idx] = viewport_b_end in dcn_validate_bandwidth()
987 v->scaler_rec_out_width[input_idx] = pipe->plane_res.scl_data.recout.width in dcn_validate_bandwidth()
991 if (pipe->plane_state->rotation % 2 == 0) { in dcn_validate_bandwidth()
993 || v->scaler_rec_out_width[input_idx] == v->viewport_width[input_idx]); in dcn_validate_bandwidth()
995 || v->scaler_recout_height[input_idx] == v->viewport_height[input_idx]); in dcn_validate_bandwidth()
998 || v->scaler_recout_height[input_idx] == v->viewport_width[input_idx]); in dcn_validate_bandwidth()
1000 || v->scaler_rec_out_width[input_idx] == v->viewport_height[input_idx]); in dcn_validate_bandwidth()
1008 v->dcc_enable[input_idx] = pipe->plane_state->dcc.enable ? dcn_bw_yes : dcn_bw_no; in dcn_validate_bandwidth()
1018 v->dcc_enable[input_idx] = dc->res_pool->hubbub->funcs->dcc_support_pixel_format( in dcn_validate_bandwidth()
1022 v->source_pixel_format[input_idx] = tl_pixel_format_to_bw_defs( in dcn_validate_bandwidth()
1024 v->source_surface_mode[input_idx] = tl_sw_mode_to_bw_defs( in dcn_validate_bandwidth()
1026 v->lb_bit_per_pixel[input_idx] = tl_lb_bpp_to_int(pipe->plane_res.scl_data.lb_params.depth); in dcn_validate_bandwidth()
1027 v->override_hta_ps[input_idx] = pipe->plane_res.scl_data.taps.h_taps; in dcn_validate_bandwidth()
1028 v->override_vta_ps[input_idx] = pipe->plane_res.scl_data.taps.v_taps; in dcn_validate_bandwidth()
1029 v->override_hta_pschroma[input_idx] = pipe->plane_res.scl_data.taps.h_taps_c; in dcn_validate_bandwidth()
1030 v->override_vta_pschroma[input_idx] = pipe->plane_res.scl_data.taps.v_taps_c; in dcn_validate_bandwidth()
1036 if (v->override_hta_pschroma[input_idx] == 1) in dcn_validate_bandwidth()
1037 v->override_hta_pschroma[input_idx] = 2; in dcn_validate_bandwidth()
1038 if (v->override_vta_pschroma[input_idx] == 1) in dcn_validate_bandwidth()
1039 v->override_vta_pschroma[input_idx] = 2; in dcn_validate_bandwidth()
1040 v->source_scan[input_idx] = (pipe->plane_state->rotation % 2) ? dcn_bw_vert : dcn_bw_hor; in dcn_validate_bandwidth()
1042 if (v->is_line_buffer_bpp_fixed == dcn_bw_yes) in dcn_validate_bandwidth()
1043 v->lb_bit_per_pixel[input_idx] = v->line_buffer_fixed_bpp; in dcn_validate_bandwidth()
1044 v->dcc_rate[input_idx] = 1; /*TODO: Worst case? does this change?*/ in dcn_validate_bandwidth()
1045 v->output_format[input_idx] = pipe->stream->timing.pixel_encoding == in dcn_validate_bandwidth()
1047 v->output[input_idx] = pipe->stream->signal == in dcn_validate_bandwidth()
1049 v->output_deep_color[input_idx] = dcn_bw_encoder_8bpc; in dcn_validate_bandwidth()
1050 if (v->output[input_idx] == dcn_bw_hdmi) { in dcn_validate_bandwidth()
1053 v->output_deep_color[input_idx] = dcn_bw_encoder_10bpc; in dcn_validate_bandwidth()
1056 v->output_deep_color[input_idx] = dcn_bw_encoder_12bpc; in dcn_validate_bandwidth()
1059 v->output_deep_color[input_idx] = dcn_bw_encoder_16bpc; in dcn_validate_bandwidth()
1068 v->number_of_active_planes = input_idx; in dcn_validate_bandwidth()
1070 scaler_settings_calculation(v); in dcn_validate_bandwidth()
1072 hack_bounding_box(v, &dc->debug, context); in dcn_validate_bandwidth()
1074 mode_support_and_system_configuration(v); in dcn_validate_bandwidth()
1077 if (v->voltage_level != 0 in dcn_validate_bandwidth()
1080 v->max_dppclk[0] = v->max_dppclk_vmin0p65; in dcn_validate_bandwidth()
1081 mode_support_and_system_configuration(v); in dcn_validate_bandwidth()
1084 if (v->voltage_level == 0 && in dcn_validate_bandwidth()
1089 v->sr_enter_plus_exit_time = in dcn_validate_bandwidth()
1092 v->sr_exit_time = dc->debug.sr_exit_time_dpm0_ns / 1000.0f; in dcn_validate_bandwidth()
1093 context->bw_ctx.dml.soc.sr_enter_plus_exit_time_us = v->sr_enter_plus_exit_time; in dcn_validate_bandwidth()
1094 context->bw_ctx.dml.soc.sr_exit_time_us = v->sr_exit_time; in dcn_validate_bandwidth()
1095 mode_support_and_system_configuration(v); in dcn_validate_bandwidth()
1098 display_pipe_configuration(v); in dcn_validate_bandwidth()
1100 for (k = 0; k <= v->number_of_active_planes - 1; k++) { in dcn_validate_bandwidth()
1101 if (v->source_scan[k] == dcn_bw_hor) in dcn_validate_bandwidth()
1102 v->swath_width_y[k] = v->viewport_width[k] / v->dpp_per_plane[k]; in dcn_validate_bandwidth()
1104 v->swath_width_y[k] = v->viewport_height[k] / v->dpp_per_plane[k]; in dcn_validate_bandwidth()
1106 for (k = 0; k <= v->number_of_active_planes - 1; k++) { in dcn_validate_bandwidth()
1107 if (v->source_pixel_format[k] == dcn_bw_rgb_sub_64) { in dcn_validate_bandwidth()
1108 v->byte_per_pixel_dety[k] = 8.0; in dcn_validate_bandwidth()
1109 v->byte_per_pixel_detc[k] = 0.0; in dcn_validate_bandwidth()
1110 } else if (v->source_pixel_format[k] == dcn_bw_rgb_sub_32) { in dcn_validate_bandwidth()
1111 v->byte_per_pixel_dety[k] = 4.0; in dcn_validate_bandwidth()
1112 v->byte_per_pixel_detc[k] = 0.0; in dcn_validate_bandwidth()
1113 } else if (v->source_pixel_format[k] == dcn_bw_rgb_sub_16) { in dcn_validate_bandwidth()
1114 v->byte_per_pixel_dety[k] = 2.0; in dcn_validate_bandwidth()
1115 v->byte_per_pixel_detc[k] = 0.0; in dcn_validate_bandwidth()
1116 } else if (v->source_pixel_format[k] == dcn_bw_yuv420_sub_8) { in dcn_validate_bandwidth()
1117 v->byte_per_pixel_dety[k] = 1.0; in dcn_validate_bandwidth()
1118 v->byte_per_pixel_detc[k] = 2.0; in dcn_validate_bandwidth()
1120 v->byte_per_pixel_dety[k] = 4.0f / 3.0f; in dcn_validate_bandwidth()
1121 v->byte_per_pixel_detc[k] = 8.0f / 3.0f; in dcn_validate_bandwidth()
1125 v->total_data_read_bandwidth = 0.0; in dcn_validate_bandwidth()
1126 for (k = 0; k <= v->number_of_active_planes - 1; k++) { in dcn_validate_bandwidth()
1127 v->read_bandwidth_plane_luma[k] = v->swath_width_y[k] * v->dpp_per_plane[k] * in dcn_validate_bandwidth()
1128 … dcn_bw_ceil2(v->byte_per_pixel_dety[k], 1.0) / (v->htotal[k] / v->pixel_clock[k]) * v->v_ratio[k]; in dcn_validate_bandwidth()
1129 v->read_bandwidth_plane_chroma[k] = v->swath_width_y[k] / 2.0 * v->dpp_per_plane[k] * in dcn_validate_bandwidth()
1130 …dcn_bw_ceil2(v->byte_per_pixel_detc[k], 2.0) / (v->htotal[k] / v->pixel_clock[k]) * v->v_ratio[k] … in dcn_validate_bandwidth()
1131 v->total_data_read_bandwidth = v->total_data_read_bandwidth + in dcn_validate_bandwidth()
1132 v->read_bandwidth_plane_luma[k] + v->read_bandwidth_plane_chroma[k]; in dcn_validate_bandwidth()
1137 if (v->voltage_level != number_of_states_plus_one && !fast_validate) { in dcn_validate_bandwidth()
1138 float bw_consumed = v->total_bandwidth_consumed_gbyte_per_second; in dcn_validate_bandwidth()
1140 if (bw_consumed < v->fabric_and_dram_bandwidth_vmin0p65) in dcn_validate_bandwidth()
1141 bw_consumed = v->fabric_and_dram_bandwidth_vmin0p65; in dcn_validate_bandwidth()
1142 else if (bw_consumed < v->fabric_and_dram_bandwidth_vmid0p72) in dcn_validate_bandwidth()
1143 bw_consumed = v->fabric_and_dram_bandwidth_vmid0p72; in dcn_validate_bandwidth()
1144 else if (bw_consumed < v->fabric_and_dram_bandwidth_vnom0p8) in dcn_validate_bandwidth()
1145 bw_consumed = v->fabric_and_dram_bandwidth_vnom0p8; in dcn_validate_bandwidth()
1147 bw_consumed = v->fabric_and_dram_bandwidth_vmax0p9; in dcn_validate_bandwidth()
1149 if (bw_consumed < v->fabric_and_dram_bandwidth) in dcn_validate_bandwidth()
1151 bw_consumed = v->fabric_and_dram_bandwidth; in dcn_validate_bandwidth()
1153 display_pipe_configuration(v); in dcn_validate_bandwidth()
1154 /*calc_wm_sets_and_perf_params(context, v);*/ in dcn_validate_bandwidth()
1158 dispclkdppclkdcfclk_deep_sleep_prefetch_parameters_watermarks_and_performance_calculation(v); in dcn_validate_bandwidth()
1161 v->stutter_exit_watermark * 1000; in dcn_validate_bandwidth()
1163 v->stutter_enter_plus_exit_watermark * 1000; in dcn_validate_bandwidth()
1165 v->dram_clock_change_watermark * 1000; in dcn_validate_bandwidth()
1166 context->bw_ctx.bw.dcn.watermarks.a.pte_meta_urgent_ns = v->ptemeta_urgent_watermark * 1000; in dcn_validate_bandwidth()
1167 context->bw_ctx.bw.dcn.watermarks.a.urgent_ns = v->urgent_watermark * 1000; in dcn_validate_bandwidth()
1173 (ddr4_dram_factor_single_Channel * v->number_of_channels)); in dcn_validate_bandwidth()
1174 if (bw_consumed == v->fabric_and_dram_bandwidth_vmin0p65) in dcn_validate_bandwidth()
1177 context->bw_ctx.bw.dcn.clk.dcfclk_deep_sleep_khz = (int)(v->dcf_clk_deep_sleep * 1000); in dcn_validate_bandwidth()
1178 context->bw_ctx.bw.dcn.clk.dcfclk_khz = (int)(v->dcfclk * 1000); in dcn_validate_bandwidth()
1180 context->bw_ctx.bw.dcn.clk.dispclk_khz = (int)(v->dispclk * 1000); in dcn_validate_bandwidth()
1191 v->dispclk_dppclk_ratio; in dcn_validate_bandwidth()
1192 context->bw_ctx.bw.dcn.clk.phyclk_khz = v->phyclk_per_state[v->voltage_level]; in dcn_validate_bandwidth()
1193 switch (v->voltage_level) { in dcn_validate_bandwidth()
1202 case 2: in dcn_validate_bandwidth()
1224 pipe->pipe_dlg_param.vupdate_width = v->v_update_width_pix[input_idx]; in dcn_validate_bandwidth()
1225 pipe->pipe_dlg_param.vupdate_offset = v->v_update_offset_pix[input_idx]; in dcn_validate_bandwidth()
1226 pipe->pipe_dlg_param.vready_offset = v->v_ready_offset_pix[input_idx]; in dcn_validate_bandwidth()
1227 pipe->pipe_dlg_param.vstartup_start = v->v_startup[input_idx]; in dcn_validate_bandwidth()
1254 if (v->dpp_per_plane[input_idx] == 2 || in dcn_validate_bandwidth()
1265 hsplit_pipe->pipe_dlg_param.vupdate_width = v->v_update_width_pix[input_idx]; in dcn_validate_bandwidth()
1266 hsplit_pipe->pipe_dlg_param.vupdate_offset = v->v_update_offset_pix[input_idx]; in dcn_validate_bandwidth()
1267 hsplit_pipe->pipe_dlg_param.vready_offset = v->v_ready_offset_pix[input_idx]; in dcn_validate_bandwidth()
1268 hsplit_pipe->pipe_dlg_param.vstartup_start = v->v_startup[input_idx]; in dcn_validate_bandwidth()
1281 dcn_bw_calc_rq_dlg_ttu(dc, v, hsplit_pipe, input_idx); in dcn_validate_bandwidth()
1297 dcn_bw_calc_rq_dlg_ttu(dc, v, pipe, input_idx); in dcn_validate_bandwidth()
1302 } else if (v->voltage_level == number_of_states_plus_one) { in dcn_validate_bandwidth()
1308 if (v->voltage_level == 0) { in dcn_validate_bandwidth()
1318 bw_limit = dc->dcn_soc->percent_disp_bw_limit * v->fabric_and_dram_bandwidth_vmax0p9; in dcn_validate_bandwidth()
1319 bw_limit_pass = (v->total_data_read_bandwidth / 1000.0) < bw_limit; in dcn_validate_bandwidth()
1326 if (bw_limit_pass && v->voltage_level <= get_highest_allowed_voltage_level( in dcn_validate_bandwidth()
1502 (fclks.num_levels > 2 ? 3 : (fclks.num_levels > 1 ? 2 : 1)); in dcn_bw_update_from_pplib()
1503 vnom0p8_idx = fclks.num_levels - (fclks.num_levels > 1 ? 2 : 1); in dcn_bw_update_from_pplib()
1536 dc->dcn_soc->dcfclkv_nom0p8 = dcfclks.data[dcfclks.num_levels - 2].clocks_in_khz / 1000.0; in dcn_bw_update_from_pplib()
1599 ranges.reader_wm_sets[2] = ranges.writer_wm_sets[0]; in dcn_bw_notify_pplib_of_wm_ranges()
1600 ranges.reader_wm_sets[2].wm_inst = WM_C; in dcn_bw_notify_pplib_of_wm_ranges()