Lines Matching full:dm
122 * **dm**) sits between DRM and DC. It acts as a liason, converting DRM
177 static void amdgpu_dm_destroy_drm_device(struct amdgpu_display_manager *dm);
179 static int amdgpu_dm_plane_init(struct amdgpu_display_manager *dm,
183 static int amdgpu_dm_crtc_init(struct amdgpu_display_manager *dm,
186 static int amdgpu_dm_connector_init(struct amdgpu_display_manager *dm,
212 static bool amdgpu_dm_psr_disable_all(struct amdgpu_display_manager *dm);
473 adev->dm.freesync_module, in dm_vupdate_high_irq()
478 adev->dm.dc, in dm_vupdate_high_irq()
536 mod_freesync_handle_v_update(adev->dm.freesync_module, in dm_crtc_high_irq()
540 dc_stream_adjust_vmin_vmax(adev->dm.dc, acrtc->dm_irq_params.stream, in dm_crtc_high_irq()
588 struct dm_compressor_info *compressor = &adev->dm.compressor; in amdgpu_dm_fbc_init()
593 if (adev->dm.dc->fbc_compressor == NULL) in amdgpu_dm_fbc_init()
614 DRM_ERROR("DM: Failed to initialize FBC\n"); in amdgpu_dm_fbc_init()
616 adev->dm.dc->ctx->fbc_gpu_addr = compressor->gpu_addr; in amdgpu_dm_fbc_init()
617 DRM_INFO("DM: FBC alloc %lu\n", max_size*4); in amdgpu_dm_fbc_init()
637 mutex_lock(&adev->dm.audio_lock); in amdgpu_dm_audio_component_get_eld()
653 mutex_unlock(&adev->dm.audio_lock); in amdgpu_dm_audio_component_get_eld()
673 adev->dm.audio_component = acomp; in amdgpu_dm_audio_component_bind()
687 adev->dm.audio_component = NULL; in amdgpu_dm_audio_component_unbind()
704 adev->mode_info.audio.num_pins = adev->dm.dc->res_pool->audio_count; in amdgpu_dm_audio_init()
714 adev->dm.dc->res_pool->audios[i]->inst; in amdgpu_dm_audio_init()
722 adev->dm.audio_registered = true; in amdgpu_dm_audio_init()
735 if (adev->dm.audio_registered) { in amdgpu_dm_audio_fini()
737 adev->dm.audio_registered = false; in amdgpu_dm_audio_fini()
747 struct drm_audio_component *acomp = adev->dm.audio_component; in amdgpu_dm_audio_eld_notify()
760 struct dmub_srv *dmub_srv = adev->dm.dmub_srv; in dm_dmub_hw_init()
761 struct dmub_srv_fb_info *fb_info = adev->dm.dmub_fb_info; in dm_dmub_hw_init()
762 const struct firmware *dmub_fw = adev->dm.dmub_fw; in dm_dmub_hw_init()
763 struct dmcu *dmcu = adev->dm.dc->res_pool->dmcu; in dm_dmub_hw_init()
764 struct abm *abm = adev->dm.dc->res_pool->abm; in dm_dmub_hw_init()
873 adev->dm.dc->ctx->dmub_srv = dc_dmub_srv_create(adev->dm.dc, dmub_srv); in dm_dmub_hw_init()
874 if (!adev->dm.dc->ctx->dmub_srv) { in dm_dmub_hw_init()
880 adev->dm.dmcub_fw_version); in dm_dmub_hw_init()
932 adev->dm.ddev = adev_to_drm(adev); in amdgpu_dm_init()
933 adev->dm.adev = adev; in amdgpu_dm_init()
941 mutex_init(&adev->dm.dc_lock); in amdgpu_dm_init()
942 mutex_init(&adev->dm.audio_lock); in amdgpu_dm_init()
945 DRM_ERROR("amdgpu: failed to initialize DM IRQ support.\n"); in amdgpu_dm_init()
961 adev->dm.cgs_device = amdgpu_cgs_create_device(adev); in amdgpu_dm_init()
963 if (!adev->dm.cgs_device) { in amdgpu_dm_init()
968 init_data.cgs_device = adev->dm.cgs_device; in amdgpu_dm_init()
996 init_data.soc_bounding_box = adev->dm.soc_bounding_box; in amdgpu_dm_init()
999 adev->dm.dc = dc_create(&init_data); in amdgpu_dm_init()
1001 if (adev->dm.dc) { in amdgpu_dm_init()
1009 adev->dm.dc->debug.force_single_disp_pipe_split = false; in amdgpu_dm_init()
1010 adev->dm.dc->debug.pipe_split_policy = MPC_SPLIT_AVOID; in amdgpu_dm_init()
1014 adev->dm.dc->debug.disable_stutter = amdgpu_pp_feature_mask & PP_STUTTER_MODE ? false : true; in amdgpu_dm_init()
1017 adev->dm.dc->debug.disable_stutter = true; in amdgpu_dm_init()
1020 adev->dm.dc->debug.disable_dsc = true; in amdgpu_dm_init()
1023 adev->dm.dc->debug.disable_clock_gate = true; in amdgpu_dm_init()
1031 dc_hardware_init(adev->dm.dc); in amdgpu_dm_init()
1033 adev->dm.freesync_module = mod_freesync_create(adev->dm.dc); in amdgpu_dm_init()
1034 if (!adev->dm.freesync_module) { in amdgpu_dm_init()
1039 adev->dm.freesync_module); in amdgpu_dm_init()
1044 if (adev->dm.dc->caps.max_links > 0 && adev->asic_type >= CHIP_RAVEN) { in amdgpu_dm_init()
1045 adev->dm.hdcp_workqueue = hdcp_create_workqueue(adev, &init_params.cp_psp, adev->dm.dc); in amdgpu_dm_init()
1047 if (!adev->dm.hdcp_workqueue) in amdgpu_dm_init()
1050 DRM_DEBUG_DRIVER("amdgpu: hdcp_workqueue init done %p.\n", adev->dm.hdcp_workqueue); in amdgpu_dm_init()
1052 dc_init_callbacks(adev->dm.dc, &init_params); in amdgpu_dm_init()
1067 adev_to_drm(adev)->mode_config.cursor_width = adev->dm.dc->caps.max_cursor_size; in amdgpu_dm_init()
1068 adev_to_drm(adev)->mode_config.cursor_height = adev->dm.dc->caps.max_cursor_size; in amdgpu_dm_init()
1070 if (drm_vblank_init(adev_to_drm(adev), adev->dm.display_indexes_num)) { in amdgpu_dm_init()
1089 for (i = 0; i < adev->dm.display_indexes_num; i++) { in amdgpu_dm_fini()
1090 drm_encoder_cleanup(&adev->dm.mst_encoders[i].base); in amdgpu_dm_fini()
1095 amdgpu_dm_destroy_drm_device(&adev->dm); in amdgpu_dm_fini()
1098 if (adev->dm.hdcp_workqueue) { in amdgpu_dm_fini()
1099 hdcp_destroy(adev->dm.hdcp_workqueue); in amdgpu_dm_fini()
1100 adev->dm.hdcp_workqueue = NULL; in amdgpu_dm_fini()
1103 if (adev->dm.dc) in amdgpu_dm_fini()
1104 dc_deinit_callbacks(adev->dm.dc); in amdgpu_dm_fini()
1106 if (adev->dm.dc->ctx->dmub_srv) { in amdgpu_dm_fini()
1107 dc_dmub_srv_destroy(&adev->dm.dc->ctx->dmub_srv); in amdgpu_dm_fini()
1108 adev->dm.dc->ctx->dmub_srv = NULL; in amdgpu_dm_fini()
1111 if (adev->dm.dmub_bo) in amdgpu_dm_fini()
1112 amdgpu_bo_free_kernel(&adev->dm.dmub_bo, in amdgpu_dm_fini()
1113 &adev->dm.dmub_bo_gpu_addr, in amdgpu_dm_fini()
1114 &adev->dm.dmub_bo_cpu_addr); in amdgpu_dm_fini()
1117 if (adev->dm.dc) in amdgpu_dm_fini()
1118 dc_destroy(&adev->dm.dc); in amdgpu_dm_fini()
1125 if (adev->dm.cgs_device) { in amdgpu_dm_fini()
1126 amdgpu_cgs_destroy_device(adev->dm.cgs_device); in amdgpu_dm_fini()
1127 adev->dm.cgs_device = NULL; in amdgpu_dm_fini()
1129 if (adev->dm.freesync_module) { in amdgpu_dm_fini()
1130 mod_freesync_destroy(adev->dm.freesync_module); in amdgpu_dm_fini()
1131 adev->dm.freesync_module = NULL; in amdgpu_dm_fini()
1134 mutex_destroy(&adev->dm.audio_lock); in amdgpu_dm_fini()
1135 mutex_destroy(&adev->dm.dc_lock); in amdgpu_dm_fini()
1194 DRM_DEBUG_KMS("dm: DMCU firmware not supported on direct or SMU loading\n"); in load_dmcu_fw()
1198 r = request_firmware_direct(&adev->dm.fw_dmcu, fw_name_dmcu, adev->dev); in load_dmcu_fw()
1201 DRM_DEBUG_KMS("dm: DMCU firmware not found\n"); in load_dmcu_fw()
1202 adev->dm.fw_dmcu = NULL; in load_dmcu_fw()
1211 r = amdgpu_ucode_validate(adev->dm.fw_dmcu); in load_dmcu_fw()
1215 release_firmware(adev->dm.fw_dmcu); in load_dmcu_fw()
1216 adev->dm.fw_dmcu = NULL; in load_dmcu_fw()
1220 hdr = (const struct dmcu_firmware_header_v1_0 *)adev->dm.fw_dmcu->data; in load_dmcu_fw()
1222 adev->firmware.ucode[AMDGPU_UCODE_ID_DMCU_ERAM].fw = adev->dm.fw_dmcu; in load_dmcu_fw()
1227 adev->firmware.ucode[AMDGPU_UCODE_ID_DMCU_INTV].fw = adev->dm.fw_dmcu; in load_dmcu_fw()
1231 adev->dm.dmcu_fw_version = le32_to_cpu(hdr->header.ucode_version); in load_dmcu_fw()
1242 return dm_read_reg(adev->dm.dc->ctx, address); in amdgpu_dm_dmub_reg_read()
1250 return dm_write_reg(adev->dm.dc->ctx, address, value); in amdgpu_dm_dmub_reg_write()
1290 r = request_firmware_direct(&adev->dm.dmub_fw, fw_name_dmub, adev->dev); in dm_dmub_sw_init()
1296 r = amdgpu_ucode_validate(adev->dm.dmub_fw); in dm_dmub_sw_init()
1302 hdr = (const struct dmcub_firmware_header_v1_0 *)adev->dm.dmub_fw->data; in dm_dmub_sw_init()
1308 adev->dm.dmub_fw; in dm_dmub_sw_init()
1313 adev->dm.dmcub_fw_version); in dm_dmub_sw_init()
1316 adev->dm.dmcub_fw_version = le32_to_cpu(hdr->header.ucode_version); in dm_dmub_sw_init()
1318 adev->dm.dmub_srv = kzalloc(sizeof(*adev->dm.dmub_srv), GFP_KERNEL); in dm_dmub_sw_init()
1319 dmub_srv = adev->dm.dmub_srv; in dm_dmub_sw_init()
1347 adev->dm.dmub_fw->data + in dm_dmub_sw_init()
1351 adev->dm.dmub_fw->data + in dm_dmub_sw_init()
1368 AMDGPU_GEM_DOMAIN_VRAM, &adev->dm.dmub_bo, in dm_dmub_sw_init()
1369 &adev->dm.dmub_bo_gpu_addr, in dm_dmub_sw_init()
1370 &adev->dm.dmub_bo_cpu_addr); in dm_dmub_sw_init()
1376 fb_params.cpu_addr = adev->dm.dmub_bo_cpu_addr; in dm_dmub_sw_init()
1377 fb_params.gpu_addr = adev->dm.dmub_bo_gpu_addr; in dm_dmub_sw_init()
1380 adev->dm.dmub_fb_info = in dm_dmub_sw_init()
1381 kzalloc(sizeof(*adev->dm.dmub_fb_info), GFP_KERNEL); in dm_dmub_sw_init()
1382 fb_info = adev->dm.dmub_fb_info; in dm_dmub_sw_init()
1415 kfree(adev->dm.dmub_fb_info); in dm_sw_fini()
1416 adev->dm.dmub_fb_info = NULL; in dm_sw_fini()
1418 if (adev->dm.dmub_srv) { in dm_sw_fini()
1419 dmub_srv_destroy(adev->dm.dmub_srv); in dm_sw_fini()
1420 adev->dm.dmub_srv = NULL; in dm_sw_fini()
1423 release_firmware(adev->dm.dmub_fw); in dm_sw_fini()
1424 adev->dm.dmub_fw = NULL; in dm_sw_fini()
1426 release_firmware(adev->dm.fw_dmcu); in dm_sw_fini()
1427 adev->dm.fw_dmcu = NULL; in dm_sw_fini()
1472 dmcu = adev->dm.dc->res_pool->dmcu; in dm_late_init()
1494 else if (adev->dm.dc->ctx->dmub_srv) in dm_late_init()
1495 ret = dmub_init_abm_config(adev->dm.dc->res_pool, params); in dm_late_init()
1598 * the initializers of each DM component, then populating the struct with them.
1660 rc = dc_interrupt_set(adev->dm.dc, irq_source, enable) ? 0 : -EBUSY; in dm_gpureset_toggle_interrupts()
1735 struct amdgpu_display_manager *dm = &adev->dm; in dm_suspend() local
1739 mutex_lock(&dm->dc_lock); in dm_suspend()
1740 dm->cached_dc_state = dc_copy_state(dm->dc->current_state); in dm_suspend()
1742 dm_gpureset_toggle_interrupts(adev, dm->cached_dc_state, false); in dm_suspend()
1744 amdgpu_dm_commit_zero_streams(dm->dc); in dm_suspend()
1751 WARN_ON(adev->dm.cached_state); in dm_suspend()
1752 adev->dm.cached_state = drm_atomic_helper_suspend(adev_to_drm(adev)); in dm_suspend()
1759 dc_set_power_state(dm->dc, DC_ACPI_CM_POWER_STATE_D3); in dm_suspend()
1866 struct amdgpu_display_manager *dm) in dm_gpureset_commit_state() argument
1894 dm->dc, bundle->surface_updates, in dm_gpureset_commit_state()
1909 struct amdgpu_display_manager *dm = &adev->dm; in dm_resume() local
1919 struct dm_atomic_state *dm_state = to_dm_atomic_state(dm->atomic_obj.state); in dm_resume()
1925 dc_state = dm->cached_dc_state; in dm_resume()
1931 dc_set_power_state(dm->dc, DC_ACPI_CM_POWER_STATE_D0); in dm_resume()
1932 dc_resume(dm->dc); in dm_resume()
1944 WARN_ON(!dc_commit_state(dm->dc, dc_state)); in dm_resume()
1946 dm_gpureset_commit_state(dm->cached_dc_state, dm); in dm_resume()
1948 dm_gpureset_toggle_interrupts(adev, dm->cached_dc_state, true); in dm_resume()
1950 dc_release_state(dm->cached_dc_state); in dm_resume()
1951 dm->cached_dc_state = NULL; in dm_resume()
1955 mutex_unlock(&dm->dc_lock); in dm_resume()
1961 dm_state->context = dc_create_state(dm->dc); in dm_resume()
1963 dc_resource_state_construct(dm->dc, dm_state->context); in dm_resume()
1971 dc_set_power_state(dm->dc, DC_ACPI_CM_POWER_STATE_D0); in dm_resume()
1974 dc_resume(dm->dc); in dm_resume()
2018 for_each_new_crtc_in_state(dm->cached_state, crtc, new_crtc_state, i) in dm_resume()
2026 for_each_new_crtc_in_state(dm->cached_state, crtc, new_crtc_state, i) { in dm_resume()
2035 for_each_new_plane_in_state(dm->cached_state, plane, new_plane_state, i) { in dm_resume()
2044 drm_atomic_helper_resume(ddev, dm->cached_state); in dm_resume()
2046 dm->cached_state = NULL; in dm_resume()
2056 * DOC: DM Lifecycle
2058 * DM (and consequently DC) is registered in the amdgpu base driver as a IP
2059 * block. When CONFIG_DRM_AMD_DC is enabled, the DM device IP block is added to
2066 .name = "dm",
2114 struct amdgpu_display_manager *dm; in update_connector_ext_caps() local
2131 dm = &adev->dm; in update_connector_ext_caps()
2132 caps = &dm->backlight_caps; in update_connector_ext_caps()
2330 if (adev->dm.hdcp_workqueue) in handle_hpd_irq()
2331 hdcp_reset_display(adev->dm.hdcp_workqueue, aconnector->dc_link->link_index); in handle_hpd_irq()
2508 if (adev->dm.hdcp_workqueue) in handle_hpd_rx_irq()
2509 hdcp_handle_cpirq(adev->dm.hdcp_workqueue, aconnector->base.index); in handle_hpd_rx_irq()
2565 struct dc *dc = adev->dm.dc; in dce60_register_irq_handlers()
2598 c_irq_params = &adev->dm.vblank_params[int_params.irq_source - DC_IRQ_SOURCE_VBLANK1]; in dce60_register_irq_handlers()
2620 c_irq_params = &adev->dm.pflip_params[int_params.irq_source - DC_IRQ_SOURCE_PFLIP_FIRST]; in dce60_register_irq_handlers()
2647 struct dc *dc = adev->dm.dc; in dce110_register_irq_handlers()
2683 c_irq_params = &adev->dm.vblank_params[int_params.irq_source - DC_IRQ_SOURCE_VBLANK1]; in dce110_register_irq_handlers()
2704 c_irq_params = &adev->dm.vupdate_params[int_params.irq_source - DC_IRQ_SOURCE_VUPDATE1]; in dce110_register_irq_handlers()
2726 c_irq_params = &adev->dm.pflip_params[int_params.irq_source - DC_IRQ_SOURCE_PFLIP_FIRST]; in dce110_register_irq_handlers()
2753 struct dc *dc = adev->dm.dc; in dcn10_register_irq_handlers()
2789 c_irq_params = &adev->dm.vblank_params[int_params.irq_source - DC_IRQ_SOURCE_VBLANK1]; in dcn10_register_irq_handlers()
2817 c_irq_params = &adev->dm.vupdate_params[int_params.irq_source - DC_IRQ_SOURCE_VUPDATE1]; in dcn10_register_irq_handlers()
2840 c_irq_params = &adev->dm.pflip_params[int_params.irq_source - DC_IRQ_SOURCE_PFLIP_FIRST]; in dcn10_register_irq_handlers()
2875 struct amdgpu_display_manager *dm = &adev->dm; in dm_atomic_get_state() local
2881 priv_state = drm_atomic_get_private_obj_state(state, &dm->atomic_obj); in dm_atomic_get_state()
2895 struct amdgpu_display_manager *dm = &adev->dm; in dm_atomic_get_new_state() local
2901 if (obj->funcs == dm->atomic_obj.funcs) in dm_atomic_get_new_state()
2972 state->context = dc_create_state(adev->dm.dc); in amdgpu_dm_mode_config_init()
2978 dc_resource_state_copy_construct_current(adev->dm.dc, state->context); in amdgpu_dm_mode_config_init()
2981 &adev->dm.atomic_obj, in amdgpu_dm_mode_config_init()
3009 static void amdgpu_dm_update_backlight_caps(struct amdgpu_display_manager *dm) in amdgpu_dm_update_backlight_caps() argument
3016 if (dm->backlight_caps.caps_valid) in amdgpu_dm_update_backlight_caps()
3019 amdgpu_acpi_get_backlight_caps(dm->adev, &caps); in amdgpu_dm_update_backlight_caps()
3021 dm->backlight_caps.caps_valid = true; in amdgpu_dm_update_backlight_caps()
3024 dm->backlight_caps.min_input_signal = caps.min_input_signal; in amdgpu_dm_update_backlight_caps()
3025 dm->backlight_caps.max_input_signal = caps.max_input_signal; in amdgpu_dm_update_backlight_caps()
3027 dm->backlight_caps.min_input_signal = in amdgpu_dm_update_backlight_caps()
3029 dm->backlight_caps.max_input_signal = in amdgpu_dm_update_backlight_caps()
3033 if (dm->backlight_caps.aux_support) in amdgpu_dm_update_backlight_caps()
3036 dm->backlight_caps.min_input_signal = AMDGPU_DM_DEFAULT_MIN_BACKLIGHT; in amdgpu_dm_update_backlight_caps()
3037 dm->backlight_caps.max_input_signal = AMDGPU_DM_DEFAULT_MAX_BACKLIGHT; in amdgpu_dm_update_backlight_caps()
3102 struct amdgpu_display_manager *dm = bl_get_data(bd); in amdgpu_dm_backlight_update_status() local
3108 amdgpu_dm_update_backlight_caps(dm); in amdgpu_dm_backlight_update_status()
3109 caps = dm->backlight_caps; in amdgpu_dm_backlight_update_status()
3111 link = (struct dc_link *)dm->backlight_link; in amdgpu_dm_backlight_update_status()
3118 rc = dc_link_set_backlight_level(dm->backlight_link, brightness, 0); in amdgpu_dm_backlight_update_status()
3125 struct amdgpu_display_manager *dm = bl_get_data(bd); in amdgpu_dm_backlight_get_brightness() local
3126 int ret = dc_link_get_backlight_level(dm->backlight_link); in amdgpu_dm_backlight_get_brightness()
3130 return convert_brightness_to_user(&dm->backlight_caps, ret); in amdgpu_dm_backlight_get_brightness()
3140 amdgpu_dm_register_backlight_device(struct amdgpu_display_manager *dm) in amdgpu_dm_register_backlight_device() argument
3145 amdgpu_dm_update_backlight_caps(dm); in amdgpu_dm_register_backlight_device()
3152 adev_to_drm(dm->adev)->primary->index); in amdgpu_dm_register_backlight_device()
3154 dm->backlight_dev = backlight_device_register(bl_name, in amdgpu_dm_register_backlight_device()
3155 adev_to_drm(dm->adev)->dev, in amdgpu_dm_register_backlight_device()
3156 dm, in amdgpu_dm_register_backlight_device()
3160 if (IS_ERR(dm->backlight_dev)) in amdgpu_dm_register_backlight_device()
3161 DRM_ERROR("DM: Backlight registration failed!\n"); in amdgpu_dm_register_backlight_device()
3163 DRM_DEBUG_DRIVER("DM: Registered Backlight device: %s\n", bl_name); in amdgpu_dm_register_backlight_device()
3168 static int initialize_plane(struct amdgpu_display_manager *dm, in initialize_plane() argument
3191 if (plane_id >= dm->dc->caps.max_streams) in initialize_plane()
3194 ret = amdgpu_dm_plane_init(dm, plane, possible_crtcs, plane_cap); in initialize_plane()
3209 static void register_backlight_device(struct amdgpu_display_manager *dm, in register_backlight_device() argument
3219 * DM initialization because not having a backlight control in register_backlight_device()
3222 amdgpu_dm_register_backlight_device(dm); in register_backlight_device()
3224 if (dm->backlight_dev) in register_backlight_device()
3225 dm->backlight_link = link; in register_backlight_device()
3241 struct amdgpu_display_manager *dm = &adev->dm; in amdgpu_dm_initialize_drm_device() local
3251 dm->display_indexes_num = dm->dc->caps.max_streams; in amdgpu_dm_initialize_drm_device()
3253 adev->mode_info.num_crtc = adev->dm.display_indexes_num; in amdgpu_dm_initialize_drm_device()
3255 link_cnt = dm->dc->caps.max_links; in amdgpu_dm_initialize_drm_device()
3256 if (amdgpu_dm_mode_config_init(dm->adev)) { in amdgpu_dm_initialize_drm_device()
3257 DRM_ERROR("DM: Failed to initialize mode config\n"); in amdgpu_dm_initialize_drm_device()
3262 primary_planes = dm->dc->caps.max_streams; in amdgpu_dm_initialize_drm_device()
3270 plane = &dm->dc->caps.planes[i]; in amdgpu_dm_initialize_drm_device()
3272 if (initialize_plane(dm, mode_info, i, in amdgpu_dm_initialize_drm_device()
3288 for (i = 0; i < dm->dc->caps.max_planes; ++i) { in amdgpu_dm_initialize_drm_device()
3289 struct dc_plane_cap *plane = &dm->dc->caps.planes[i]; in amdgpu_dm_initialize_drm_device()
3300 if (initialize_plane(dm, NULL, primary_planes + i, in amdgpu_dm_initialize_drm_device()
3310 for (i = 0; i < dm->dc->caps.max_streams; i++) in amdgpu_dm_initialize_drm_device()
3311 if (amdgpu_dm_crtc_init(dm, mode_info->planes[i], i)) { in amdgpu_dm_initialize_drm_device()
3335 if (amdgpu_dm_encoder_init(dm->ddev, aencoder, i)) { in amdgpu_dm_initialize_drm_device()
3340 if (amdgpu_dm_connector_init(dm, aconnector, i, aencoder)) { in amdgpu_dm_initialize_drm_device()
3345 link = dc_get_link_at_index(dm->dc, i); in amdgpu_dm_initialize_drm_device()
3356 register_backlight_device(dm, link); in amdgpu_dm_initialize_drm_device()
3371 if (dce60_register_irq_handlers(dm->adev)) { in amdgpu_dm_initialize_drm_device()
3372 DRM_ERROR("DM: Failed to initialize IRQ\n"); in amdgpu_dm_initialize_drm_device()
3393 if (dce110_register_irq_handlers(dm->adev)) { in amdgpu_dm_initialize_drm_device()
3394 DRM_ERROR("DM: Failed to initialize IRQ\n"); in amdgpu_dm_initialize_drm_device()
3408 if (dcn10_register_irq_handlers(dm->adev)) { in amdgpu_dm_initialize_drm_device()
3409 DRM_ERROR("DM: Failed to initialize IRQ\n"); in amdgpu_dm_initialize_drm_device()
3427 static void amdgpu_dm_destroy_drm_device(struct amdgpu_display_manager *dm) in amdgpu_dm_destroy_drm_device() argument
3429 drm_mode_config_cleanup(dm->ddev); in amdgpu_dm_destroy_drm_device()
3430 drm_atomic_private_obj_fini(&dm->atomic_obj); in amdgpu_dm_destroy_drm_device()
3746 struct dc *dc = adev->dm.dc; in fill_plane_dcc_attributes()
4873 rc = dc_interrupt_set(adev->dm.dc, irq_source, enable) ? 0 : -EBUSY; in dm_set_vupdate_irq()
4901 return dc_interrupt_set(adev->dm.dc, irq_source, enable) ? 0 : -EBUSY; in dm_set_vblank()
5069 struct amdgpu_display_manager *dm = &adev->dm; in amdgpu_dm_connector_destroy() local
5083 dm->backlight_dev) { in amdgpu_dm_connector_destroy()
5084 backlight_device_unregister(dm->backlight_dev); in amdgpu_dm_connector_destroy()
5085 dm->backlight_dev = NULL; in amdgpu_dm_connector_destroy()
5275 dc_result = dc_validate_stream(adev->dm.dc, stream); in create_validate_stream_for_sink()
5525 struct dc *dc = adev->dm.dc; in dm_crtc_helper_atomic_check()
5898 struct dc *dc = adev->dm.dc; in dm_plane_atomic_check()
6053 static int amdgpu_dm_plane_init(struct amdgpu_display_manager *dm, in amdgpu_dm_plane_init() argument
6066 res = drm_universal_plane_init(adev_to_drm(dm->adev), plane, possible_crtcs, in amdgpu_dm_plane_init()
6100 if (dm->adev->asic_type >= CHIP_BONAIRE) in amdgpu_dm_plane_init()
6113 static int amdgpu_dm_crtc_init(struct amdgpu_display_manager *dm, in amdgpu_dm_crtc_init() argument
6127 res = amdgpu_dm_plane_init(dm, cursor_plane, 0, NULL); in amdgpu_dm_crtc_init()
6134 dm->ddev, in amdgpu_dm_crtc_init()
6149 acrtc->max_cursor_width = dm->adev->dm.dc->caps.max_cursor_size; in amdgpu_dm_crtc_init()
6150 acrtc->max_cursor_height = dm->adev->dm.dc->caps.max_cursor_size; in amdgpu_dm_crtc_init()
6156 dm->adev->mode_info.crtcs[crtc_index] = acrtc; in amdgpu_dm_crtc_init()
6366 void amdgpu_dm_connector_init_helper(struct amdgpu_display_manager *dm, in amdgpu_dm_connector_init_helper() argument
6372 struct amdgpu_device *adev = drm_to_adev(dm->ddev); in amdgpu_dm_connector_init_helper()
6414 dm->ddev->mode_config.scaling_mode_property, in amdgpu_dm_connector_init_helper()
6435 (dc_is_dmcu_initialized(adev->dm.dc) || adev->dm.dc->ctx->dmub_srv)) { in amdgpu_dm_connector_init_helper()
6445 dm->ddev->mode_config.hdr_output_metadata_property, 0); in amdgpu_dm_connector_init_helper()
6451 if (adev->dm.hdcp_workqueue) in amdgpu_dm_connector_init_helper()
6517 snprintf(i2c->base.name, sizeof(i2c->base.name), "AMDGPU DM i2c hw bus %d", link_index); in create_i2c()
6530 static int amdgpu_dm_connector_init(struct amdgpu_display_manager *dm, in amdgpu_dm_connector_init() argument
6537 struct dc *dc = dm->dc; in amdgpu_dm_connector_init()
6562 dm->ddev, in amdgpu_dm_connector_init()
6579 dm, in amdgpu_dm_connector_init()
6590 amdgpu_dm_initialize_dp_connector(dm, aconnector, link->link_index); in amdgpu_dm_connector_init()
6834 mutex_lock(&adev->dm.dc_lock); in handle_cursor_update()
6837 mutex_unlock(&adev->dm.dc_lock); in handle_cursor_update()
6857 mutex_lock(&adev->dm.dc_lock); in handle_cursor_update()
6865 mutex_unlock(&adev->dm.dc_lock); in handle_cursor_update()
6888 struct amdgpu_display_manager *dm, in update_freesync_state_on_stream() argument
6896 struct amdgpu_device *adev = dm->adev; in update_freesync_state_on_stream()
6916 dm->freesync_module, in update_freesync_state_on_stream()
6924 mod_freesync_handle_v_update(dm->freesync_module, in update_freesync_state_on_stream()
6928 dc_stream_adjust_vmin_vmax(dm->dc, in update_freesync_state_on_stream()
6935 dm->freesync_module, in update_freesync_state_on_stream()
6968 struct amdgpu_display_manager *dm, in update_stream_irq_parameters() argument
6974 struct amdgpu_device *adev = dm->adev; in update_stream_irq_parameters()
7001 mod_freesync_build_vrr_params(dm->freesync_module, in update_stream_irq_parameters()
7010 /* Copy state for access from DM IRQ handler */ in update_stream_irq_parameters()
7066 struct amdgpu_display_manager *dm, in amdgpu_dm_commit_planes() argument
7168 dm->adev, new_plane_state, in amdgpu_dm_commit_planes()
7202 dm, in amdgpu_dm_commit_planes()
7248 (amdgpu_display_get_crtc_scanoutpos(dm->ddev, acrtc_attach->crtc_id, in amdgpu_dm_commit_planes()
7320 dm->dc, acrtc_state->stream, in amdgpu_dm_commit_planes()
7324 mutex_lock(&dm->dc_lock); in amdgpu_dm_commit_planes()
7329 dc_commit_updates_for_stream(dm->dc, in amdgpu_dm_commit_planes()
7363 mutex_unlock(&dm->dc_lock); in amdgpu_dm_commit_planes()
7412 mutex_lock(&adev->dm.audio_lock); in amdgpu_dm_commit_audio()
7415 mutex_unlock(&adev->dm.audio_lock); in amdgpu_dm_commit_audio()
7444 mutex_lock(&adev->dm.audio_lock); in amdgpu_dm_commit_audio()
7447 mutex_unlock(&adev->dm.audio_lock); in amdgpu_dm_commit_audio()
7482 * amdgpu_dm_atomic_commit_tail() - AMDgpu DM's commit tail implementation.
7493 struct amdgpu_display_manager *dm = &adev->dm; in amdgpu_dm_atomic_commit_tail() local
7514 dc_state_temp = dc_create_state(dm->dc); in amdgpu_dm_atomic_commit_tail()
7517 dc_resource_state_copy_construct_current(dm->dc, dc_state); in amdgpu_dm_atomic_commit_tail()
7611 amdgpu_dm_psr_disable_all(dm); in amdgpu_dm_atomic_commit_tail()
7614 mutex_lock(&dm->dc_lock); in amdgpu_dm_atomic_commit_tail()
7615 WARN_ON(!dc_commit_state(dm->dc, dc_state)); in amdgpu_dm_atomic_commit_tail()
7616 mutex_unlock(&dm->dc_lock); in amdgpu_dm_atomic_commit_tail()
7652 hdcp_reset_display(adev->dm.hdcp_workqueue, aconnector->dc_link->link_index); in amdgpu_dm_atomic_commit_tail()
7657 …if (is_content_protection_different(new_con_state, old_con_state, connector, adev->dm.hdcp_workque… in amdgpu_dm_atomic_commit_tail()
7659 adev->dm.hdcp_workqueue, aconnector->dc_link->link_index, aconnector, in amdgpu_dm_atomic_commit_tail()
7737 mutex_lock(&dm->dc_lock); in amdgpu_dm_atomic_commit_tail()
7738 dc_commit_updates_for_stream(dm->dc, in amdgpu_dm_atomic_commit_tail()
7744 mutex_unlock(&dm->dc_lock); in amdgpu_dm_atomic_commit_tail()
7757 update_stream_irq_parameters(dm, dm_new_crtc_state); in amdgpu_dm_atomic_commit_tail()
7808 dm, crtc, wait_for_vblank); in amdgpu_dm_atomic_commit_tail()
8029 static int dm_update_crtc_state(struct amdgpu_display_manager *dm, in dm_update_crtc_state() argument
8101 dm->force_timing_sync; in dm_update_crtc_state()
8159 dm->dc, in dm_update_crtc_state()
8202 dm->dc, in dm_update_crtc_state()
8556 * amdgpu_dm_atomic_check() - Atomic check implementation for AMDgpu DM.
8572 * Note that DM adds the affected connectors for all CRTCs in state, when that
8584 struct dc *dc = adev->dm.dc; in amdgpu_dm_atomic_check()
8713 ret = dm_update_crtc_state(&adev->dm, state, crtc, in amdgpu_dm_atomic_check()
8724 ret = dm_update_crtc_state(&adev->dm, state, crtc, in amdgpu_dm_atomic_check()
8802 * TODO: Remove this stall and drop DM state private objects. in amdgpu_dm_atomic_check()
8844 * the DM atomic state from validation we need to free it and in amdgpu_dm_atomic_check()
8847 * Furthermore, since the DM atomic state only contains the DC in amdgpu_dm_atomic_check()
8856 if (obj->funcs == adev->dm.atomic_obj.funcs) { in amdgpu_dm_atomic_check()
8962 if (!adev->dm.freesync_module) in amdgpu_dm_update_freesync_caps()
8971 adev->dm.dc, in amdgpu_dm_update_freesync_caps()
9143 static bool amdgpu_dm_psr_disable_all(struct amdgpu_display_manager *dm) in amdgpu_dm_psr_disable_all() argument
9146 return dc_set_psr_allow_active(dm->dc, false); in amdgpu_dm_psr_disable_all()
9152 struct dc *dc = adev->dm.dc; in amdgpu_dm_trigger_timing_sync()
9155 mutex_lock(&adev->dm.dc_lock); in amdgpu_dm_trigger_timing_sync()
9160 adev->dm.force_timing_sync; in amdgpu_dm_trigger_timing_sync()
9165 mutex_unlock(&adev->dm.dc_lock); in amdgpu_dm_trigger_timing_sync()