amd/amdgpu/psp_gfx_if.h

64 *  SRBM-to-PSP mailbox registers (total 8 registers).
70     volatile uint32_t   rbi_rptr;         /* +8   Read pointer (index) of RBI ring */
109 …ddr_lo;        /* bits [31:0] of the GPU Virtual address of the TA binary (must be 4 KB aligned) */
112 …f_phy_addr_lo;    /* bits [31:0] of the GPU Virtual address of CMD buffer (must be 4 KB aligned) */
114 …_t        cmd_buf_len;            /* length of the CMD buffer in bytes; must be multiple of 4 KB */
135 …uf_phy_addr_lo;       /* bits [31:0] of GPU Virtual address of the buffer (must be 4 KB aligned) */
137 …uint32_t        buf_size;              /* buffer size in bytes (must be multiple of 4 KB and no bi…
150 …e;                  /* total size of all buffers in the list in bytes (must be multiple of 4 KB) */
169 …uf_phy_addr_lo;       /* bits [31:0] of GPU Virtual address of TMR buffer (must be 4 KB aligned) */
171     uint32_t        buf_size;              /* buffer size in bytes (must be multiple of 4 KB) */
186 	GFX_FW_TYPE_RLC_G       = 8,    /* RLC-G                    VG + RV */
243 …  fw_phy_addr_lo;    /* bits [31:0] of GPU Virtual address of FW location (must be 4 KB aligned) */
254 …; /* bits [31:0] of FB address of GART memory used as save/restore buffer (must be 4 KB aligned) */
269 …_phy_addr_lo;        /* bits [31:0] of GPU Virtual address of FW location (must be 4 KB aligned) */
296 …uint32_t	fw_addr_lo;	/* +8  bits [31:0] of FW address within TMR (in response to cmd_load_ip_fw co…
312     uint32_t        cmd_id;             /* +8  command ID */
316 …f_addr_lo;   /* +12 bits [31:0] of GPU Virtual address of response buffer (must be 4 KB aligned) */
341 …f_addr_lo;    /* +0  bits [31:0] of GPU Virtual address of command buffer (must be 4 KB aligned) */
343     uint32_t    cmd_buf_size;       /* +8  command buffer size in bytes */