Lines Matching +full:32 +full:- +full:63
46 GFX_CTRL_CMD_ID_ENABLE_INT = 0x00050000, /* enable PSP-to-Gfx interrupt */
47 GFX_CTRL_CMD_ID_DISABLE_INT = 0x00060000, /* disable PSP-to-Gfx interrupt */
57 /*-----------------------------------------------------------------------------
64 * SRBM-to-PSP mailbox registers (total 8 registers).
74 …volatile uint32_t ring_addr_hi; /* +24 bits [63:32] of GPU Virtual of ring buffer (VMID=0) …
110 …uint32_t app_phy_addr_hi; /* bits [63:32] of the GPU Virtual address of the TA binar…
113 …uint32_t cmd_buf_phy_addr_hi; /* bits [63:32] of the GPU Virtual address of CMD buffer */
136 uint32_t buf_phy_addr_hi; /* bits [63:32] of GPU Virtual address of the buffer */
170 uint32_t buf_phy_addr_hi; /* bits [63:32] of GPU Virtual address of TMR buffer */
179 GFX_FW_TYPE_CP_ME = 1, /* CP-ME VG + RV */
180 GFX_FW_TYPE_CP_PFP = 2, /* CP-PFP VG + RV */
181 GFX_FW_TYPE_CP_CE = 3, /* CP-CE VG + RV */
182 GFX_FW_TYPE_CP_MEC = 4, /* CP-MEC FW VG + RV */
183 GFX_FW_TYPE_CP_MEC_ME1 = 5, /* CP-MEC Jump Table 1 VG + RV */
184 GFX_FW_TYPE_CP_MEC_ME2 = 6, /* CP-MEC Jump Table 2 VG */
185 GFX_FW_TYPE_RLC_V = 7, /* RLC-V VG */
186 GFX_FW_TYPE_RLC_G = 8, /* RLC-G VG + RV */
189 GFX_FW_TYPE_DMCU_ERAM = 11, /* DMCU-ERAM VG + RV */
190 GFX_FW_TYPE_DMCU_ISR = 12, /* DMCU-ISR VG + RV */
201 GFX_FW_TYPE_UVD1 = 23, /* UVD1 VG-20 */
202 GFX_FW_TYPE_TOC = 24, /* TOC NV-10 */
210 GFX_FW_TYPE_SDMA1_JT = 32, /* SDNA1 JT NV */
244 …uint32_t fw_phy_addr_hi; /* bits [63:32] of GPU Virtual address of FW location */
255 …uint32_t save_restore_addr_hi; /* bits [63:32] of FB address of GART memory used as…
270 uint32_t toc_phy_addr_hi; /* bits [63:32] of GPU Virtual address of FW location */
297 …uint32_t fw_addr_hi; /* +12 bits [63:32] of FW address within TMR (in response to cmd_load_ip_fw c…
302 /* total 32 bytes */
317 …uint32_t resp_buf_addr_hi; /* +16 bits [63:32] of GPU Virtual address of response buffer …
323 uint8_t reserved_1[864 - sizeof(union psp_gfx_commands) - 28];
330 uint8_t reserved_2[1024 - 864 - sizeof(struct psp_gfx_resp)];
342 uint32_t cmd_buf_addr_hi; /* +4 bits [63:32] of GPU Virtual address of command buffer */
345 …uint32_t fence_addr_hi; /* +16 bits [63:32] of GPU Virtual address of Fence for this frame…
348 uint32_t sid_hi; /* +28 bits [63:32] of SID value (used only for RBI frames) */
349 …uint8_t vmid; /* +32 VMID value used for mapping of all addresses for this frame…