Lines Matching +full:no +full:- +full:hpd
16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
69 mmDC_HPD1_INT_STATUS - mmDC_HPD1_INT_STATUS,
70 mmDC_HPD2_INT_STATUS - mmDC_HPD1_INT_STATUS,
71 mmDC_HPD3_INT_STATUS - mmDC_HPD1_INT_STATUS,
72 mmDC_HPD4_INT_STATUS - mmDC_HPD1_INT_STATUS,
73 mmDC_HPD5_INT_STATUS - mmDC_HPD1_INT_STATUS,
74 mmDC_HPD6_INT_STATUS - mmDC_HPD1_INT_STATUS,
84 (0x13830 - 0x7030) >> 2,
91 uint32_t hpd; member
97 .hpd = DISP_INTERRUPT_STATUS__DC_HPD1_INTERRUPT_MASK
102 .hpd = DISP_INTERRUPT_STATUS_CONTINUE__DC_HPD2_INTERRUPT_MASK
107 .hpd = DISP_INTERRUPT_STATUS_CONTINUE2__DC_HPD3_INTERRUPT_MASK
112 .hpd = DISP_INTERRUPT_STATUS_CONTINUE3__DC_HPD4_INTERRUPT_MASK
117 .hpd = DISP_INTERRUPT_STATUS_CONTINUE4__DC_HPD5_INTERRUPT_MASK
122 .hpd = DISP_INTERRUPT_STATUS_CONTINUE5__DC_HPD6_INTERRUPT_MASK
131 spin_lock_irqsave(&adev->audio_endpt_idx_lock, flags); in dce_v6_0_audio_endpt_rreg()
134 spin_unlock_irqrestore(&adev->audio_endpt_idx_lock, flags); in dce_v6_0_audio_endpt_rreg()
144 spin_lock_irqsave(&adev->audio_endpt_idx_lock, flags); in dce_v6_0_audio_endpt_wreg()
148 spin_unlock_irqrestore(&adev->audio_endpt_idx_lock, flags); in dce_v6_0_audio_endpt_wreg()
153 if (crtc >= adev->mode_info.num_crtc) in dce_v6_0_vblank_get_counter()
164 for (i = 0; i < adev->mode_info.num_crtc; i++) in dce_v6_0_pageflip_interrupt_init()
165 amdgpu_irq_get(adev, &adev->pageflip_irq, i); in dce_v6_0_pageflip_interrupt_init()
173 for (i = 0; i < adev->mode_info.num_crtc; i++) in dce_v6_0_pageflip_interrupt_fini()
174 amdgpu_irq_put(adev, &adev->pageflip_irq, i); in dce_v6_0_pageflip_interrupt_fini()
178 * dce_v6_0_page_flip - pageflip callback.
193 struct amdgpu_crtc *amdgpu_crtc = adev->mode_info.crtcs[crtc_id]; in dce_v6_0_page_flip()
194 struct drm_framebuffer *fb = amdgpu_crtc->base.primary->fb; in dce_v6_0_page_flip()
197 WREG32(mmGRPH_FLIP_CONTROL + amdgpu_crtc->crtc_offset, async ? in dce_v6_0_page_flip()
200 WREG32(mmGRPH_PITCH + amdgpu_crtc->crtc_offset, in dce_v6_0_page_flip()
201 fb->pitches[0] / fb->format->cpp[0]); in dce_v6_0_page_flip()
203 WREG32(mmGRPH_PRIMARY_SURFACE_ADDRESS_HIGH + amdgpu_crtc->crtc_offset, in dce_v6_0_page_flip()
205 WREG32(mmGRPH_PRIMARY_SURFACE_ADDRESS + amdgpu_crtc->crtc_offset, in dce_v6_0_page_flip()
209 RREG32(mmGRPH_PRIMARY_SURFACE_ADDRESS + amdgpu_crtc->crtc_offset); in dce_v6_0_page_flip()
215 if ((crtc < 0) || (crtc >= adev->mode_info.num_crtc)) in dce_v6_0_crtc_get_scanoutpos()
216 return -EINVAL; in dce_v6_0_crtc_get_scanoutpos()
225 * dce_v6_0_hpd_sense - hpd sense callback.
228 * @hpd: hpd (hotplug detect) pin
234 enum amdgpu_hpd_id hpd) in dce_v6_0_hpd_sense() argument
238 if (hpd >= adev->mode_info.num_hpd) in dce_v6_0_hpd_sense()
241 if (RREG32(mmDC_HPD1_INT_STATUS + hpd_offsets[hpd]) & DC_HPD1_INT_STATUS__DC_HPD1_SENSE_MASK) in dce_v6_0_hpd_sense()
248 * dce_v6_0_hpd_set_polarity - hpd set polarity callback.
251 * @hpd: hpd (hotplug detect) pin
253 * Set the polarity of the hpd pin (evergreen+).
256 enum amdgpu_hpd_id hpd) in dce_v6_0_hpd_set_polarity() argument
259 bool connected = dce_v6_0_hpd_sense(adev, hpd); in dce_v6_0_hpd_set_polarity()
261 if (hpd >= adev->mode_info.num_hpd) in dce_v6_0_hpd_set_polarity()
264 tmp = RREG32(mmDC_HPD1_INT_CONTROL + hpd_offsets[hpd]); in dce_v6_0_hpd_set_polarity()
269 WREG32(mmDC_HPD1_INT_CONTROL + hpd_offsets[hpd], tmp); in dce_v6_0_hpd_set_polarity()
273 * dce_v6_0_hpd_init - hpd setup callback.
277 * Setup the hpd pins used by the card (evergreen+).
278 * Enable the pin, set the polarity, and enable the hpd interrupts.
291 if (amdgpu_connector->hpd.hpd >= adev->mode_info.num_hpd) in dce_v6_0_hpd_init()
294 tmp = RREG32(mmDC_HPD1_CONTROL + hpd_offsets[amdgpu_connector->hpd.hpd]); in dce_v6_0_hpd_init()
296 WREG32(mmDC_HPD1_CONTROL + hpd_offsets[amdgpu_connector->hpd.hpd], tmp); in dce_v6_0_hpd_init()
298 if (connector->connector_type == DRM_MODE_CONNECTOR_eDP || in dce_v6_0_hpd_init()
299 connector->connector_type == DRM_MODE_CONNECTOR_LVDS) { in dce_v6_0_hpd_init()
300 /* don't try to enable hpd on eDP or LVDS avoid breaking the in dce_v6_0_hpd_init()
305 tmp = RREG32(mmDC_HPD1_INT_CONTROL + hpd_offsets[amdgpu_connector->hpd.hpd]); in dce_v6_0_hpd_init()
307 WREG32(mmDC_HPD1_INT_CONTROL + hpd_offsets[amdgpu_connector->hpd.hpd], tmp); in dce_v6_0_hpd_init()
311 dce_v6_0_hpd_set_polarity(adev, amdgpu_connector->hpd.hpd); in dce_v6_0_hpd_init()
312 amdgpu_irq_get(adev, &adev->hpd_irq, amdgpu_connector->hpd.hpd); in dce_v6_0_hpd_init()
318 * dce_v6_0_hpd_fini - hpd tear down callback.
322 * Tear down the hpd pins used by the card (evergreen+).
323 * Disable the hpd interrupts.
336 if (amdgpu_connector->hpd.hpd >= adev->mode_info.num_hpd) in dce_v6_0_hpd_fini()
339 tmp = RREG32(mmDC_HPD1_CONTROL + hpd_offsets[amdgpu_connector->hpd.hpd]); in dce_v6_0_hpd_fini()
341 WREG32(mmDC_HPD1_CONTROL + hpd_offsets[amdgpu_connector->hpd.hpd], 0); in dce_v6_0_hpd_fini()
343 amdgpu_irq_put(adev, &adev->hpd_irq, amdgpu_connector->hpd.hpd); in dce_v6_0_hpd_fini()
364 switch (adev->asic_type) { in dce_v6_0_get_num_crtc()
403 struct drm_device *dev = encoder->dev; in dce_v6_0_program_fmt()
407 struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(encoder->crtc); in dce_v6_0_program_fmt()
415 dither = amdgpu_connector->dither; in dce_v6_0_program_fmt()
419 if (amdgpu_encoder->devices & ATOM_DEVICE_LCD_SUPPORT) in dce_v6_0_program_fmt()
454 WREG32(mmFMT_BIT_DEPTH_CONTROL + amdgpu_crtc->crtc_offset, tmp); in dce_v6_0_program_fmt()
458 * cik_get_number_of_dram_channels - get the number of dram channels
510 * dce_v6_0_dram_bandwidth - get the dram bandwidth
526 yclk.full = dfixed_const(wm->yclk); in dce_v6_0_dram_bandwidth()
528 dram_channels.full = dfixed_const(wm->dram_channels * 4); in dce_v6_0_dram_bandwidth()
539 * dce_v6_0_dram_bandwidth_for_display - get the dram bandwidth for display
555 yclk.full = dfixed_const(wm->yclk); in dce_v6_0_dram_bandwidth_for_display()
557 dram_channels.full = dfixed_const(wm->dram_channels * 4); in dce_v6_0_dram_bandwidth_for_display()
568 * dce_v6_0_data_return_bandwidth - get the data return bandwidth
584 sclk.full = dfixed_const(wm->sclk); in dce_v6_0_data_return_bandwidth()
597 * dce_v6_0_dmif_request_bandwidth - get the dmif bandwidth
613 disp_clk.full = dfixed_const(wm->disp_clk); in dce_v6_0_dmif_request_bandwidth()
628 * dce_v6_0_available_bandwidth - get the min available bandwidth
647 * dce_v6_0_average_bandwidth - get the average available bandwidth
668 line_time.full = dfixed_const(wm->active_time + wm->blank_time); in dce_v6_0_average_bandwidth()
670 bpp.full = dfixed_const(wm->bytes_per_pixel); in dce_v6_0_average_bandwidth()
671 src_width.full = dfixed_const(wm->src_width); in dce_v6_0_average_bandwidth()
673 bandwidth.full = dfixed_mul(bandwidth, wm->vsc); in dce_v6_0_average_bandwidth()
680 * dce_v6_0_latency_watermark - get the latency watermark
695 u32 dc_latency = 40000000 / wm->disp_clk; /* dc pipe latency */ in dce_v6_0_latency_watermark()
696 u32 other_heads_data_return_time = ((wm->num_heads + 1) * worst_chunk_return_time) + in dce_v6_0_latency_watermark()
697 (wm->num_heads * cursor_line_pair_return_time); in dce_v6_0_latency_watermark()
703 if (wm->num_heads == 0) in dce_v6_0_latency_watermark()
708 if ((wm->vsc.full > a.full) || in dce_v6_0_latency_watermark()
709 ((wm->vsc.full > b.full) && (wm->vtaps >= 3)) || in dce_v6_0_latency_watermark()
710 (wm->vtaps >= 5) || in dce_v6_0_latency_watermark()
711 ((wm->vsc.full >= a.full) && wm->interlaced)) in dce_v6_0_latency_watermark()
717 b.full = dfixed_const(wm->num_heads); in dce_v6_0_latency_watermark()
719 tmp = div_u64((u64) dmif_size * (u64) wm->disp_clk, mc_latency + 512); in dce_v6_0_latency_watermark()
722 lb_fill_bw = min(tmp, wm->disp_clk * wm->bytes_per_pixel / 1000); in dce_v6_0_latency_watermark()
724 a.full = dfixed_const(max_src_lines_per_dst_line * wm->src_width * wm->bytes_per_pixel); in dce_v6_0_latency_watermark()
731 if (line_fill_time < wm->active_time) in dce_v6_0_latency_watermark()
734 return latency + (line_fill_time - wm->active_time); in dce_v6_0_latency_watermark()
739 * dce_v6_0_average_bandwidth_vs_dram_bandwidth_for_display - check
752 (dce_v6_0_dram_bandwidth_for_display(wm) / wm->num_heads)) in dce_v6_0_average_bandwidth_vs_dram_bandwidth_for_display()
759 * dce_v6_0_average_bandwidth_vs_available_bandwidth - check
772 (dce_v6_0_available_bandwidth(wm) / wm->num_heads)) in dce_v6_0_average_bandwidth_vs_available_bandwidth()
779 * dce_v6_0_check_latency_hiding - check latency hiding
789 u32 lb_partitions = wm->lb_size / wm->src_width; in dce_v6_0_check_latency_hiding()
790 u32 line_time = wm->active_time + wm->blank_time; in dce_v6_0_check_latency_hiding()
796 if (wm->vsc.full > a.full) in dce_v6_0_check_latency_hiding()
799 if (lb_partitions <= (wm->vtaps + 1)) in dce_v6_0_check_latency_hiding()
805 latency_hiding = (latency_tolerant_lines * line_time + wm->blank_time); in dce_v6_0_check_latency_hiding()
814 * dce_v6_0_program_watermarks - program display watermarks
828 struct drm_display_mode *mode = &amdgpu_crtc->base.mode; in dce_v6_0_program_watermarks()
840 if (amdgpu_crtc->base.enabled && num_heads && mode) { in dce_v6_0_program_watermarks()
841 active_time = (u32) div_u64((u64)mode->crtc_hdisplay * 1000000, in dce_v6_0_program_watermarks()
842 (u32)mode->clock); in dce_v6_0_program_watermarks()
843 line_time = (u32) div_u64((u64)mode->crtc_htotal * 1000000, in dce_v6_0_program_watermarks()
844 (u32)mode->clock); in dce_v6_0_program_watermarks()
852 if (adev->pm.dpm_enabled) { in dce_v6_0_program_watermarks()
858 wm_high.yclk = adev->pm.current_mclk * 10; in dce_v6_0_program_watermarks()
859 wm_high.sclk = adev->pm.current_sclk * 10; in dce_v6_0_program_watermarks()
862 wm_high.disp_clk = mode->clock; in dce_v6_0_program_watermarks()
863 wm_high.src_width = mode->crtc_hdisplay; in dce_v6_0_program_watermarks()
865 wm_high.blank_time = line_time - wm_high.active_time; in dce_v6_0_program_watermarks()
867 if (mode->flags & DRM_MODE_FLAG_INTERLACE) in dce_v6_0_program_watermarks()
869 wm_high.vsc = amdgpu_crtc->vsc; in dce_v6_0_program_watermarks()
871 if (amdgpu_crtc->rmx_type != RMX_OFF) in dce_v6_0_program_watermarks()
878 if (adev->pm.dpm_enabled) { in dce_v6_0_program_watermarks()
885 wm_low.yclk = adev->pm.current_mclk * 10; in dce_v6_0_program_watermarks()
886 wm_low.sclk = adev->pm.current_sclk * 10; in dce_v6_0_program_watermarks()
889 wm_low.disp_clk = mode->clock; in dce_v6_0_program_watermarks()
890 wm_low.src_width = mode->crtc_hdisplay; in dce_v6_0_program_watermarks()
892 wm_low.blank_time = line_time - wm_low.active_time; in dce_v6_0_program_watermarks()
894 if (mode->flags & DRM_MODE_FLAG_INTERLACE) in dce_v6_0_program_watermarks()
896 wm_low.vsc = amdgpu_crtc->vsc; in dce_v6_0_program_watermarks()
898 if (amdgpu_crtc->rmx_type != RMX_OFF) in dce_v6_0_program_watermarks()
915 (adev->mode_info.disp_priority == 2)) { in dce_v6_0_program_watermarks()
923 (adev->mode_info.disp_priority == 2)) { in dce_v6_0_program_watermarks()
930 b.full = dfixed_const(mode->clock); in dce_v6_0_program_watermarks()
934 c.full = dfixed_mul(c, amdgpu_crtc->hsc); in dce_v6_0_program_watermarks()
942 b.full = dfixed_const(mode->clock); in dce_v6_0_program_watermarks()
946 c.full = dfixed_mul(c, amdgpu_crtc->hsc); in dce_v6_0_program_watermarks()
953 lb_vblank_lead_lines = DIV_ROUND_UP(lb_size, mode->crtc_hdisplay); in dce_v6_0_program_watermarks()
957 arb_control3 = RREG32(mmDPG_PIPE_ARBITRATION_CONTROL3 + amdgpu_crtc->crtc_offset); in dce_v6_0_program_watermarks()
961 WREG32(mmDPG_PIPE_ARBITRATION_CONTROL3 + amdgpu_crtc->crtc_offset, tmp); in dce_v6_0_program_watermarks()
962 WREG32(mmDPG_PIPE_URGENCY_CONTROL + amdgpu_crtc->crtc_offset, in dce_v6_0_program_watermarks()
966 tmp = RREG32(mmDPG_PIPE_ARBITRATION_CONTROL3 + amdgpu_crtc->crtc_offset); in dce_v6_0_program_watermarks()
969 WREG32(mmDPG_PIPE_ARBITRATION_CONTROL3 + amdgpu_crtc->crtc_offset, tmp); in dce_v6_0_program_watermarks()
970 WREG32(mmDPG_PIPE_URGENCY_CONTROL + amdgpu_crtc->crtc_offset, in dce_v6_0_program_watermarks()
974 WREG32(mmDPG_PIPE_ARBITRATION_CONTROL3 + amdgpu_crtc->crtc_offset, arb_control3); in dce_v6_0_program_watermarks()
977 WREG32(mmPRIORITY_A_CNT + amdgpu_crtc->crtc_offset, priority_a_cnt); in dce_v6_0_program_watermarks()
978 WREG32(mmPRIORITY_B_CNT + amdgpu_crtc->crtc_offset, priority_b_cnt); in dce_v6_0_program_watermarks()
981 amdgpu_crtc->line_time = line_time; in dce_v6_0_program_watermarks()
982 amdgpu_crtc->wm_high = latency_watermark_a; in dce_v6_0_program_watermarks()
985 amdgpu_crtc->lb_vblank_lead_lines = lb_vblank_lead_lines; in dce_v6_0_program_watermarks()
995 u32 pipe_offset = amdgpu_crtc->crtc_id * 0x8; in dce_v6_0_line_buffer_adjust()
1002 * 0 - half lb in dce_v6_0_line_buffer_adjust()
1003 * 2 - whole lb, other crtc must be disabled in dce_v6_0_line_buffer_adjust()
1007 * non-linked crtcs for maximum line buffer allocation. in dce_v6_0_line_buffer_adjust()
1009 if (amdgpu_crtc->base.enabled && mode) { in dce_v6_0_line_buffer_adjust()
1022 WREG32(mmDC_LB_MEMORY_SPLIT + amdgpu_crtc->crtc_offset, in dce_v6_0_line_buffer_adjust()
1027 for (i = 0; i < adev->usec_timeout; i++) { in dce_v6_0_line_buffer_adjust()
1034 if (amdgpu_crtc->base.enabled && mode) { in dce_v6_0_line_buffer_adjust()
1044 /* controller not enabled, so no lb used */ in dce_v6_0_line_buffer_adjust()
1051 * dce_v6_0_bandwidth_update - program display watermarks
1065 if (!adev->mode_info.mode_config_initialized) in dce_v6_0_bandwidth_update()
1070 for (i = 0; i < adev->mode_info.num_crtc; i++) { in dce_v6_0_bandwidth_update()
1071 if (adev->mode_info.crtcs[i]->base.enabled) in dce_v6_0_bandwidth_update()
1074 for (i = 0; i < adev->mode_info.num_crtc; i += 2) { in dce_v6_0_bandwidth_update()
1075 mode0 = &adev->mode_info.crtcs[i]->base.mode; in dce_v6_0_bandwidth_update()
1076 mode1 = &adev->mode_info.crtcs[i+1]->base.mode; in dce_v6_0_bandwidth_update()
1077 lb_size = dce_v6_0_line_buffer_adjust(adev, adev->mode_info.crtcs[i], mode0, mode1); in dce_v6_0_bandwidth_update()
1078 dce_v6_0_program_watermarks(adev, adev->mode_info.crtcs[i], lb_size, num_heads); in dce_v6_0_bandwidth_update()
1079 lb_size = dce_v6_0_line_buffer_adjust(adev, adev->mode_info.crtcs[i+1], mode1, mode0); in dce_v6_0_bandwidth_update()
1080 dce_v6_0_program_watermarks(adev, adev->mode_info.crtcs[i+1], lb_size, num_heads); in dce_v6_0_bandwidth_update()
1089 for (i = 0; i < adev->mode_info.audio.num_pins; i++) { in dce_v6_0_audio_get_connected_pins()
1090 tmp = RREG32_AUDIO_ENDPT(adev->mode_info.audio.pin[i].offset, in dce_v6_0_audio_get_connected_pins()
1094 adev->mode_info.audio.pin[i].connected = false; in dce_v6_0_audio_get_connected_pins()
1096 adev->mode_info.audio.pin[i].connected = true; in dce_v6_0_audio_get_connected_pins()
1107 for (i = 0; i < adev->mode_info.audio.num_pins; i++) { in dce_v6_0_audio_get_pin()
1108 if (adev->mode_info.audio.pin[i].connected) in dce_v6_0_audio_get_pin()
1109 return &adev->mode_info.audio.pin[i]; in dce_v6_0_audio_get_pin()
1111 DRM_ERROR("No connected audio pins found!\n"); in dce_v6_0_audio_get_pin()
1117 struct amdgpu_device *adev = drm_to_adev(encoder->dev); in dce_v6_0_audio_select_pin()
1119 struct amdgpu_encoder_atom_dig *dig = amdgpu_encoder->enc_priv; in dce_v6_0_audio_select_pin()
1121 if (!dig || !dig->afmt || !dig->afmt->pin) in dce_v6_0_audio_select_pin()
1124 WREG32(mmAFMT_AUDIO_SRC_CONTROL + dig->afmt->offset, in dce_v6_0_audio_select_pin()
1126 dig->afmt->pin->id)); in dce_v6_0_audio_select_pin()
1132 struct drm_device *dev = encoder->dev; in dce_v6_0_audio_write_latency_fields()
1135 struct amdgpu_encoder_atom_dig *dig = amdgpu_encoder->enc_priv; in dce_v6_0_audio_write_latency_fields()
1144 if (connector->encoder == encoder) { in dce_v6_0_audio_write_latency_fields()
1156 if (mode->flags & DRM_MODE_FLAG_INTERLACE) in dce_v6_0_audio_write_latency_fields()
1159 if (connector->latency_present[interlace]) { in dce_v6_0_audio_write_latency_fields()
1161 VIDEO_LIPSYNC, connector->video_latency[interlace]); in dce_v6_0_audio_write_latency_fields()
1163 AUDIO_LIPSYNC, connector->audio_latency[interlace]); in dce_v6_0_audio_write_latency_fields()
1170 WREG32_AUDIO_ENDPT(dig->afmt->pin->offset, in dce_v6_0_audio_write_latency_fields()
1176 struct drm_device *dev = encoder->dev; in dce_v6_0_audio_write_speaker_allocation()
1179 struct amdgpu_encoder_atom_dig *dig = amdgpu_encoder->enc_priv; in dce_v6_0_audio_write_speaker_allocation()
1189 if (connector->encoder == encoder) { in dce_v6_0_audio_write_speaker_allocation()
1208 tmp = RREG32_AUDIO_ENDPT(dig->afmt->pin->offset, in dce_v6_0_audio_write_speaker_allocation()
1215 if (connector->connector_type == DRM_MODE_CONNECTOR_DisplayPort) in dce_v6_0_audio_write_speaker_allocation()
1229 WREG32_AUDIO_ENDPT(dig->afmt->pin->offset, in dce_v6_0_audio_write_speaker_allocation()
1237 struct drm_device *dev = encoder->dev; in dce_v6_0_audio_write_sad_regs()
1240 struct amdgpu_encoder_atom_dig *dig = amdgpu_encoder->enc_priv; in dce_v6_0_audio_write_sad_regs()
1264 if (connector->encoder == encoder) { in dce_v6_0_audio_write_sad_regs()
1285 int max_channels = -1; in dce_v6_0_audio_write_sad_regs()
1291 if (sad->format == eld_reg_to_type[i][1]) { in dce_v6_0_audio_write_sad_regs()
1292 if (sad->channels > max_channels) { in dce_v6_0_audio_write_sad_regs()
1294 MAX_CHANNELS, sad->channels); in dce_v6_0_audio_write_sad_regs()
1296 DESCRIPTOR_BYTE_2, sad->byte2); in dce_v6_0_audio_write_sad_regs()
1298 SUPPORTED_FREQUENCIES, sad->freq); in dce_v6_0_audio_write_sad_regs()
1299 max_channels = sad->channels; in dce_v6_0_audio_write_sad_regs()
1302 if (sad->format == HDMI_AUDIO_CODING_TYPE_PCM) in dce_v6_0_audio_write_sad_regs()
1303 stereo_freqs |= sad->freq; in dce_v6_0_audio_write_sad_regs()
1311 WREG32_AUDIO_ENDPT(dig->afmt->pin->offset, eld_reg_to_type[i][0], tmp); in dce_v6_0_audio_write_sad_regs()
1325 WREG32_AUDIO_ENDPT(pin->offset, ixAZALIA_F0_CODEC_PIN_CONTROL_HOT_PLUG_CONTROL, in dce_v6_0_audio_enable()
1331 (0x1780 - 0x1780),
1332 (0x1786 - 0x1780),
1333 (0x178c - 0x1780),
1334 (0x1792 - 0x1780),
1335 (0x1798 - 0x1780),
1336 (0x179d - 0x1780),
1337 (0x17a4 - 0x1780),
1347 adev->mode_info.audio.enabled = true; in dce_v6_0_audio_init()
1349 switch (adev->asic_type) { in dce_v6_0_audio_init()
1354 adev->mode_info.audio.num_pins = 6; in dce_v6_0_audio_init()
1357 adev->mode_info.audio.num_pins = 2; in dce_v6_0_audio_init()
1361 for (i = 0; i < adev->mode_info.audio.num_pins; i++) { in dce_v6_0_audio_init()
1362 adev->mode_info.audio.pin[i].channels = -1; in dce_v6_0_audio_init()
1363 adev->mode_info.audio.pin[i].rate = -1; in dce_v6_0_audio_init()
1364 adev->mode_info.audio.pin[i].bits_per_sample = -1; in dce_v6_0_audio_init()
1365 adev->mode_info.audio.pin[i].status_bits = 0; in dce_v6_0_audio_init()
1366 adev->mode_info.audio.pin[i].category_code = 0; in dce_v6_0_audio_init()
1367 adev->mode_info.audio.pin[i].connected = false; in dce_v6_0_audio_init()
1368 adev->mode_info.audio.pin[i].offset = pin_offsets[i]; in dce_v6_0_audio_init()
1369 adev->mode_info.audio.pin[i].id = i; in dce_v6_0_audio_init()
1370 dce_v6_0_audio_enable(adev, &adev->mode_info.audio.pin[i], false); in dce_v6_0_audio_init()
1383 if (!adev->mode_info.audio.enabled) in dce_v6_0_audio_fini()
1386 for (i = 0; i < adev->mode_info.audio.num_pins; i++) in dce_v6_0_audio_fini()
1387 dce_v6_0_audio_enable(adev, &adev->mode_info.audio.pin[i], false); in dce_v6_0_audio_fini()
1389 adev->mode_info.audio.enabled = false; in dce_v6_0_audio_fini()
1394 struct drm_device *dev = encoder->dev; in dce_v6_0_audio_set_vbi_packet()
1397 struct amdgpu_encoder_atom_dig *dig = amdgpu_encoder->enc_priv; in dce_v6_0_audio_set_vbi_packet()
1400 tmp = RREG32(mmHDMI_VBI_PACKET_CONTROL + dig->afmt->offset); in dce_v6_0_audio_set_vbi_packet()
1404 WREG32(mmHDMI_VBI_PACKET_CONTROL + dig->afmt->offset, tmp); in dce_v6_0_audio_set_vbi_packet()
1410 struct drm_device *dev = encoder->dev; in dce_v6_0_audio_set_acr()
1414 struct amdgpu_encoder_atom_dig *dig = amdgpu_encoder->enc_priv; in dce_v6_0_audio_set_acr()
1417 tmp = RREG32(mmHDMI_ACR_PACKET_CONTROL + dig->afmt->offset); in dce_v6_0_audio_set_acr()
1421 WREG32(mmHDMI_ACR_PACKET_CONTROL + dig->afmt->offset, tmp); in dce_v6_0_audio_set_acr()
1423 tmp = RREG32(mmHDMI_ACR_32_0 + dig->afmt->offset); in dce_v6_0_audio_set_acr()
1425 WREG32(mmHDMI_ACR_32_0 + dig->afmt->offset, tmp); in dce_v6_0_audio_set_acr()
1426 tmp = RREG32(mmHDMI_ACR_32_1 + dig->afmt->offset); in dce_v6_0_audio_set_acr()
1428 WREG32(mmHDMI_ACR_32_1 + dig->afmt->offset, tmp); in dce_v6_0_audio_set_acr()
1430 tmp = RREG32(mmHDMI_ACR_44_0 + dig->afmt->offset); in dce_v6_0_audio_set_acr()
1432 WREG32(mmHDMI_ACR_44_0 + dig->afmt->offset, tmp); in dce_v6_0_audio_set_acr()
1433 tmp = RREG32(mmHDMI_ACR_44_1 + dig->afmt->offset); in dce_v6_0_audio_set_acr()
1435 WREG32(mmHDMI_ACR_44_1 + dig->afmt->offset, tmp); in dce_v6_0_audio_set_acr()
1437 tmp = RREG32(mmHDMI_ACR_48_0 + dig->afmt->offset); in dce_v6_0_audio_set_acr()
1439 WREG32(mmHDMI_ACR_48_0 + dig->afmt->offset, tmp); in dce_v6_0_audio_set_acr()
1440 tmp = RREG32(mmHDMI_ACR_48_1 + dig->afmt->offset); in dce_v6_0_audio_set_acr()
1442 WREG32(mmHDMI_ACR_48_1 + dig->afmt->offset, tmp); in dce_v6_0_audio_set_acr()
1448 struct drm_device *dev = encoder->dev; in dce_v6_0_audio_set_avi_infoframe()
1451 struct amdgpu_encoder_atom_dig *dig = amdgpu_encoder->enc_priv; in dce_v6_0_audio_set_avi_infoframe()
1472 WREG32(mmAFMT_AVI_INFO0 + dig->afmt->offset, in dce_v6_0_audio_set_avi_infoframe()
1474 WREG32(mmAFMT_AVI_INFO1 + dig->afmt->offset, in dce_v6_0_audio_set_avi_infoframe()
1476 WREG32(mmAFMT_AVI_INFO2 + dig->afmt->offset, in dce_v6_0_audio_set_avi_infoframe()
1478 WREG32(mmAFMT_AVI_INFO3 + dig->afmt->offset, in dce_v6_0_audio_set_avi_infoframe()
1481 tmp = RREG32(mmHDMI_INFOFRAME_CONTROL1 + dig->afmt->offset); in dce_v6_0_audio_set_avi_infoframe()
1485 WREG32(mmHDMI_INFOFRAME_CONTROL1 + dig->afmt->offset, tmp); in dce_v6_0_audio_set_avi_infoframe()
1490 struct drm_device *dev = encoder->dev; in dce_v6_0_audio_set_dto()
1492 struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(encoder->crtc); in dce_v6_0_audio_set_dto()
1504 DCCG_AUDIO_DTO0_SOURCE_SEL, amdgpu_crtc->crtc_id); in dce_v6_0_audio_set_dto()
1524 struct drm_device *dev = encoder->dev; in dce_v6_0_audio_set_packet()
1527 struct amdgpu_encoder_atom_dig *dig = amdgpu_encoder->enc_priv; in dce_v6_0_audio_set_packet()
1530 tmp = RREG32(mmAFMT_INFOFRAME_CONTROL0 + dig->afmt->offset); in dce_v6_0_audio_set_packet()
1532 WREG32(mmAFMT_INFOFRAME_CONTROL0 + dig->afmt->offset, tmp); in dce_v6_0_audio_set_packet()
1534 tmp = RREG32(mmAFMT_60958_0 + dig->afmt->offset); in dce_v6_0_audio_set_packet()
1536 WREG32(mmAFMT_60958_0 + dig->afmt->offset, tmp); in dce_v6_0_audio_set_packet()
1538 tmp = RREG32(mmAFMT_60958_1 + dig->afmt->offset); in dce_v6_0_audio_set_packet()
1540 WREG32(mmAFMT_60958_1 + dig->afmt->offset, tmp); in dce_v6_0_audio_set_packet()
1542 tmp = RREG32(mmAFMT_60958_2 + dig->afmt->offset); in dce_v6_0_audio_set_packet()
1549 WREG32(mmAFMT_60958_2 + dig->afmt->offset, tmp); in dce_v6_0_audio_set_packet()
1551 tmp = RREG32(mmAFMT_AUDIO_PACKET_CONTROL2 + dig->afmt->offset); in dce_v6_0_audio_set_packet()
1553 WREG32(mmAFMT_AUDIO_PACKET_CONTROL2 + dig->afmt->offset, tmp); in dce_v6_0_audio_set_packet()
1555 tmp = RREG32(mmHDMI_AUDIO_PACKET_CONTROL + dig->afmt->offset); in dce_v6_0_audio_set_packet()
1558 WREG32(mmHDMI_AUDIO_PACKET_CONTROL + dig->afmt->offset, tmp); in dce_v6_0_audio_set_packet()
1560 tmp = RREG32(mmAFMT_AUDIO_PACKET_CONTROL + dig->afmt->offset); in dce_v6_0_audio_set_packet()
1563 WREG32(mmAFMT_AUDIO_PACKET_CONTROL + dig->afmt->offset, tmp); in dce_v6_0_audio_set_packet()
1568 struct drm_device *dev = encoder->dev; in dce_v6_0_audio_set_mute()
1571 struct amdgpu_encoder_atom_dig *dig = amdgpu_encoder->enc_priv; in dce_v6_0_audio_set_mute()
1574 tmp = RREG32(mmHDMI_GC + dig->afmt->offset); in dce_v6_0_audio_set_mute()
1576 WREG32(mmHDMI_GC + dig->afmt->offset, tmp); in dce_v6_0_audio_set_mute()
1581 struct drm_device *dev = encoder->dev; in dce_v6_0_audio_hdmi_enable()
1584 struct amdgpu_encoder_atom_dig *dig = amdgpu_encoder->enc_priv; in dce_v6_0_audio_hdmi_enable()
1588 tmp = RREG32(mmHDMI_INFOFRAME_CONTROL0 + dig->afmt->offset); in dce_v6_0_audio_hdmi_enable()
1593 WREG32(mmHDMI_INFOFRAME_CONTROL0 + dig->afmt->offset, tmp); in dce_v6_0_audio_hdmi_enable()
1595 tmp = RREG32(mmHDMI_INFOFRAME_CONTROL1 + dig->afmt->offset); in dce_v6_0_audio_hdmi_enable()
1597 WREG32(mmHDMI_INFOFRAME_CONTROL1 + dig->afmt->offset, tmp); in dce_v6_0_audio_hdmi_enable()
1599 tmp = RREG32(mmAFMT_AUDIO_PACKET_CONTROL + dig->afmt->offset); in dce_v6_0_audio_hdmi_enable()
1601 WREG32(mmAFMT_AUDIO_PACKET_CONTROL + dig->afmt->offset, tmp); in dce_v6_0_audio_hdmi_enable()
1603 tmp = RREG32(mmHDMI_INFOFRAME_CONTROL0 + dig->afmt->offset); in dce_v6_0_audio_hdmi_enable()
1608 WREG32(mmHDMI_INFOFRAME_CONTROL0 + dig->afmt->offset, tmp); in dce_v6_0_audio_hdmi_enable()
1610 tmp = RREG32(mmAFMT_AUDIO_PACKET_CONTROL + dig->afmt->offset); in dce_v6_0_audio_hdmi_enable()
1612 WREG32(mmAFMT_AUDIO_PACKET_CONTROL + dig->afmt->offset, tmp); in dce_v6_0_audio_hdmi_enable()
1618 struct drm_device *dev = encoder->dev; in dce_v6_0_audio_dp_enable()
1621 struct amdgpu_encoder_atom_dig *dig = amdgpu_encoder->enc_priv; in dce_v6_0_audio_dp_enable()
1625 tmp = RREG32(mmAFMT_AUDIO_PACKET_CONTROL + dig->afmt->offset); in dce_v6_0_audio_dp_enable()
1627 WREG32(mmAFMT_AUDIO_PACKET_CONTROL + dig->afmt->offset, tmp); in dce_v6_0_audio_dp_enable()
1629 tmp = RREG32(mmDP_SEC_TIMESTAMP + dig->afmt->offset); in dce_v6_0_audio_dp_enable()
1631 WREG32(mmDP_SEC_TIMESTAMP + dig->afmt->offset, tmp); in dce_v6_0_audio_dp_enable()
1633 tmp = RREG32(mmDP_SEC_CNTL + dig->afmt->offset); in dce_v6_0_audio_dp_enable()
1638 WREG32(mmDP_SEC_CNTL + dig->afmt->offset, tmp); in dce_v6_0_audio_dp_enable()
1640 WREG32(mmDP_SEC_CNTL + dig->afmt->offset, 0); in dce_v6_0_audio_dp_enable()
1647 struct drm_device *dev = encoder->dev; in dce_v6_0_afmt_setmode()
1650 struct amdgpu_encoder_atom_dig *dig = amdgpu_encoder->enc_priv; in dce_v6_0_afmt_setmode()
1657 if (!dig || !dig->afmt) in dce_v6_0_afmt_setmode()
1662 if (connector->encoder == encoder) { in dce_v6_0_afmt_setmode()
1674 if (!dig->afmt->enabled) in dce_v6_0_afmt_setmode()
1677 dig->afmt->pin = dce_v6_0_audio_get_pin(adev); in dce_v6_0_afmt_setmode()
1678 if (!dig->afmt->pin) in dce_v6_0_afmt_setmode()
1681 if (encoder->crtc) { in dce_v6_0_afmt_setmode()
1682 struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(encoder->crtc); in dce_v6_0_afmt_setmode()
1683 bpc = amdgpu_crtc->bpc; in dce_v6_0_afmt_setmode()
1687 dce_v6_0_audio_enable(adev, dig->afmt->pin, false); in dce_v6_0_afmt_setmode()
1694 dce_v6_0_audio_set_dto(encoder, mode->clock); in dce_v6_0_afmt_setmode()
1696 dce_v6_0_audio_set_acr(encoder, mode->clock, bpc); in dce_v6_0_afmt_setmode()
1698 dce_v6_0_audio_set_dto(encoder, adev->clock.default_dispclk * 10); in dce_v6_0_afmt_setmode()
1711 dce_v6_0_audio_enable(adev, dig->afmt->pin, true); in dce_v6_0_afmt_setmode()
1716 struct drm_device *dev = encoder->dev; in dce_v6_0_afmt_enable()
1719 struct amdgpu_encoder_atom_dig *dig = amdgpu_encoder->enc_priv; in dce_v6_0_afmt_enable()
1721 if (!dig || !dig->afmt) in dce_v6_0_afmt_enable()
1725 if (enable && dig->afmt->enabled) in dce_v6_0_afmt_enable()
1728 if (!enable && !dig->afmt->enabled) in dce_v6_0_afmt_enable()
1731 if (!enable && dig->afmt->pin) { in dce_v6_0_afmt_enable()
1732 dce_v6_0_audio_enable(adev, dig->afmt->pin, false); in dce_v6_0_afmt_enable()
1733 dig->afmt->pin = NULL; in dce_v6_0_afmt_enable()
1736 dig->afmt->enabled = enable; in dce_v6_0_afmt_enable()
1739 enable ? "En" : "Dis", dig->afmt->offset, amdgpu_encoder->encoder_id); in dce_v6_0_afmt_enable()
1746 for (i = 0; i < adev->mode_info.num_dig; i++) in dce_v6_0_afmt_init()
1747 adev->mode_info.afmt[i] = NULL; in dce_v6_0_afmt_init()
1750 for (i = 0; i < adev->mode_info.num_dig; i++) { in dce_v6_0_afmt_init()
1751 adev->mode_info.afmt[i] = kzalloc(sizeof(struct amdgpu_afmt), GFP_KERNEL); in dce_v6_0_afmt_init()
1752 if (adev->mode_info.afmt[i]) { in dce_v6_0_afmt_init()
1753 adev->mode_info.afmt[i]->offset = dig_offsets[i]; in dce_v6_0_afmt_init()
1754 adev->mode_info.afmt[i]->id = i; in dce_v6_0_afmt_init()
1757 kfree(adev->mode_info.afmt[j]); in dce_v6_0_afmt_init()
1758 adev->mode_info.afmt[j] = NULL; in dce_v6_0_afmt_init()
1761 return -ENOMEM; in dce_v6_0_afmt_init()
1771 for (i = 0; i < adev->mode_info.num_dig; i++) { in dce_v6_0_afmt_fini()
1772 kfree(adev->mode_info.afmt[i]); in dce_v6_0_afmt_fini()
1773 adev->mode_info.afmt[i] = NULL; in dce_v6_0_afmt_fini()
1790 struct drm_device *dev = crtc->dev; in dce_v6_0_vga_enable()
1794 vga_control = RREG32(vga_control_regs[amdgpu_crtc->crtc_id]) & ~1; in dce_v6_0_vga_enable()
1795 WREG32(vga_control_regs[amdgpu_crtc->crtc_id], vga_control | (enable ? 1 : 0)); in dce_v6_0_vga_enable()
1801 struct drm_device *dev = crtc->dev; in dce_v6_0_grph_enable()
1804 WREG32(mmGRPH_ENABLE + amdgpu_crtc->crtc_offset, enable ? 1 : 0); in dce_v6_0_grph_enable()
1812 struct drm_device *dev = crtc->dev; in dce_v6_0_crtc_do_set_base()
1825 /* no fb bound */ in dce_v6_0_crtc_do_set_base()
1826 if (!atomic && !crtc->primary->fb) { in dce_v6_0_crtc_do_set_base()
1827 DRM_DEBUG_KMS("No FB bound\n"); in dce_v6_0_crtc_do_set_base()
1834 target_fb = crtc->primary->fb; in dce_v6_0_crtc_do_set_base()
1839 obj = target_fb->obj[0]; in dce_v6_0_crtc_do_set_base()
1849 return -EINVAL; in dce_v6_0_crtc_do_set_base()
1857 switch (target_fb->format->format) { in dce_v6_0_crtc_do_set_base()
1908 /* Greater 8 bpc fb needs to bypass hw-lut to retain precision */ in dce_v6_0_crtc_do_set_base()
1918 /* Greater 8 bpc fb needs to bypass hw-lut to retain precision */ in dce_v6_0_crtc_do_set_base()
1933 drm_get_format_name(target_fb->format->format, &format_name)); in dce_v6_0_crtc_do_set_base()
1934 return -EINVAL; in dce_v6_0_crtc_do_set_base()
1964 WREG32(mmGRPH_FLIP_CONTROL + amdgpu_crtc->crtc_offset, 0); in dce_v6_0_crtc_do_set_base()
1966 WREG32(mmGRPH_PRIMARY_SURFACE_ADDRESS_HIGH + amdgpu_crtc->crtc_offset, in dce_v6_0_crtc_do_set_base()
1968 WREG32(mmGRPH_SECONDARY_SURFACE_ADDRESS_HIGH + amdgpu_crtc->crtc_offset, in dce_v6_0_crtc_do_set_base()
1970 WREG32(mmGRPH_PRIMARY_SURFACE_ADDRESS + amdgpu_crtc->crtc_offset, in dce_v6_0_crtc_do_set_base()
1972 WREG32(mmGRPH_SECONDARY_SURFACE_ADDRESS + amdgpu_crtc->crtc_offset, in dce_v6_0_crtc_do_set_base()
1974 WREG32(mmGRPH_CONTROL + amdgpu_crtc->crtc_offset, fb_format); in dce_v6_0_crtc_do_set_base()
1975 WREG32(mmGRPH_SWAP_CNTL + amdgpu_crtc->crtc_offset, fb_swap); in dce_v6_0_crtc_do_set_base()
1982 WREG32_P(mmGRPH_LUT_10BIT_BYPASS + amdgpu_crtc->crtc_offset, in dce_v6_0_crtc_do_set_base()
1989 WREG32(mmGRPH_SURFACE_OFFSET_X + amdgpu_crtc->crtc_offset, 0); in dce_v6_0_crtc_do_set_base()
1990 WREG32(mmGRPH_SURFACE_OFFSET_Y + amdgpu_crtc->crtc_offset, 0); in dce_v6_0_crtc_do_set_base()
1991 WREG32(mmGRPH_X_START + amdgpu_crtc->crtc_offset, 0); in dce_v6_0_crtc_do_set_base()
1992 WREG32(mmGRPH_Y_START + amdgpu_crtc->crtc_offset, 0); in dce_v6_0_crtc_do_set_base()
1993 WREG32(mmGRPH_X_END + amdgpu_crtc->crtc_offset, target_fb->width); in dce_v6_0_crtc_do_set_base()
1994 WREG32(mmGRPH_Y_END + amdgpu_crtc->crtc_offset, target_fb->height); in dce_v6_0_crtc_do_set_base()
1996 fb_pitch_pixels = target_fb->pitches[0] / target_fb->format->cpp[0]; in dce_v6_0_crtc_do_set_base()
1997 WREG32(mmGRPH_PITCH + amdgpu_crtc->crtc_offset, fb_pitch_pixels); in dce_v6_0_crtc_do_set_base()
2001 WREG32(mmDESKTOP_HEIGHT + amdgpu_crtc->crtc_offset, in dce_v6_0_crtc_do_set_base()
2002 target_fb->height); in dce_v6_0_crtc_do_set_base()
2005 WREG32(mmVIEWPORT_START + amdgpu_crtc->crtc_offset, in dce_v6_0_crtc_do_set_base()
2007 viewport_w = crtc->mode.hdisplay; in dce_v6_0_crtc_do_set_base()
2008 viewport_h = (crtc->mode.vdisplay + 1) & ~1; in dce_v6_0_crtc_do_set_base()
2010 WREG32(mmVIEWPORT_SIZE + amdgpu_crtc->crtc_offset, in dce_v6_0_crtc_do_set_base()
2014 WREG32(mmMASTER_UPDATE_MODE + amdgpu_crtc->crtc_offset, 0); in dce_v6_0_crtc_do_set_base()
2016 if (!atomic && fb && fb != crtc->primary->fb) { in dce_v6_0_crtc_do_set_base()
2017 abo = gem_to_amdgpu_bo(fb->obj[0]); in dce_v6_0_crtc_do_set_base()
2035 struct drm_device *dev = crtc->dev; in dce_v6_0_set_interleave()
2039 if (mode->flags & DRM_MODE_FLAG_INTERLACE) in dce_v6_0_set_interleave()
2040 WREG32(mmDATA_FORMAT + amdgpu_crtc->crtc_offset, in dce_v6_0_set_interleave()
2043 WREG32(mmDATA_FORMAT + amdgpu_crtc->crtc_offset, 0); in dce_v6_0_set_interleave()
2050 struct drm_device *dev = crtc->dev; in dce_v6_0_crtc_load_lut()
2055 DRM_DEBUG_KMS("%d\n", amdgpu_crtc->crtc_id); in dce_v6_0_crtc_load_lut()
2057 WREG32(mmINPUT_CSC_CONTROL + amdgpu_crtc->crtc_offset, in dce_v6_0_crtc_load_lut()
2060 WREG32(mmPRESCALE_GRPH_CONTROL + amdgpu_crtc->crtc_offset, in dce_v6_0_crtc_load_lut()
2062 WREG32(mmPRESCALE_OVL_CONTROL + amdgpu_crtc->crtc_offset, in dce_v6_0_crtc_load_lut()
2064 WREG32(mmINPUT_GAMMA_CONTROL + amdgpu_crtc->crtc_offset, in dce_v6_0_crtc_load_lut()
2068 WREG32(mmDC_LUT_CONTROL + amdgpu_crtc->crtc_offset, 0); in dce_v6_0_crtc_load_lut()
2070 WREG32(mmDC_LUT_BLACK_OFFSET_BLUE + amdgpu_crtc->crtc_offset, 0); in dce_v6_0_crtc_load_lut()
2071 WREG32(mmDC_LUT_BLACK_OFFSET_GREEN + amdgpu_crtc->crtc_offset, 0); in dce_v6_0_crtc_load_lut()
2072 WREG32(mmDC_LUT_BLACK_OFFSET_RED + amdgpu_crtc->crtc_offset, 0); in dce_v6_0_crtc_load_lut()
2074 WREG32(mmDC_LUT_WHITE_OFFSET_BLUE + amdgpu_crtc->crtc_offset, 0xffff); in dce_v6_0_crtc_load_lut()
2075 WREG32(mmDC_LUT_WHITE_OFFSET_GREEN + amdgpu_crtc->crtc_offset, 0xffff); in dce_v6_0_crtc_load_lut()
2076 WREG32(mmDC_LUT_WHITE_OFFSET_RED + amdgpu_crtc->crtc_offset, 0xffff); in dce_v6_0_crtc_load_lut()
2078 WREG32(mmDC_LUT_RW_MODE + amdgpu_crtc->crtc_offset, 0); in dce_v6_0_crtc_load_lut()
2079 WREG32(mmDC_LUT_WRITE_EN_MASK + amdgpu_crtc->crtc_offset, 0x00000007); in dce_v6_0_crtc_load_lut()
2081 WREG32(mmDC_LUT_RW_INDEX + amdgpu_crtc->crtc_offset, 0); in dce_v6_0_crtc_load_lut()
2082 r = crtc->gamma_store; in dce_v6_0_crtc_load_lut()
2083 g = r + crtc->gamma_size; in dce_v6_0_crtc_load_lut()
2084 b = g + crtc->gamma_size; in dce_v6_0_crtc_load_lut()
2086 WREG32(mmDC_LUT_30_COLOR + amdgpu_crtc->crtc_offset, in dce_v6_0_crtc_load_lut()
2092 WREG32(mmDEGAMMA_CONTROL + amdgpu_crtc->crtc_offset, in dce_v6_0_crtc_load_lut()
2097 WREG32(mmGAMUT_REMAP_CONTROL + amdgpu_crtc->crtc_offset, in dce_v6_0_crtc_load_lut()
2100 WREG32(mmREGAMMA_CONTROL + amdgpu_crtc->crtc_offset, in dce_v6_0_crtc_load_lut()
2103 WREG32(mmOUTPUT_CSC_CONTROL + amdgpu_crtc->crtc_offset, in dce_v6_0_crtc_load_lut()
2107 WREG32(0x1a50 + amdgpu_crtc->crtc_offset, 0); in dce_v6_0_crtc_load_lut()
2115 struct amdgpu_encoder_atom_dig *dig = amdgpu_encoder->enc_priv; in dce_v6_0_pick_dig_encoder()
2117 switch (amdgpu_encoder->encoder_id) { in dce_v6_0_pick_dig_encoder()
2119 return dig->linkb ? 1 : 0; in dce_v6_0_pick_dig_encoder()
2121 return dig->linkb ? 3 : 2; in dce_v6_0_pick_dig_encoder()
2123 return dig->linkb ? 5 : 4; in dce_v6_0_pick_dig_encoder()
2127 DRM_ERROR("invalid encoder_id: 0x%x\n", amdgpu_encoder->encoder_id); in dce_v6_0_pick_dig_encoder()
2133 * dce_v6_0_pick_pll - Allocate a PPLL for use by the crtc.
2138 * a single PPLL can be used for all DP crtcs/encoders. For non-DP
2141 * as there is no need to program the PLL itself. If we are not able to
2150 struct drm_device *dev = crtc->dev; in dce_v6_0_pick_pll()
2155 if (ENCODER_MODE_IS_DP(amdgpu_atombios_encoder_get_encoder_mode(amdgpu_crtc->encoder))) { in dce_v6_0_pick_pll()
2156 if (adev->clock.dp_extclk) in dce_v6_0_pick_pll()
2180 struct amdgpu_device *adev = drm_to_adev(crtc->dev); in dce_v6_0_lock_cursor()
2184 cur_lock = RREG32(mmCUR_UPDATE + amdgpu_crtc->crtc_offset); in dce_v6_0_lock_cursor()
2189 WREG32(mmCUR_UPDATE + amdgpu_crtc->crtc_offset, cur_lock); in dce_v6_0_lock_cursor()
2195 struct amdgpu_device *adev = drm_to_adev(crtc->dev); in dce_v6_0_hide_cursor()
2197 WREG32(mmCUR_CONTROL + amdgpu_crtc->crtc_offset, in dce_v6_0_hide_cursor()
2207 struct amdgpu_device *adev = drm_to_adev(crtc->dev); in dce_v6_0_show_cursor()
2209 WREG32(mmCUR_SURFACE_ADDRESS_HIGH + amdgpu_crtc->crtc_offset, in dce_v6_0_show_cursor()
2210 upper_32_bits(amdgpu_crtc->cursor_addr)); in dce_v6_0_show_cursor()
2211 WREG32(mmCUR_SURFACE_ADDRESS + amdgpu_crtc->crtc_offset, in dce_v6_0_show_cursor()
2212 lower_32_bits(amdgpu_crtc->cursor_addr)); in dce_v6_0_show_cursor()
2214 WREG32(mmCUR_CONTROL + amdgpu_crtc->crtc_offset, in dce_v6_0_show_cursor()
2225 struct amdgpu_device *adev = drm_to_adev(crtc->dev); in dce_v6_0_cursor_move_locked()
2228 int w = amdgpu_crtc->cursor_width; in dce_v6_0_cursor_move_locked()
2230 amdgpu_crtc->cursor_x = x; in dce_v6_0_cursor_move_locked()
2231 amdgpu_crtc->cursor_y = y; in dce_v6_0_cursor_move_locked()
2234 x += crtc->x; in dce_v6_0_cursor_move_locked()
2235 y += crtc->y; in dce_v6_0_cursor_move_locked()
2236 DRM_DEBUG("x %d y %d c->x %d c->y %d\n", x, y, crtc->x, crtc->y); in dce_v6_0_cursor_move_locked()
2239 xorigin = min(-x, amdgpu_crtc->max_cursor_width - 1); in dce_v6_0_cursor_move_locked()
2243 yorigin = min(-y, amdgpu_crtc->max_cursor_height - 1); in dce_v6_0_cursor_move_locked()
2247 WREG32(mmCUR_POSITION + amdgpu_crtc->crtc_offset, (x << 16) | y); in dce_v6_0_cursor_move_locked()
2248 WREG32(mmCUR_HOT_SPOT + amdgpu_crtc->crtc_offset, (xorigin << 16) | yorigin); in dce_v6_0_cursor_move_locked()
2249 WREG32(mmCUR_SIZE + amdgpu_crtc->crtc_offset, in dce_v6_0_cursor_move_locked()
2250 ((w - 1) << 16) | (amdgpu_crtc->cursor_height - 1)); in dce_v6_0_cursor_move_locked()
2287 if ((width > amdgpu_crtc->max_cursor_width) || in dce_v6_0_crtc_cursor_set2()
2288 (height > amdgpu_crtc->max_cursor_height)) { in dce_v6_0_crtc_cursor_set2()
2290 return -EINVAL; in dce_v6_0_crtc_cursor_set2()
2295 DRM_ERROR("Cannot find cursor object %x for crtc %d\n", handle, amdgpu_crtc->crtc_id); in dce_v6_0_crtc_cursor_set2()
2296 return -ENOENT; in dce_v6_0_crtc_cursor_set2()
2313 amdgpu_crtc->cursor_addr = amdgpu_bo_gpu_offset(aobj); in dce_v6_0_crtc_cursor_set2()
2317 if (width != amdgpu_crtc->cursor_width || in dce_v6_0_crtc_cursor_set2()
2318 height != amdgpu_crtc->cursor_height || in dce_v6_0_crtc_cursor_set2()
2319 hot_x != amdgpu_crtc->cursor_hot_x || in dce_v6_0_crtc_cursor_set2()
2320 hot_y != amdgpu_crtc->cursor_hot_y) { in dce_v6_0_crtc_cursor_set2()
2323 x = amdgpu_crtc->cursor_x + amdgpu_crtc->cursor_hot_x - hot_x; in dce_v6_0_crtc_cursor_set2()
2324 y = amdgpu_crtc->cursor_y + amdgpu_crtc->cursor_hot_y - hot_y; in dce_v6_0_crtc_cursor_set2()
2328 amdgpu_crtc->cursor_width = width; in dce_v6_0_crtc_cursor_set2()
2329 amdgpu_crtc->cursor_height = height; in dce_v6_0_crtc_cursor_set2()
2330 amdgpu_crtc->cursor_hot_x = hot_x; in dce_v6_0_crtc_cursor_set2()
2331 amdgpu_crtc->cursor_hot_y = hot_y; in dce_v6_0_crtc_cursor_set2()
2338 if (amdgpu_crtc->cursor_bo) { in dce_v6_0_crtc_cursor_set2()
2339 struct amdgpu_bo *aobj = gem_to_amdgpu_bo(amdgpu_crtc->cursor_bo); in dce_v6_0_crtc_cursor_set2()
2345 drm_gem_object_put(amdgpu_crtc->cursor_bo); in dce_v6_0_crtc_cursor_set2()
2348 amdgpu_crtc->cursor_bo = obj; in dce_v6_0_crtc_cursor_set2()
2356 if (amdgpu_crtc->cursor_bo) { in dce_v6_0_cursor_reset()
2359 dce_v6_0_cursor_move_locked(crtc, amdgpu_crtc->cursor_x, in dce_v6_0_cursor_reset()
2360 amdgpu_crtc->cursor_y); in dce_v6_0_cursor_reset()
2399 struct drm_device *dev = crtc->dev; in dce_v6_0_crtc_dpms()
2406 amdgpu_crtc->enabled = true; in dce_v6_0_crtc_dpms()
2411 amdgpu_crtc->crtc_id); in dce_v6_0_crtc_dpms()
2412 amdgpu_irq_update(adev, &adev->crtc_irq, type); in dce_v6_0_crtc_dpms()
2413 amdgpu_irq_update(adev, &adev->pageflip_irq, type); in dce_v6_0_crtc_dpms()
2421 if (amdgpu_crtc->enabled) in dce_v6_0_crtc_dpms()
2424 amdgpu_crtc->enabled = false; in dce_v6_0_crtc_dpms()
2449 struct drm_device *dev = crtc->dev; in dce_v6_0_crtc_disable()
2455 if (crtc->primary->fb) { in dce_v6_0_crtc_disable()
2459 abo = gem_to_amdgpu_bo(crtc->primary->fb->obj[0]); in dce_v6_0_crtc_disable()
2473 for (i = 0; i < adev->mode_info.num_crtc; i++) { in dce_v6_0_crtc_disable()
2474 if (adev->mode_info.crtcs[i] && in dce_v6_0_crtc_disable()
2475 adev->mode_info.crtcs[i]->enabled && in dce_v6_0_crtc_disable()
2476 i != amdgpu_crtc->crtc_id && in dce_v6_0_crtc_disable()
2477 amdgpu_crtc->pll_id == adev->mode_info.crtcs[i]->pll_id) { in dce_v6_0_crtc_disable()
2485 switch (amdgpu_crtc->pll_id) { in dce_v6_0_crtc_disable()
2489 amdgpu_atombios_crtc_program_pll(crtc, amdgpu_crtc->crtc_id, amdgpu_crtc->pll_id, in dce_v6_0_crtc_disable()
2496 amdgpu_crtc->pll_id = ATOM_PPLL_INVALID; in dce_v6_0_crtc_disable()
2497 amdgpu_crtc->adjusted_clock = 0; in dce_v6_0_crtc_disable()
2498 amdgpu_crtc->encoder = NULL; in dce_v6_0_crtc_disable()
2499 amdgpu_crtc->connector = NULL; in dce_v6_0_crtc_disable()
2509 if (!amdgpu_crtc->adjusted_clock) in dce_v6_0_crtc_mode_set()
2510 return -EINVAL; in dce_v6_0_crtc_mode_set()
2519 amdgpu_crtc->hw_mode = *adjusted_mode; in dce_v6_0_crtc_mode_set()
2530 struct drm_device *dev = crtc->dev; in dce_v6_0_crtc_mode_fixup()
2534 list_for_each_entry(encoder, &dev->mode_config.encoder_list, head) { in dce_v6_0_crtc_mode_fixup()
2535 if (encoder->crtc == crtc) { in dce_v6_0_crtc_mode_fixup()
2536 amdgpu_crtc->encoder = encoder; in dce_v6_0_crtc_mode_fixup()
2537 amdgpu_crtc->connector = amdgpu_get_connector_for_encoder(encoder); in dce_v6_0_crtc_mode_fixup()
2541 if ((amdgpu_crtc->encoder == NULL) || (amdgpu_crtc->connector == NULL)) { in dce_v6_0_crtc_mode_fixup()
2542 amdgpu_crtc->encoder = NULL; in dce_v6_0_crtc_mode_fixup()
2543 amdgpu_crtc->connector = NULL; in dce_v6_0_crtc_mode_fixup()
2551 amdgpu_crtc->pll_id = dce_v6_0_pick_pll(crtc); in dce_v6_0_crtc_mode_fixup()
2552 /* if we can't get a PPLL for a non-DP encoder, fail */ in dce_v6_0_crtc_mode_fixup()
2553 if ((amdgpu_crtc->pll_id == ATOM_PPLL_INVALID) && in dce_v6_0_crtc_mode_fixup()
2554 !ENCODER_MODE_IS_DP(amdgpu_atombios_encoder_get_encoder_mode(amdgpu_crtc->encoder))) in dce_v6_0_crtc_mode_fixup()
2592 return -ENOMEM; in dce_v6_0_crtc_init()
2594 drm_crtc_init(adev_to_drm(adev), &amdgpu_crtc->base, &dce_v6_0_crtc_funcs); in dce_v6_0_crtc_init()
2596 drm_mode_crtc_set_gamma_size(&amdgpu_crtc->base, 256); in dce_v6_0_crtc_init()
2597 amdgpu_crtc->crtc_id = index; in dce_v6_0_crtc_init()
2598 adev->mode_info.crtcs[index] = amdgpu_crtc; in dce_v6_0_crtc_init()
2600 amdgpu_crtc->max_cursor_width = CURSOR_WIDTH; in dce_v6_0_crtc_init()
2601 amdgpu_crtc->max_cursor_height = CURSOR_HEIGHT; in dce_v6_0_crtc_init()
2602 adev_to_drm(adev)->mode_config.cursor_width = amdgpu_crtc->max_cursor_width; in dce_v6_0_crtc_init()
2603 adev_to_drm(adev)->mode_config.cursor_height = amdgpu_crtc->max_cursor_height; in dce_v6_0_crtc_init()
2605 amdgpu_crtc->crtc_offset = crtc_offsets[amdgpu_crtc->crtc_id]; in dce_v6_0_crtc_init()
2607 amdgpu_crtc->pll_id = ATOM_PPLL_INVALID; in dce_v6_0_crtc_init()
2608 amdgpu_crtc->adjusted_clock = 0; in dce_v6_0_crtc_init()
2609 amdgpu_crtc->encoder = NULL; in dce_v6_0_crtc_init()
2610 amdgpu_crtc->connector = NULL; in dce_v6_0_crtc_init()
2611 drm_crtc_helper_add(&amdgpu_crtc->base, &dce_v6_0_crtc_helper_funcs); in dce_v6_0_crtc_init()
2620 adev->audio_endpt_rreg = &dce_v6_0_audio_endpt_rreg; in dce_v6_0_early_init()
2621 adev->audio_endpt_wreg = &dce_v6_0_audio_endpt_wreg; in dce_v6_0_early_init()
2625 adev->mode_info.num_crtc = dce_v6_0_get_num_crtc(adev); in dce_v6_0_early_init()
2627 switch (adev->asic_type) { in dce_v6_0_early_init()
2631 adev->mode_info.num_hpd = 6; in dce_v6_0_early_init()
2632 adev->mode_info.num_dig = 6; in dce_v6_0_early_init()
2635 adev->mode_info.num_hpd = 2; in dce_v6_0_early_init()
2636 adev->mode_info.num_dig = 2; in dce_v6_0_early_init()
2639 return -EINVAL; in dce_v6_0_early_init()
2653 for (i = 0; i < adev->mode_info.num_crtc; i++) { in dce_v6_0_sw_init()
2654 r = amdgpu_irq_add_id(adev, AMDGPU_IRQ_CLIENTID_LEGACY, i + 1, &adev->crtc_irq); in dce_v6_0_sw_init()
2660 r = amdgpu_irq_add_id(adev, AMDGPU_IRQ_CLIENTID_LEGACY, i, &adev->pageflip_irq); in dce_v6_0_sw_init()
2665 /* HPD hotplug */ in dce_v6_0_sw_init()
2666 r = amdgpu_irq_add_id(adev, AMDGPU_IRQ_CLIENTID_LEGACY, 42, &adev->hpd_irq); in dce_v6_0_sw_init()
2670 adev->mode_info.mode_config_initialized = true; in dce_v6_0_sw_init()
2672 adev_to_drm(adev)->mode_config.funcs = &amdgpu_mode_funcs; in dce_v6_0_sw_init()
2673 adev_to_drm(adev)->mode_config.async_page_flip = true; in dce_v6_0_sw_init()
2674 adev_to_drm(adev)->mode_config.max_width = 16384; in dce_v6_0_sw_init()
2675 adev_to_drm(adev)->mode_config.max_height = 16384; in dce_v6_0_sw_init()
2676 adev_to_drm(adev)->mode_config.preferred_depth = 24; in dce_v6_0_sw_init()
2677 adev_to_drm(adev)->mode_config.prefer_shadow = 1; in dce_v6_0_sw_init()
2678 adev_to_drm(adev)->mode_config.fb_base = adev->gmc.aper_base; in dce_v6_0_sw_init()
2684 adev_to_drm(adev)->mode_config.max_width = 16384; in dce_v6_0_sw_init()
2685 adev_to_drm(adev)->mode_config.max_height = 16384; in dce_v6_0_sw_init()
2688 for (i = 0; i < adev->mode_info.num_crtc; i++) { in dce_v6_0_sw_init()
2698 return -EINVAL; in dce_v6_0_sw_init()
2718 kfree(adev->mode_info.bios_hardcoded_edid); in dce_v6_0_sw_fini()
2726 adev->mode_info.mode_config_initialized = false; in dce_v6_0_sw_fini()
2740 amdgpu_atombios_crtc_set_disp_eng_pll(adev, adev->clock.default_dispclk); in dce_v6_0_hw_init()
2742 /* initialize hpd */ in dce_v6_0_hw_init()
2745 for (i = 0; i < adev->mode_info.audio.num_pins; i++) { in dce_v6_0_hw_init()
2746 dce_v6_0_audio_enable(adev, &adev->mode_info.audio.pin[i], false); in dce_v6_0_hw_init()
2761 for (i = 0; i < adev->mode_info.audio.num_pins; i++) { in dce_v6_0_hw_fini()
2762 dce_v6_0_audio_enable(adev, &adev->mode_info.audio.pin[i], false); in dce_v6_0_hw_fini()
2774 adev->mode_info.bl_level = in dce_v6_0_suspend()
2786 adev->mode_info.bl_level); in dce_v6_0_resume()
2791 if (adev->mode_info.bl_encoder) { in dce_v6_0_resume()
2793 adev->mode_info.bl_encoder); in dce_v6_0_resume()
2794 amdgpu_display_backlight_set_level(adev, adev->mode_info.bl_encoder, in dce_v6_0_resume()
2813 DRM_INFO("xxxx: dce_v6_0_soft_reset --- no impl!!\n"); in dce_v6_0_soft_reset()
2823 if (crtc >= adev->mode_info.num_crtc) { in dce_v6_0_set_crtc_vblank_interrupt_state()
2882 if (type >= adev->mode_info.num_hpd) { in dce_v6_0_set_hpd_interrupt_state()
2957 unsigned crtc = entry->src_id - 1; in dce_v6_0_crtc_irq()
2962 switch (entry->src_data[0]) { in dce_v6_0_crtc_irq()
2983 DRM_DEBUG("Unhandled interrupt: %d %d\n", entry->src_id, entry->src_data[0]); in dce_v6_0_crtc_irq()
2997 if (type >= adev->mode_info.num_crtc) { in dce_v6_0_set_pageflip_interrupt_state()
2999 return -EINVAL; in dce_v6_0_set_pageflip_interrupt_state()
3022 crtc_id = (entry->src_id - 8) >> 1; in dce_v6_0_pageflip_irq()
3023 amdgpu_crtc = adev->mode_info.crtcs[crtc_id]; in dce_v6_0_pageflip_irq()
3025 if (crtc_id >= adev->mode_info.num_crtc) { in dce_v6_0_pageflip_irq()
3027 return -EINVAL; in dce_v6_0_pageflip_irq()
3039 spin_lock_irqsave(&adev_to_drm(adev)->event_lock, flags); in dce_v6_0_pageflip_irq()
3040 works = amdgpu_crtc->pflip_works; in dce_v6_0_pageflip_irq()
3041 if (amdgpu_crtc->pflip_status != AMDGPU_FLIP_SUBMITTED){ in dce_v6_0_pageflip_irq()
3042 DRM_DEBUG_DRIVER("amdgpu_crtc->pflip_status = %d != " in dce_v6_0_pageflip_irq()
3044 amdgpu_crtc->pflip_status, in dce_v6_0_pageflip_irq()
3046 spin_unlock_irqrestore(&adev_to_drm(adev)->event_lock, flags); in dce_v6_0_pageflip_irq()
3051 amdgpu_crtc->pflip_status = AMDGPU_FLIP_NONE; in dce_v6_0_pageflip_irq()
3052 amdgpu_crtc->pflip_works = NULL; in dce_v6_0_pageflip_irq()
3055 if (works->event) in dce_v6_0_pageflip_irq()
3056 drm_crtc_send_vblank_event(&amdgpu_crtc->base, works->event); in dce_v6_0_pageflip_irq()
3058 spin_unlock_irqrestore(&adev_to_drm(adev)->event_lock, flags); in dce_v6_0_pageflip_irq()
3060 drm_crtc_vblank_put(&amdgpu_crtc->base); in dce_v6_0_pageflip_irq()
3061 schedule_work(&works->unpin_work); in dce_v6_0_pageflip_irq()
3071 unsigned hpd; in dce_v6_0_hpd_irq() local
3073 if (entry->src_data[0] >= adev->mode_info.num_hpd) { in dce_v6_0_hpd_irq()
3074 DRM_DEBUG("Unhandled interrupt: %d %d\n", entry->src_id, entry->src_data[0]); in dce_v6_0_hpd_irq()
3078 hpd = entry->src_data[0]; in dce_v6_0_hpd_irq()
3079 disp_int = RREG32(interrupt_status_offsets[hpd].reg); in dce_v6_0_hpd_irq()
3080 mask = interrupt_status_offsets[hpd].hpd; in dce_v6_0_hpd_irq()
3083 tmp = RREG32(mmDC_HPD1_INT_CONTROL + hpd_offsets[hpd]); in dce_v6_0_hpd_irq()
3085 WREG32(mmDC_HPD1_INT_CONTROL + hpd_offsets[hpd], tmp); in dce_v6_0_hpd_irq()
3086 schedule_work(&adev->hotplug_work); in dce_v6_0_hpd_irq()
3087 DRM_DEBUG("IH: HPD%d\n", hpd + 1); in dce_v6_0_hpd_irq()
3132 amdgpu_encoder->pixel_clock = adjusted_mode->clock; in dce_v6_0_encoder_mode_set()
3138 dce_v6_0_set_interleave(encoder->crtc, mode); in dce_v6_0_encoder_mode_set()
3149 struct amdgpu_device *adev = drm_to_adev(encoder->dev); in dce_v6_0_encoder_prepare()
3153 if ((amdgpu_encoder->active_device & in dce_v6_0_encoder_prepare()
3157 struct amdgpu_encoder_atom_dig *dig = amdgpu_encoder->enc_priv; in dce_v6_0_encoder_prepare()
3159 dig->dig_encoder = dce_v6_0_pick_dig_encoder(encoder); in dce_v6_0_encoder_prepare()
3160 if (amdgpu_encoder->active_device & ATOM_DEVICE_DFP_SUPPORT) in dce_v6_0_encoder_prepare()
3161 dig->afmt = adev->mode_info.afmt[dig->dig_encoder]; in dce_v6_0_encoder_prepare()
3171 if (amdgpu_connector->router.cd_valid) in dce_v6_0_encoder_prepare()
3175 if (connector->connector_type == DRM_MODE_CONNECTOR_eDP) in dce_v6_0_encoder_prepare()
3189 struct drm_device *dev = encoder->dev; in dce_v6_0_encoder_commit()
3209 dig = amdgpu_encoder->enc_priv; in dce_v6_0_encoder_disable()
3210 dig->dig_encoder = -1; in dce_v6_0_encoder_disable()
3212 amdgpu_encoder->active_device = 0; in dce_v6_0_encoder_disable()
3259 /* no detect for TMDS/LVDS yet */
3284 if (amdgpu_encoder->devices & (ATOM_DEVICE_LCD_SUPPORT)) in dce_v6_0_encoder_destroy()
3286 kfree(amdgpu_encoder->enc_priv); in dce_v6_0_encoder_destroy()
3305 list_for_each_entry(encoder, &dev->mode_config.encoder_list, head) { in dce_v6_0_encoder_add()
3307 if (amdgpu_encoder->encoder_enum == encoder_enum) { in dce_v6_0_encoder_add()
3308 amdgpu_encoder->devices |= supported_device; in dce_v6_0_encoder_add()
3319 encoder = &amdgpu_encoder->base; in dce_v6_0_encoder_add()
3320 switch (adev->mode_info.num_crtc) { in dce_v6_0_encoder_add()
3322 encoder->possible_crtcs = 0x1; in dce_v6_0_encoder_add()
3326 encoder->possible_crtcs = 0x3; in dce_v6_0_encoder_add()
3329 encoder->possible_crtcs = 0xf; in dce_v6_0_encoder_add()
3332 encoder->possible_crtcs = 0x3f; in dce_v6_0_encoder_add()
3336 amdgpu_encoder->enc_priv = NULL; in dce_v6_0_encoder_add()
3337 amdgpu_encoder->encoder_enum = encoder_enum; in dce_v6_0_encoder_add()
3338 amdgpu_encoder->encoder_id = (encoder_enum & OBJECT_ID_MASK) >> OBJECT_ID_SHIFT; in dce_v6_0_encoder_add()
3339 amdgpu_encoder->devices = supported_device; in dce_v6_0_encoder_add()
3340 amdgpu_encoder->rmx_type = RMX_OFF; in dce_v6_0_encoder_add()
3341 amdgpu_encoder->underscan_type = UNDERSCAN_OFF; in dce_v6_0_encoder_add()
3342 amdgpu_encoder->is_ext_encoder = false; in dce_v6_0_encoder_add()
3343 amdgpu_encoder->caps = caps; in dce_v6_0_encoder_add()
3345 switch (amdgpu_encoder->encoder_id) { in dce_v6_0_encoder_add()
3357 if (amdgpu_encoder->devices & (ATOM_DEVICE_LCD_SUPPORT)) { in dce_v6_0_encoder_add()
3358 amdgpu_encoder->rmx_type = RMX_FULL; in dce_v6_0_encoder_add()
3361 amdgpu_encoder->enc_priv = amdgpu_atombios_encoder_get_lcd_info(amdgpu_encoder); in dce_v6_0_encoder_add()
3362 } else if (amdgpu_encoder->devices & (ATOM_DEVICE_CRT_SUPPORT)) { in dce_v6_0_encoder_add()
3365 amdgpu_encoder->enc_priv = amdgpu_atombios_encoder_get_dig_info(amdgpu_encoder); in dce_v6_0_encoder_add()
3369 amdgpu_encoder->enc_priv = amdgpu_atombios_encoder_get_dig_info(amdgpu_encoder); in dce_v6_0_encoder_add()
3383 amdgpu_encoder->is_ext_encoder = true; in dce_v6_0_encoder_add()
3384 if (amdgpu_encoder->devices & (ATOM_DEVICE_LCD_SUPPORT)) in dce_v6_0_encoder_add()
3387 else if (amdgpu_encoder->devices & (ATOM_DEVICE_CRT_SUPPORT)) in dce_v6_0_encoder_add()
3414 adev->mode_info.funcs = &dce_v6_0_display_funcs; in dce_v6_0_set_display_funcs()
3434 if (adev->mode_info.num_crtc > 0) in dce_v6_0_set_irq_funcs()
3435 adev->crtc_irq.num_types = AMDGPU_CRTC_IRQ_VLINE1 + adev->mode_info.num_crtc; in dce_v6_0_set_irq_funcs()
3437 adev->crtc_irq.num_types = 0; in dce_v6_0_set_irq_funcs()
3438 adev->crtc_irq.funcs = &dce_v6_0_crtc_irq_funcs; in dce_v6_0_set_irq_funcs()
3440 adev->pageflip_irq.num_types = adev->mode_info.num_crtc; in dce_v6_0_set_irq_funcs()
3441 adev->pageflip_irq.funcs = &dce_v6_0_pageflip_irq_funcs; in dce_v6_0_set_irq_funcs()
3443 adev->hpd_irq.num_types = adev->mode_info.num_hpd; in dce_v6_0_set_irq_funcs()
3444 adev->hpd_irq.funcs = &dce_v6_0_hpd_irq_funcs; in dce_v6_0_set_irq_funcs()