Lines Matching +full:no +full:- +full:hpd
16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
90 uint32_t hpd; member
96 .hpd = DISP_INTERRUPT_STATUS__DC_HPD1_INTERRUPT_MASK
101 .hpd = DISP_INTERRUPT_STATUS_CONTINUE__DC_HPD2_INTERRUPT_MASK
106 .hpd = DISP_INTERRUPT_STATUS_CONTINUE2__DC_HPD3_INTERRUPT_MASK
111 .hpd = DISP_INTERRUPT_STATUS_CONTINUE3__DC_HPD4_INTERRUPT_MASK
116 .hpd = DISP_INTERRUPT_STATUS_CONTINUE4__DC_HPD5_INTERRUPT_MASK
121 .hpd = DISP_INTERRUPT_STATUS_CONTINUE5__DC_HPD6_INTERRUPT_MASK
161 switch (adev->asic_type) { in dce_v11_0_init_golden_registers()
198 spin_lock_irqsave(&adev->audio_endpt_idx_lock, flags); in dce_v11_0_audio_endpt_rreg()
201 spin_unlock_irqrestore(&adev->audio_endpt_idx_lock, flags); in dce_v11_0_audio_endpt_rreg()
211 spin_lock_irqsave(&adev->audio_endpt_idx_lock, flags); in dce_v11_0_audio_endpt_wreg()
214 spin_unlock_irqrestore(&adev->audio_endpt_idx_lock, flags); in dce_v11_0_audio_endpt_wreg()
219 if (crtc < 0 || crtc >= adev->mode_info.num_crtc) in dce_v11_0_vblank_get_counter()
230 for (i = 0; i < adev->mode_info.num_crtc; i++) in dce_v11_0_pageflip_interrupt_init()
231 amdgpu_irq_get(adev, &adev->pageflip_irq, i); in dce_v11_0_pageflip_interrupt_init()
239 for (i = 0; i < adev->mode_info.num_crtc; i++) in dce_v11_0_pageflip_interrupt_fini()
240 amdgpu_irq_put(adev, &adev->pageflip_irq, i); in dce_v11_0_pageflip_interrupt_fini()
244 * dce_v11_0_page_flip - pageflip callback.
256 struct amdgpu_crtc *amdgpu_crtc = adev->mode_info.crtcs[crtc_id]; in dce_v11_0_page_flip()
257 struct drm_framebuffer *fb = amdgpu_crtc->base.primary->fb; in dce_v11_0_page_flip()
261 tmp = RREG32(mmGRPH_FLIP_CONTROL + amdgpu_crtc->crtc_offset); in dce_v11_0_page_flip()
264 WREG32(mmGRPH_FLIP_CONTROL + amdgpu_crtc->crtc_offset, tmp); in dce_v11_0_page_flip()
266 WREG32(mmGRPH_PITCH + amdgpu_crtc->crtc_offset, in dce_v11_0_page_flip()
267 fb->pitches[0] / fb->format->cpp[0]); in dce_v11_0_page_flip()
269 WREG32(mmGRPH_PRIMARY_SURFACE_ADDRESS_HIGH + amdgpu_crtc->crtc_offset, in dce_v11_0_page_flip()
272 WREG32(mmGRPH_PRIMARY_SURFACE_ADDRESS + amdgpu_crtc->crtc_offset, in dce_v11_0_page_flip()
275 RREG32(mmGRPH_PRIMARY_SURFACE_ADDRESS + amdgpu_crtc->crtc_offset); in dce_v11_0_page_flip()
281 if ((crtc < 0) || (crtc >= adev->mode_info.num_crtc)) in dce_v11_0_crtc_get_scanoutpos()
282 return -EINVAL; in dce_v11_0_crtc_get_scanoutpos()
291 * dce_v11_0_hpd_sense - hpd sense callback.
294 * @hpd: hpd (hotplug detect) pin
300 enum amdgpu_hpd_id hpd) in dce_v11_0_hpd_sense() argument
304 if (hpd >= adev->mode_info.num_hpd) in dce_v11_0_hpd_sense()
307 if (RREG32(mmDC_HPD_INT_STATUS + hpd_offsets[hpd]) & in dce_v11_0_hpd_sense()
315 * dce_v11_0_hpd_set_polarity - hpd set polarity callback.
318 * @hpd: hpd (hotplug detect) pin
320 * Set the polarity of the hpd pin (evergreen+).
323 enum amdgpu_hpd_id hpd) in dce_v11_0_hpd_set_polarity() argument
326 bool connected = dce_v11_0_hpd_sense(adev, hpd); in dce_v11_0_hpd_set_polarity()
328 if (hpd >= adev->mode_info.num_hpd) in dce_v11_0_hpd_set_polarity()
331 tmp = RREG32(mmDC_HPD_INT_CONTROL + hpd_offsets[hpd]); in dce_v11_0_hpd_set_polarity()
336 WREG32(mmDC_HPD_INT_CONTROL + hpd_offsets[hpd], tmp); in dce_v11_0_hpd_set_polarity()
340 * dce_v11_0_hpd_init - hpd setup callback.
344 * Setup the hpd pins used by the card (evergreen+).
345 * Enable the pin, set the polarity, and enable the hpd interrupts.
358 if (amdgpu_connector->hpd.hpd >= adev->mode_info.num_hpd) in dce_v11_0_hpd_init()
361 if (connector->connector_type == DRM_MODE_CONNECTOR_eDP || in dce_v11_0_hpd_init()
362 connector->connector_type == DRM_MODE_CONNECTOR_LVDS) { in dce_v11_0_hpd_init()
363 /* don't try to enable hpd on eDP or LVDS avoid breaking the in dce_v11_0_hpd_init()
368 tmp = RREG32(mmDC_HPD_INT_CONTROL + hpd_offsets[amdgpu_connector->hpd.hpd]); in dce_v11_0_hpd_init()
370 WREG32(mmDC_HPD_INT_CONTROL + hpd_offsets[amdgpu_connector->hpd.hpd], tmp); in dce_v11_0_hpd_init()
374 tmp = RREG32(mmDC_HPD_CONTROL + hpd_offsets[amdgpu_connector->hpd.hpd]); in dce_v11_0_hpd_init()
376 WREG32(mmDC_HPD_CONTROL + hpd_offsets[amdgpu_connector->hpd.hpd], tmp); in dce_v11_0_hpd_init()
378 tmp = RREG32(mmDC_HPD_TOGGLE_FILT_CNTL + hpd_offsets[amdgpu_connector->hpd.hpd]); in dce_v11_0_hpd_init()
385 WREG32(mmDC_HPD_TOGGLE_FILT_CNTL + hpd_offsets[amdgpu_connector->hpd.hpd], tmp); in dce_v11_0_hpd_init()
387 dce_v11_0_hpd_set_polarity(adev, amdgpu_connector->hpd.hpd); in dce_v11_0_hpd_init()
388 amdgpu_irq_get(adev, &adev->hpd_irq, amdgpu_connector->hpd.hpd); in dce_v11_0_hpd_init()
394 * dce_v11_0_hpd_fini - hpd tear down callback.
398 * Tear down the hpd pins used by the card (evergreen+).
399 * Disable the hpd interrupts.
412 if (amdgpu_connector->hpd.hpd >= adev->mode_info.num_hpd) in dce_v11_0_hpd_fini()
415 tmp = RREG32(mmDC_HPD_CONTROL + hpd_offsets[amdgpu_connector->hpd.hpd]); in dce_v11_0_hpd_fini()
417 WREG32(mmDC_HPD_CONTROL + hpd_offsets[amdgpu_connector->hpd.hpd], tmp); in dce_v11_0_hpd_fini()
419 amdgpu_irq_put(adev, &adev->hpd_irq, amdgpu_connector->hpd.hpd); in dce_v11_0_hpd_fini()
435 for (i = 0; i < adev->mode_info.num_crtc; i++) { in dce_v11_0_is_display_hung()
444 for (i = 0; i < adev->mode_info.num_crtc; i++) { in dce_v11_0_is_display_hung()
485 switch (adev->asic_type) { in dce_v11_0_get_num_crtc()
532 struct drm_device *dev = encoder->dev; in dce_v11_0_program_fmt()
535 struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(encoder->crtc); in dce_v11_0_program_fmt()
544 dither = amdgpu_connector->dither; in dce_v11_0_program_fmt()
548 if (amdgpu_encoder->devices & ATOM_DEVICE_LCD_SUPPORT) in dce_v11_0_program_fmt()
552 if ((amdgpu_encoder->encoder_id == ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DAC1) || in dce_v11_0_program_fmt()
553 (amdgpu_encoder->encoder_id == ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DAC2)) in dce_v11_0_program_fmt()
603 WREG32(mmFMT_BIT_DEPTH_CONTROL + amdgpu_crtc->crtc_offset, tmp); in dce_v11_0_program_fmt()
609 * dce_v11_0_line_buffer_adjust - Set up the line buffer
625 u32 pipe_offset = amdgpu_crtc->crtc_id; in dce_v11_0_line_buffer_adjust()
634 if (amdgpu_crtc->base.enabled && mode) { in dce_v11_0_line_buffer_adjust()
635 if (mode->crtc_hdisplay < 1920) { in dce_v11_0_line_buffer_adjust()
638 } else if (mode->crtc_hdisplay < 2560) { in dce_v11_0_line_buffer_adjust()
641 } else if (mode->crtc_hdisplay < 4096) { in dce_v11_0_line_buffer_adjust()
643 buffer_alloc = (adev->flags & AMD_IS_APU) ? 2 : 4; in dce_v11_0_line_buffer_adjust()
647 buffer_alloc = (adev->flags & AMD_IS_APU) ? 2 : 4; in dce_v11_0_line_buffer_adjust()
654 tmp = RREG32(mmLB_MEMORY_CTRL + amdgpu_crtc->crtc_offset); in dce_v11_0_line_buffer_adjust()
656 WREG32(mmLB_MEMORY_CTRL + amdgpu_crtc->crtc_offset, tmp); in dce_v11_0_line_buffer_adjust()
662 for (i = 0; i < adev->usec_timeout; i++) { in dce_v11_0_line_buffer_adjust()
669 if (amdgpu_crtc->base.enabled && mode) { in dce_v11_0_line_buffer_adjust()
681 /* controller not enabled, so no lb used */ in dce_v11_0_line_buffer_adjust()
686 * cik_get_number_of_dram_channels - get the number of dram channels
738 * dce_v11_0_dram_bandwidth - get the dram bandwidth
754 yclk.full = dfixed_const(wm->yclk); in dce_v11_0_dram_bandwidth()
756 dram_channels.full = dfixed_const(wm->dram_channels * 4); in dce_v11_0_dram_bandwidth()
767 * dce_v11_0_dram_bandwidth_for_display - get the dram bandwidth for display
783 yclk.full = dfixed_const(wm->yclk); in dce_v11_0_dram_bandwidth_for_display()
785 dram_channels.full = dfixed_const(wm->dram_channels * 4); in dce_v11_0_dram_bandwidth_for_display()
796 * dce_v11_0_data_return_bandwidth - get the data return bandwidth
812 sclk.full = dfixed_const(wm->sclk); in dce_v11_0_data_return_bandwidth()
825 * dce_v11_0_dmif_request_bandwidth - get the dmif bandwidth
841 disp_clk.full = dfixed_const(wm->disp_clk); in dce_v11_0_dmif_request_bandwidth()
856 * dce_v11_0_available_bandwidth - get the min available bandwidth
875 * dce_v11_0_average_bandwidth - get the average available bandwidth
896 line_time.full = dfixed_const(wm->active_time + wm->blank_time); in dce_v11_0_average_bandwidth()
898 bpp.full = dfixed_const(wm->bytes_per_pixel); in dce_v11_0_average_bandwidth()
899 src_width.full = dfixed_const(wm->src_width); in dce_v11_0_average_bandwidth()
901 bandwidth.full = dfixed_mul(bandwidth, wm->vsc); in dce_v11_0_average_bandwidth()
908 * dce_v11_0_latency_watermark - get the latency watermark
923 u32 dc_latency = 40000000 / wm->disp_clk; /* dc pipe latency */ in dce_v11_0_latency_watermark()
924 u32 other_heads_data_return_time = ((wm->num_heads + 1) * worst_chunk_return_time) + in dce_v11_0_latency_watermark()
925 (wm->num_heads * cursor_line_pair_return_time); in dce_v11_0_latency_watermark()
931 if (wm->num_heads == 0) in dce_v11_0_latency_watermark()
936 if ((wm->vsc.full > a.full) || in dce_v11_0_latency_watermark()
937 ((wm->vsc.full > b.full) && (wm->vtaps >= 3)) || in dce_v11_0_latency_watermark()
938 (wm->vtaps >= 5) || in dce_v11_0_latency_watermark()
939 ((wm->vsc.full >= a.full) && wm->interlaced)) in dce_v11_0_latency_watermark()
945 b.full = dfixed_const(wm->num_heads); in dce_v11_0_latency_watermark()
947 tmp = div_u64((u64) dmif_size * (u64) wm->disp_clk, mc_latency + 512); in dce_v11_0_latency_watermark()
950 lb_fill_bw = min(tmp, wm->disp_clk * wm->bytes_per_pixel / 1000); in dce_v11_0_latency_watermark()
952 a.full = dfixed_const(max_src_lines_per_dst_line * wm->src_width * wm->bytes_per_pixel); in dce_v11_0_latency_watermark()
959 if (line_fill_time < wm->active_time) in dce_v11_0_latency_watermark()
962 return latency + (line_fill_time - wm->active_time); in dce_v11_0_latency_watermark()
967 * dce_v11_0_average_bandwidth_vs_dram_bandwidth_for_display - check
980 (dce_v11_0_dram_bandwidth_for_display(wm) / wm->num_heads)) in dce_v11_0_average_bandwidth_vs_dram_bandwidth_for_display()
987 * dce_v11_0_average_bandwidth_vs_available_bandwidth - check
1000 (dce_v11_0_available_bandwidth(wm) / wm->num_heads)) in dce_v11_0_average_bandwidth_vs_available_bandwidth()
1007 * dce_v11_0_check_latency_hiding - check latency hiding
1017 u32 lb_partitions = wm->lb_size / wm->src_width; in dce_v11_0_check_latency_hiding()
1018 u32 line_time = wm->active_time + wm->blank_time; in dce_v11_0_check_latency_hiding()
1024 if (wm->vsc.full > a.full) in dce_v11_0_check_latency_hiding()
1027 if (lb_partitions <= (wm->vtaps + 1)) in dce_v11_0_check_latency_hiding()
1033 latency_hiding = (latency_tolerant_lines * line_time + wm->blank_time); in dce_v11_0_check_latency_hiding()
1042 * dce_v11_0_program_watermarks - program display watermarks
1056 struct drm_display_mode *mode = &amdgpu_crtc->base.mode; in dce_v11_0_program_watermarks()
1063 if (amdgpu_crtc->base.enabled && num_heads && mode) { in dce_v11_0_program_watermarks()
1064 active_time = (u32) div_u64((u64)mode->crtc_hdisplay * 1000000, in dce_v11_0_program_watermarks()
1065 (u32)mode->clock); in dce_v11_0_program_watermarks()
1066 line_time = (u32) div_u64((u64)mode->crtc_htotal * 1000000, in dce_v11_0_program_watermarks()
1067 (u32)mode->clock); in dce_v11_0_program_watermarks()
1071 if (adev->pm.dpm_enabled) { in dce_v11_0_program_watermarks()
1077 wm_high.yclk = adev->pm.current_mclk * 10; in dce_v11_0_program_watermarks()
1078 wm_high.sclk = adev->pm.current_sclk * 10; in dce_v11_0_program_watermarks()
1081 wm_high.disp_clk = mode->clock; in dce_v11_0_program_watermarks()
1082 wm_high.src_width = mode->crtc_hdisplay; in dce_v11_0_program_watermarks()
1084 wm_high.blank_time = line_time - wm_high.active_time; in dce_v11_0_program_watermarks()
1086 if (mode->flags & DRM_MODE_FLAG_INTERLACE) in dce_v11_0_program_watermarks()
1088 wm_high.vsc = amdgpu_crtc->vsc; in dce_v11_0_program_watermarks()
1090 if (amdgpu_crtc->rmx_type != RMX_OFF) in dce_v11_0_program_watermarks()
1105 (adev->mode_info.disp_priority == 2)) { in dce_v11_0_program_watermarks()
1110 if (adev->pm.dpm_enabled) { in dce_v11_0_program_watermarks()
1116 wm_low.yclk = adev->pm.current_mclk * 10; in dce_v11_0_program_watermarks()
1117 wm_low.sclk = adev->pm.current_sclk * 10; in dce_v11_0_program_watermarks()
1120 wm_low.disp_clk = mode->clock; in dce_v11_0_program_watermarks()
1121 wm_low.src_width = mode->crtc_hdisplay; in dce_v11_0_program_watermarks()
1123 wm_low.blank_time = line_time - wm_low.active_time; in dce_v11_0_program_watermarks()
1125 if (mode->flags & DRM_MODE_FLAG_INTERLACE) in dce_v11_0_program_watermarks()
1127 wm_low.vsc = amdgpu_crtc->vsc; in dce_v11_0_program_watermarks()
1129 if (amdgpu_crtc->rmx_type != RMX_OFF) in dce_v11_0_program_watermarks()
1144 (adev->mode_info.disp_priority == 2)) { in dce_v11_0_program_watermarks()
1147 lb_vblank_lead_lines = DIV_ROUND_UP(lb_size, mode->crtc_hdisplay); in dce_v11_0_program_watermarks()
1151 wm_mask = RREG32(mmDPG_WATERMARK_MASK_CONTROL + amdgpu_crtc->crtc_offset); in dce_v11_0_program_watermarks()
1153 WREG32(mmDPG_WATERMARK_MASK_CONTROL + amdgpu_crtc->crtc_offset, tmp); in dce_v11_0_program_watermarks()
1154 tmp = RREG32(mmDPG_PIPE_URGENCY_CONTROL + amdgpu_crtc->crtc_offset); in dce_v11_0_program_watermarks()
1157 WREG32(mmDPG_PIPE_URGENCY_CONTROL + amdgpu_crtc->crtc_offset, tmp); in dce_v11_0_program_watermarks()
1160 WREG32(mmDPG_WATERMARK_MASK_CONTROL + amdgpu_crtc->crtc_offset, tmp); in dce_v11_0_program_watermarks()
1161 tmp = RREG32(mmDPG_PIPE_URGENCY_CONTROL + amdgpu_crtc->crtc_offset); in dce_v11_0_program_watermarks()
1164 WREG32(mmDPG_PIPE_URGENCY_CONTROL + amdgpu_crtc->crtc_offset, tmp); in dce_v11_0_program_watermarks()
1166 WREG32(mmDPG_WATERMARK_MASK_CONTROL + amdgpu_crtc->crtc_offset, wm_mask); in dce_v11_0_program_watermarks()
1169 amdgpu_crtc->line_time = line_time; in dce_v11_0_program_watermarks()
1170 amdgpu_crtc->wm_high = latency_watermark_a; in dce_v11_0_program_watermarks()
1171 amdgpu_crtc->wm_low = latency_watermark_b; in dce_v11_0_program_watermarks()
1173 amdgpu_crtc->lb_vblank_lead_lines = lb_vblank_lead_lines; in dce_v11_0_program_watermarks()
1177 * dce_v11_0_bandwidth_update - program display watermarks
1192 for (i = 0; i < adev->mode_info.num_crtc; i++) { in dce_v11_0_bandwidth_update()
1193 if (adev->mode_info.crtcs[i]->base.enabled) in dce_v11_0_bandwidth_update()
1196 for (i = 0; i < adev->mode_info.num_crtc; i++) { in dce_v11_0_bandwidth_update()
1197 mode = &adev->mode_info.crtcs[i]->base.mode; in dce_v11_0_bandwidth_update()
1198 lb_size = dce_v11_0_line_buffer_adjust(adev, adev->mode_info.crtcs[i], mode); in dce_v11_0_bandwidth_update()
1199 dce_v11_0_program_watermarks(adev, adev->mode_info.crtcs[i], in dce_v11_0_bandwidth_update()
1209 for (i = 0; i < adev->mode_info.audio.num_pins; i++) { in dce_v11_0_audio_get_connected_pins()
1210 offset = adev->mode_info.audio.pin[i].offset; in dce_v11_0_audio_get_connected_pins()
1216 adev->mode_info.audio.pin[i].connected = false; in dce_v11_0_audio_get_connected_pins()
1218 adev->mode_info.audio.pin[i].connected = true; in dce_v11_0_audio_get_connected_pins()
1228 for (i = 0; i < adev->mode_info.audio.num_pins; i++) { in dce_v11_0_audio_get_pin()
1229 if (adev->mode_info.audio.pin[i].connected) in dce_v11_0_audio_get_pin()
1230 return &adev->mode_info.audio.pin[i]; in dce_v11_0_audio_get_pin()
1232 DRM_ERROR("No connected audio pins found!\n"); in dce_v11_0_audio_get_pin()
1238 struct amdgpu_device *adev = drm_to_adev(encoder->dev); in dce_v11_0_afmt_audio_select_pin()
1240 struct amdgpu_encoder_atom_dig *dig = amdgpu_encoder->enc_priv; in dce_v11_0_afmt_audio_select_pin()
1243 if (!dig || !dig->afmt || !dig->afmt->pin) in dce_v11_0_afmt_audio_select_pin()
1246 tmp = RREG32(mmAFMT_AUDIO_SRC_CONTROL + dig->afmt->offset); in dce_v11_0_afmt_audio_select_pin()
1247 tmp = REG_SET_FIELD(tmp, AFMT_AUDIO_SRC_CONTROL, AFMT_AUDIO_SRC_SELECT, dig->afmt->pin->id); in dce_v11_0_afmt_audio_select_pin()
1248 WREG32(mmAFMT_AUDIO_SRC_CONTROL + dig->afmt->offset, tmp); in dce_v11_0_afmt_audio_select_pin()
1254 struct drm_device *dev = encoder->dev; in dce_v11_0_audio_write_latency_fields()
1257 struct amdgpu_encoder_atom_dig *dig = amdgpu_encoder->enc_priv; in dce_v11_0_audio_write_latency_fields()
1264 if (!dig || !dig->afmt || !dig->afmt->pin) in dce_v11_0_audio_write_latency_fields()
1269 if (connector->encoder == encoder) { in dce_v11_0_audio_write_latency_fields()
1281 if (mode->flags & DRM_MODE_FLAG_INTERLACE) in dce_v11_0_audio_write_latency_fields()
1283 if (connector->latency_present[interlace]) { in dce_v11_0_audio_write_latency_fields()
1285 VIDEO_LIPSYNC, connector->video_latency[interlace]); in dce_v11_0_audio_write_latency_fields()
1287 AUDIO_LIPSYNC, connector->audio_latency[interlace]); in dce_v11_0_audio_write_latency_fields()
1294 WREG32_AUDIO_ENDPT(dig->afmt->pin->offset, in dce_v11_0_audio_write_latency_fields()
1300 struct drm_device *dev = encoder->dev; in dce_v11_0_audio_write_speaker_allocation()
1303 struct amdgpu_encoder_atom_dig *dig = amdgpu_encoder->enc_priv; in dce_v11_0_audio_write_speaker_allocation()
1311 if (!dig || !dig->afmt || !dig->afmt->pin) in dce_v11_0_audio_write_speaker_allocation()
1316 if (connector->encoder == encoder) { in dce_v11_0_audio_write_speaker_allocation()
1335 tmp = RREG32_AUDIO_ENDPT(dig->afmt->pin->offset, in dce_v11_0_audio_write_speaker_allocation()
1348 WREG32_AUDIO_ENDPT(dig->afmt->pin->offset, in dce_v11_0_audio_write_speaker_allocation()
1356 struct drm_device *dev = encoder->dev; in dce_v11_0_audio_write_sad_regs()
1359 struct amdgpu_encoder_atom_dig *dig = amdgpu_encoder->enc_priv; in dce_v11_0_audio_write_sad_regs()
1381 if (!dig || !dig->afmt || !dig->afmt->pin) in dce_v11_0_audio_write_sad_regs()
1386 if (connector->encoder == encoder) { in dce_v11_0_audio_write_sad_regs()
1408 int max_channels = -1; in dce_v11_0_audio_write_sad_regs()
1414 if (sad->format == eld_reg_to_type[i][1]) { in dce_v11_0_audio_write_sad_regs()
1415 if (sad->channels > max_channels) { in dce_v11_0_audio_write_sad_regs()
1417 MAX_CHANNELS, sad->channels); in dce_v11_0_audio_write_sad_regs()
1419 DESCRIPTOR_BYTE_2, sad->byte2); in dce_v11_0_audio_write_sad_regs()
1421 SUPPORTED_FREQUENCIES, sad->freq); in dce_v11_0_audio_write_sad_regs()
1422 max_channels = sad->channels; in dce_v11_0_audio_write_sad_regs()
1425 if (sad->format == HDMI_AUDIO_CODING_TYPE_PCM) in dce_v11_0_audio_write_sad_regs()
1426 stereo_freqs |= sad->freq; in dce_v11_0_audio_write_sad_regs()
1434 WREG32_AUDIO_ENDPT(dig->afmt->pin->offset, eld_reg_to_type[i][0], tmp); in dce_v11_0_audio_write_sad_regs()
1447 WREG32_AUDIO_ENDPT(pin->offset, ixAZALIA_F0_CODEC_PIN_CONTROL_HOT_PLUG_CONTROL, in dce_v11_0_audio_enable()
1470 adev->mode_info.audio.enabled = true; in dce_v11_0_audio_init()
1472 switch (adev->asic_type) { in dce_v11_0_audio_init()
1475 adev->mode_info.audio.num_pins = 7; in dce_v11_0_audio_init()
1479 adev->mode_info.audio.num_pins = 8; in dce_v11_0_audio_init()
1483 adev->mode_info.audio.num_pins = 6; in dce_v11_0_audio_init()
1486 return -EINVAL; in dce_v11_0_audio_init()
1489 for (i = 0; i < adev->mode_info.audio.num_pins; i++) { in dce_v11_0_audio_init()
1490 adev->mode_info.audio.pin[i].channels = -1; in dce_v11_0_audio_init()
1491 adev->mode_info.audio.pin[i].rate = -1; in dce_v11_0_audio_init()
1492 adev->mode_info.audio.pin[i].bits_per_sample = -1; in dce_v11_0_audio_init()
1493 adev->mode_info.audio.pin[i].status_bits = 0; in dce_v11_0_audio_init()
1494 adev->mode_info.audio.pin[i].category_code = 0; in dce_v11_0_audio_init()
1495 adev->mode_info.audio.pin[i].connected = false; in dce_v11_0_audio_init()
1496 adev->mode_info.audio.pin[i].offset = pin_offsets[i]; in dce_v11_0_audio_init()
1497 adev->mode_info.audio.pin[i].id = i; in dce_v11_0_audio_init()
1500 dce_v11_0_audio_enable(adev, &adev->mode_info.audio.pin[i], false); in dce_v11_0_audio_init()
1513 if (!adev->mode_info.audio.enabled) in dce_v11_0_audio_fini()
1516 for (i = 0; i < adev->mode_info.audio.num_pins; i++) in dce_v11_0_audio_fini()
1517 dce_v11_0_audio_enable(adev, &adev->mode_info.audio.pin[i], false); in dce_v11_0_audio_fini()
1519 adev->mode_info.audio.enabled = false; in dce_v11_0_audio_fini()
1527 struct drm_device *dev = encoder->dev; in dce_v11_0_afmt_update_ACR()
1531 struct amdgpu_encoder_atom_dig *dig = amdgpu_encoder->enc_priv; in dce_v11_0_afmt_update_ACR()
1534 tmp = RREG32(mmHDMI_ACR_32_0 + dig->afmt->offset); in dce_v11_0_afmt_update_ACR()
1536 WREG32(mmHDMI_ACR_32_0 + dig->afmt->offset, tmp); in dce_v11_0_afmt_update_ACR()
1537 tmp = RREG32(mmHDMI_ACR_32_1 + dig->afmt->offset); in dce_v11_0_afmt_update_ACR()
1539 WREG32(mmHDMI_ACR_32_1 + dig->afmt->offset, tmp); in dce_v11_0_afmt_update_ACR()
1541 tmp = RREG32(mmHDMI_ACR_44_0 + dig->afmt->offset); in dce_v11_0_afmt_update_ACR()
1543 WREG32(mmHDMI_ACR_44_0 + dig->afmt->offset, tmp); in dce_v11_0_afmt_update_ACR()
1544 tmp = RREG32(mmHDMI_ACR_44_1 + dig->afmt->offset); in dce_v11_0_afmt_update_ACR()
1546 WREG32(mmHDMI_ACR_44_1 + dig->afmt->offset, tmp); in dce_v11_0_afmt_update_ACR()
1548 tmp = RREG32(mmHDMI_ACR_48_0 + dig->afmt->offset); in dce_v11_0_afmt_update_ACR()
1550 WREG32(mmHDMI_ACR_48_0 + dig->afmt->offset, tmp); in dce_v11_0_afmt_update_ACR()
1551 tmp = RREG32(mmHDMI_ACR_48_1 + dig->afmt->offset); in dce_v11_0_afmt_update_ACR()
1553 WREG32(mmHDMI_ACR_48_1 + dig->afmt->offset, tmp); in dce_v11_0_afmt_update_ACR()
1563 struct drm_device *dev = encoder->dev; in dce_v11_0_afmt_update_avi_infoframe()
1566 struct amdgpu_encoder_atom_dig *dig = amdgpu_encoder->enc_priv; in dce_v11_0_afmt_update_avi_infoframe()
1570 WREG32(mmAFMT_AVI_INFO0 + dig->afmt->offset, in dce_v11_0_afmt_update_avi_infoframe()
1572 WREG32(mmAFMT_AVI_INFO1 + dig->afmt->offset, in dce_v11_0_afmt_update_avi_infoframe()
1574 WREG32(mmAFMT_AVI_INFO2 + dig->afmt->offset, in dce_v11_0_afmt_update_avi_infoframe()
1576 WREG32(mmAFMT_AVI_INFO3 + dig->afmt->offset, in dce_v11_0_afmt_update_avi_infoframe()
1582 struct drm_device *dev = encoder->dev; in dce_v11_0_audio_set_dto()
1585 struct amdgpu_encoder_atom_dig *dig = amdgpu_encoder->enc_priv; in dce_v11_0_audio_set_dto()
1586 struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(encoder->crtc); in dce_v11_0_audio_set_dto()
1591 if (!dig || !dig->afmt) in dce_v11_0_audio_set_dto()
1601 amdgpu_crtc->crtc_id); in dce_v11_0_audio_set_dto()
1613 struct drm_device *dev = encoder->dev; in dce_v11_0_afmt_setmode()
1616 struct amdgpu_encoder_atom_dig *dig = amdgpu_encoder->enc_priv; in dce_v11_0_afmt_setmode()
1624 if (!dig || !dig->afmt) in dce_v11_0_afmt_setmode()
1628 if (!dig->afmt->enabled) in dce_v11_0_afmt_setmode()
1632 if (encoder->crtc) { in dce_v11_0_afmt_setmode()
1633 struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(encoder->crtc); in dce_v11_0_afmt_setmode()
1634 bpc = amdgpu_crtc->bpc; in dce_v11_0_afmt_setmode()
1638 dig->afmt->pin = dce_v11_0_audio_get_pin(adev); in dce_v11_0_afmt_setmode()
1639 dce_v11_0_audio_enable(adev, dig->afmt->pin, false); in dce_v11_0_afmt_setmode()
1641 dce_v11_0_audio_set_dto(encoder, mode->clock); in dce_v11_0_afmt_setmode()
1643 tmp = RREG32(mmHDMI_VBI_PACKET_CONTROL + dig->afmt->offset); in dce_v11_0_afmt_setmode()
1645 WREG32(mmHDMI_VBI_PACKET_CONTROL + dig->afmt->offset, tmp); /* send null packets when required */ in dce_v11_0_afmt_setmode()
1647 WREG32(mmAFMT_AUDIO_CRC_CONTROL + dig->afmt->offset, 0x1000); in dce_v11_0_afmt_setmode()
1649 tmp = RREG32(mmHDMI_CONTROL + dig->afmt->offset); in dce_v11_0_afmt_setmode()
1659 connector->name, bpc); in dce_v11_0_afmt_setmode()
1665 connector->name); in dce_v11_0_afmt_setmode()
1671 connector->name); in dce_v11_0_afmt_setmode()
1674 WREG32(mmHDMI_CONTROL + dig->afmt->offset, tmp); in dce_v11_0_afmt_setmode()
1676 tmp = RREG32(mmHDMI_VBI_PACKET_CONTROL + dig->afmt->offset); in dce_v11_0_afmt_setmode()
1680 WREG32(mmHDMI_VBI_PACKET_CONTROL + dig->afmt->offset, tmp); in dce_v11_0_afmt_setmode()
1682 tmp = RREG32(mmHDMI_INFOFRAME_CONTROL0 + dig->afmt->offset); in dce_v11_0_afmt_setmode()
1687 WREG32(mmHDMI_INFOFRAME_CONTROL0 + dig->afmt->offset, tmp); in dce_v11_0_afmt_setmode()
1689 tmp = RREG32(mmAFMT_INFOFRAME_CONTROL0 + dig->afmt->offset); in dce_v11_0_afmt_setmode()
1692 WREG32(mmAFMT_INFOFRAME_CONTROL0 + dig->afmt->offset, tmp); in dce_v11_0_afmt_setmode()
1694 tmp = RREG32(mmHDMI_INFOFRAME_CONTROL1 + dig->afmt->offset); in dce_v11_0_afmt_setmode()
1697 WREG32(mmHDMI_INFOFRAME_CONTROL1 + dig->afmt->offset, tmp); in dce_v11_0_afmt_setmode()
1699 WREG32(mmHDMI_GC + dig->afmt->offset, 0); /* unset HDMI_GC_AVMUTE */ in dce_v11_0_afmt_setmode()
1701 tmp = RREG32(mmHDMI_AUDIO_PACKET_CONTROL + dig->afmt->offset); in dce_v11_0_afmt_setmode()
1706 WREG32(mmHDMI_AUDIO_PACKET_CONTROL + dig->afmt->offset, tmp); in dce_v11_0_afmt_setmode()
1708 tmp = RREG32(mmAFMT_AUDIO_PACKET_CONTROL + dig->afmt->offset); in dce_v11_0_afmt_setmode()
1711 WREG32(mmAFMT_AUDIO_PACKET_CONTROL + dig->afmt->offset, tmp); in dce_v11_0_afmt_setmode()
1713 tmp = RREG32(mmHDMI_ACR_PACKET_CONTROL + dig->afmt->offset); in dce_v11_0_afmt_setmode()
1722 WREG32(mmHDMI_ACR_PACKET_CONTROL + dig->afmt->offset, tmp); in dce_v11_0_afmt_setmode()
1724 dce_v11_0_afmt_update_ACR(encoder, mode->clock); in dce_v11_0_afmt_setmode()
1726 tmp = RREG32(mmAFMT_60958_0 + dig->afmt->offset); in dce_v11_0_afmt_setmode()
1728 WREG32(mmAFMT_60958_0 + dig->afmt->offset, tmp); in dce_v11_0_afmt_setmode()
1730 tmp = RREG32(mmAFMT_60958_1 + dig->afmt->offset); in dce_v11_0_afmt_setmode()
1732 WREG32(mmAFMT_60958_1 + dig->afmt->offset, tmp); in dce_v11_0_afmt_setmode()
1734 tmp = RREG32(mmAFMT_60958_2 + dig->afmt->offset); in dce_v11_0_afmt_setmode()
1741 WREG32(mmAFMT_60958_2 + dig->afmt->offset, tmp); in dce_v11_0_afmt_setmode()
1745 WREG32(mmAFMT_AUDIO_PACKET_CONTROL2 + dig->afmt->offset, in dce_v11_0_afmt_setmode()
1766 tmp = RREG32(mmHDMI_INFOFRAME_CONTROL0 + dig->afmt->offset); in dce_v11_0_afmt_setmode()
1771 WREG32(mmHDMI_INFOFRAME_CONTROL0 + dig->afmt->offset, tmp); in dce_v11_0_afmt_setmode()
1773 tmp = RREG32(mmHDMI_INFOFRAME_CONTROL1 + dig->afmt->offset); in dce_v11_0_afmt_setmode()
1775 WREG32(mmHDMI_INFOFRAME_CONTROL1 + dig->afmt->offset, tmp); in dce_v11_0_afmt_setmode()
1777 tmp = RREG32(mmAFMT_AUDIO_PACKET_CONTROL + dig->afmt->offset); in dce_v11_0_afmt_setmode()
1780 WREG32(mmAFMT_AUDIO_PACKET_CONTROL + dig->afmt->offset, tmp); in dce_v11_0_afmt_setmode()
1782 WREG32(mmAFMT_RAMP_CONTROL0 + dig->afmt->offset, 0x00FFFFFF); in dce_v11_0_afmt_setmode()
1783 WREG32(mmAFMT_RAMP_CONTROL1 + dig->afmt->offset, 0x007FFFFF); in dce_v11_0_afmt_setmode()
1784 WREG32(mmAFMT_RAMP_CONTROL2 + dig->afmt->offset, 0x00000001); in dce_v11_0_afmt_setmode()
1785 WREG32(mmAFMT_RAMP_CONTROL3 + dig->afmt->offset, 0x00000001); in dce_v11_0_afmt_setmode()
1788 dce_v11_0_audio_enable(adev, dig->afmt->pin, true); in dce_v11_0_afmt_setmode()
1793 struct drm_device *dev = encoder->dev; in dce_v11_0_afmt_enable()
1796 struct amdgpu_encoder_atom_dig *dig = amdgpu_encoder->enc_priv; in dce_v11_0_afmt_enable()
1798 if (!dig || !dig->afmt) in dce_v11_0_afmt_enable()
1802 if (enable && dig->afmt->enabled) in dce_v11_0_afmt_enable()
1804 if (!enable && !dig->afmt->enabled) in dce_v11_0_afmt_enable()
1807 if (!enable && dig->afmt->pin) { in dce_v11_0_afmt_enable()
1808 dce_v11_0_audio_enable(adev, dig->afmt->pin, false); in dce_v11_0_afmt_enable()
1809 dig->afmt->pin = NULL; in dce_v11_0_afmt_enable()
1812 dig->afmt->enabled = enable; in dce_v11_0_afmt_enable()
1815 enable ? "En" : "Dis", dig->afmt->offset, amdgpu_encoder->encoder_id); in dce_v11_0_afmt_enable()
1822 for (i = 0; i < adev->mode_info.num_dig; i++) in dce_v11_0_afmt_init()
1823 adev->mode_info.afmt[i] = NULL; in dce_v11_0_afmt_init()
1826 for (i = 0; i < adev->mode_info.num_dig; i++) { in dce_v11_0_afmt_init()
1827 adev->mode_info.afmt[i] = kzalloc(sizeof(struct amdgpu_afmt), GFP_KERNEL); in dce_v11_0_afmt_init()
1828 if (adev->mode_info.afmt[i]) { in dce_v11_0_afmt_init()
1829 adev->mode_info.afmt[i]->offset = dig_offsets[i]; in dce_v11_0_afmt_init()
1830 adev->mode_info.afmt[i]->id = i; in dce_v11_0_afmt_init()
1834 kfree(adev->mode_info.afmt[j]); in dce_v11_0_afmt_init()
1835 adev->mode_info.afmt[j] = NULL; in dce_v11_0_afmt_init()
1837 return -ENOMEM; in dce_v11_0_afmt_init()
1847 for (i = 0; i < adev->mode_info.num_dig; i++) { in dce_v11_0_afmt_fini()
1848 kfree(adev->mode_info.afmt[i]); in dce_v11_0_afmt_fini()
1849 adev->mode_info.afmt[i] = NULL; in dce_v11_0_afmt_fini()
1866 struct drm_device *dev = crtc->dev; in dce_v11_0_vga_enable()
1870 vga_control = RREG32(vga_control_regs[amdgpu_crtc->crtc_id]) & ~1; in dce_v11_0_vga_enable()
1872 WREG32(vga_control_regs[amdgpu_crtc->crtc_id], vga_control | 1); in dce_v11_0_vga_enable()
1874 WREG32(vga_control_regs[amdgpu_crtc->crtc_id], vga_control); in dce_v11_0_vga_enable()
1880 struct drm_device *dev = crtc->dev; in dce_v11_0_grph_enable()
1884 WREG32(mmGRPH_ENABLE + amdgpu_crtc->crtc_offset, 1); in dce_v11_0_grph_enable()
1886 WREG32(mmGRPH_ENABLE + amdgpu_crtc->crtc_offset, 0); in dce_v11_0_grph_enable()
1894 struct drm_device *dev = crtc->dev; in dce_v11_0_crtc_do_set_base()
1908 /* no fb bound */ in dce_v11_0_crtc_do_set_base()
1909 if (!atomic && !crtc->primary->fb) { in dce_v11_0_crtc_do_set_base()
1910 DRM_DEBUG_KMS("No FB bound\n"); in dce_v11_0_crtc_do_set_base()
1917 target_fb = crtc->primary->fb; in dce_v11_0_crtc_do_set_base()
1922 obj = target_fb->obj[0]; in dce_v11_0_crtc_do_set_base()
1932 return -EINVAL; in dce_v11_0_crtc_do_set_base()
1942 switch (target_fb->format->format) { in dce_v11_0_crtc_do_set_base()
1999 /* Greater 8 bpc fb needs to bypass hw-lut to retain precision */ in dce_v11_0_crtc_do_set_base()
2010 /* Greater 8 bpc fb needs to bypass hw-lut to retain precision */ in dce_v11_0_crtc_do_set_base()
2026 drm_get_format_name(target_fb->format->format, &format_name)); in dce_v11_0_crtc_do_set_base()
2027 return -EINVAL; in dce_v11_0_crtc_do_set_base()
2063 tmp = RREG32(mmGRPH_FLIP_CONTROL + amdgpu_crtc->crtc_offset); in dce_v11_0_crtc_do_set_base()
2066 WREG32(mmGRPH_FLIP_CONTROL + amdgpu_crtc->crtc_offset, tmp); in dce_v11_0_crtc_do_set_base()
2068 WREG32(mmGRPH_PRIMARY_SURFACE_ADDRESS_HIGH + amdgpu_crtc->crtc_offset, in dce_v11_0_crtc_do_set_base()
2070 WREG32(mmGRPH_SECONDARY_SURFACE_ADDRESS_HIGH + amdgpu_crtc->crtc_offset, in dce_v11_0_crtc_do_set_base()
2072 WREG32(mmGRPH_PRIMARY_SURFACE_ADDRESS + amdgpu_crtc->crtc_offset, in dce_v11_0_crtc_do_set_base()
2074 WREG32(mmGRPH_SECONDARY_SURFACE_ADDRESS + amdgpu_crtc->crtc_offset, in dce_v11_0_crtc_do_set_base()
2076 WREG32(mmGRPH_CONTROL + amdgpu_crtc->crtc_offset, fb_format); in dce_v11_0_crtc_do_set_base()
2077 WREG32(mmGRPH_SWAP_CNTL + amdgpu_crtc->crtc_offset, fb_swap); in dce_v11_0_crtc_do_set_base()
2084 tmp = RREG32(mmGRPH_LUT_10BIT_BYPASS + amdgpu_crtc->crtc_offset); in dce_v11_0_crtc_do_set_base()
2089 WREG32(mmGRPH_LUT_10BIT_BYPASS + amdgpu_crtc->crtc_offset, tmp); in dce_v11_0_crtc_do_set_base()
2094 WREG32(mmGRPH_SURFACE_OFFSET_X + amdgpu_crtc->crtc_offset, 0); in dce_v11_0_crtc_do_set_base()
2095 WREG32(mmGRPH_SURFACE_OFFSET_Y + amdgpu_crtc->crtc_offset, 0); in dce_v11_0_crtc_do_set_base()
2096 WREG32(mmGRPH_X_START + amdgpu_crtc->crtc_offset, 0); in dce_v11_0_crtc_do_set_base()
2097 WREG32(mmGRPH_Y_START + amdgpu_crtc->crtc_offset, 0); in dce_v11_0_crtc_do_set_base()
2098 WREG32(mmGRPH_X_END + amdgpu_crtc->crtc_offset, target_fb->width); in dce_v11_0_crtc_do_set_base()
2099 WREG32(mmGRPH_Y_END + amdgpu_crtc->crtc_offset, target_fb->height); in dce_v11_0_crtc_do_set_base()
2101 fb_pitch_pixels = target_fb->pitches[0] / target_fb->format->cpp[0]; in dce_v11_0_crtc_do_set_base()
2102 WREG32(mmGRPH_PITCH + amdgpu_crtc->crtc_offset, fb_pitch_pixels); in dce_v11_0_crtc_do_set_base()
2106 WREG32(mmLB_DESKTOP_HEIGHT + amdgpu_crtc->crtc_offset, in dce_v11_0_crtc_do_set_base()
2107 target_fb->height); in dce_v11_0_crtc_do_set_base()
2111 WREG32(mmVIEWPORT_START + amdgpu_crtc->crtc_offset, in dce_v11_0_crtc_do_set_base()
2113 viewport_w = crtc->mode.hdisplay; in dce_v11_0_crtc_do_set_base()
2114 viewport_h = (crtc->mode.vdisplay + 1) & ~1; in dce_v11_0_crtc_do_set_base()
2115 WREG32(mmVIEWPORT_SIZE + amdgpu_crtc->crtc_offset, in dce_v11_0_crtc_do_set_base()
2119 WREG32(mmCRTC_MASTER_UPDATE_MODE + amdgpu_crtc->crtc_offset, 0); in dce_v11_0_crtc_do_set_base()
2121 if (!atomic && fb && fb != crtc->primary->fb) { in dce_v11_0_crtc_do_set_base()
2122 abo = gem_to_amdgpu_bo(fb->obj[0]); in dce_v11_0_crtc_do_set_base()
2139 struct drm_device *dev = crtc->dev; in dce_v11_0_set_interleave()
2144 tmp = RREG32(mmLB_DATA_FORMAT + amdgpu_crtc->crtc_offset); in dce_v11_0_set_interleave()
2145 if (mode->flags & DRM_MODE_FLAG_INTERLACE) in dce_v11_0_set_interleave()
2149 WREG32(mmLB_DATA_FORMAT + amdgpu_crtc->crtc_offset, tmp); in dce_v11_0_set_interleave()
2155 struct drm_device *dev = crtc->dev; in dce_v11_0_crtc_load_lut()
2161 DRM_DEBUG_KMS("%d\n", amdgpu_crtc->crtc_id); in dce_v11_0_crtc_load_lut()
2163 tmp = RREG32(mmINPUT_CSC_CONTROL + amdgpu_crtc->crtc_offset); in dce_v11_0_crtc_load_lut()
2165 WREG32(mmINPUT_CSC_CONTROL + amdgpu_crtc->crtc_offset, tmp); in dce_v11_0_crtc_load_lut()
2167 tmp = RREG32(mmPRESCALE_GRPH_CONTROL + amdgpu_crtc->crtc_offset); in dce_v11_0_crtc_load_lut()
2169 WREG32(mmPRESCALE_GRPH_CONTROL + amdgpu_crtc->crtc_offset, tmp); in dce_v11_0_crtc_load_lut()
2171 tmp = RREG32(mmINPUT_GAMMA_CONTROL + amdgpu_crtc->crtc_offset); in dce_v11_0_crtc_load_lut()
2173 WREG32(mmINPUT_GAMMA_CONTROL + amdgpu_crtc->crtc_offset, tmp); in dce_v11_0_crtc_load_lut()
2175 WREG32(mmDC_LUT_CONTROL + amdgpu_crtc->crtc_offset, 0); in dce_v11_0_crtc_load_lut()
2177 WREG32(mmDC_LUT_BLACK_OFFSET_BLUE + amdgpu_crtc->crtc_offset, 0); in dce_v11_0_crtc_load_lut()
2178 WREG32(mmDC_LUT_BLACK_OFFSET_GREEN + amdgpu_crtc->crtc_offset, 0); in dce_v11_0_crtc_load_lut()
2179 WREG32(mmDC_LUT_BLACK_OFFSET_RED + amdgpu_crtc->crtc_offset, 0); in dce_v11_0_crtc_load_lut()
2181 WREG32(mmDC_LUT_WHITE_OFFSET_BLUE + amdgpu_crtc->crtc_offset, 0xffff); in dce_v11_0_crtc_load_lut()
2182 WREG32(mmDC_LUT_WHITE_OFFSET_GREEN + amdgpu_crtc->crtc_offset, 0xffff); in dce_v11_0_crtc_load_lut()
2183 WREG32(mmDC_LUT_WHITE_OFFSET_RED + amdgpu_crtc->crtc_offset, 0xffff); in dce_v11_0_crtc_load_lut()
2185 WREG32(mmDC_LUT_RW_MODE + amdgpu_crtc->crtc_offset, 0); in dce_v11_0_crtc_load_lut()
2186 WREG32(mmDC_LUT_WRITE_EN_MASK + amdgpu_crtc->crtc_offset, 0x00000007); in dce_v11_0_crtc_load_lut()
2188 WREG32(mmDC_LUT_RW_INDEX + amdgpu_crtc->crtc_offset, 0); in dce_v11_0_crtc_load_lut()
2189 r = crtc->gamma_store; in dce_v11_0_crtc_load_lut()
2190 g = r + crtc->gamma_size; in dce_v11_0_crtc_load_lut()
2191 b = g + crtc->gamma_size; in dce_v11_0_crtc_load_lut()
2193 WREG32(mmDC_LUT_30_COLOR + amdgpu_crtc->crtc_offset, in dce_v11_0_crtc_load_lut()
2199 tmp = RREG32(mmDEGAMMA_CONTROL + amdgpu_crtc->crtc_offset); in dce_v11_0_crtc_load_lut()
2203 WREG32(mmDEGAMMA_CONTROL + amdgpu_crtc->crtc_offset, tmp); in dce_v11_0_crtc_load_lut()
2205 tmp = RREG32(mmGAMUT_REMAP_CONTROL + amdgpu_crtc->crtc_offset); in dce_v11_0_crtc_load_lut()
2207 WREG32(mmGAMUT_REMAP_CONTROL + amdgpu_crtc->crtc_offset, tmp); in dce_v11_0_crtc_load_lut()
2209 tmp = RREG32(mmREGAMMA_CONTROL + amdgpu_crtc->crtc_offset); in dce_v11_0_crtc_load_lut()
2211 WREG32(mmREGAMMA_CONTROL + amdgpu_crtc->crtc_offset, tmp); in dce_v11_0_crtc_load_lut()
2213 tmp = RREG32(mmOUTPUT_CSC_CONTROL + amdgpu_crtc->crtc_offset); in dce_v11_0_crtc_load_lut()
2215 WREG32(mmOUTPUT_CSC_CONTROL + amdgpu_crtc->crtc_offset, tmp); in dce_v11_0_crtc_load_lut()
2218 WREG32(mmDENORM_CONTROL + amdgpu_crtc->crtc_offset, 0); in dce_v11_0_crtc_load_lut()
2222 tmp = RREG32(mmALPHA_CONTROL + amdgpu_crtc->crtc_offset); in dce_v11_0_crtc_load_lut()
2224 WREG32(mmALPHA_CONTROL + amdgpu_crtc->crtc_offset, tmp); in dce_v11_0_crtc_load_lut()
2230 struct amdgpu_encoder_atom_dig *dig = amdgpu_encoder->enc_priv; in dce_v11_0_pick_dig_encoder()
2232 switch (amdgpu_encoder->encoder_id) { in dce_v11_0_pick_dig_encoder()
2234 if (dig->linkb) in dce_v11_0_pick_dig_encoder()
2240 if (dig->linkb) in dce_v11_0_pick_dig_encoder()
2246 if (dig->linkb) in dce_v11_0_pick_dig_encoder()
2255 DRM_ERROR("invalid encoder_id: 0x%x\n", amdgpu_encoder->encoder_id); in dce_v11_0_pick_dig_encoder()
2261 * dce_v11_0_pick_pll - Allocate a PPLL for use by the crtc.
2266 * a single PPLL can be used for all DP crtcs/encoders. For non-DP
2269 * as there is no need to program the PLL itself. If we are not able to
2277 * - PPLL1, PPLL2 are available for all UNIPHY (both DP and non-DP)
2279 * - PPLL0, PPLL1, PPLL2 are available for all UNIPHY (both DP and non-DP) and DAC
2285 struct drm_device *dev = crtc->dev; in dce_v11_0_pick_pll()
2290 if ((adev->asic_type == CHIP_POLARIS10) || in dce_v11_0_pick_pll()
2291 (adev->asic_type == CHIP_POLARIS11) || in dce_v11_0_pick_pll()
2292 (adev->asic_type == CHIP_POLARIS12) || in dce_v11_0_pick_pll()
2293 (adev->asic_type == CHIP_VEGAM)) { in dce_v11_0_pick_pll()
2295 to_amdgpu_encoder(amdgpu_crtc->encoder); in dce_v11_0_pick_pll()
2296 struct amdgpu_encoder_atom_dig *dig = amdgpu_encoder->enc_priv; in dce_v11_0_pick_pll()
2298 if (ENCODER_MODE_IS_DP(amdgpu_atombios_encoder_get_encoder_mode(amdgpu_crtc->encoder))) in dce_v11_0_pick_pll()
2301 switch (amdgpu_encoder->encoder_id) { in dce_v11_0_pick_pll()
2303 if (dig->linkb) in dce_v11_0_pick_pll()
2309 if (dig->linkb) in dce_v11_0_pick_pll()
2315 if (dig->linkb) in dce_v11_0_pick_pll()
2321 DRM_ERROR("invalid encoder_id: 0x%x\n", amdgpu_encoder->encoder_id); in dce_v11_0_pick_pll()
2326 if (ENCODER_MODE_IS_DP(amdgpu_atombios_encoder_get_encoder_mode(amdgpu_crtc->encoder))) { in dce_v11_0_pick_pll()
2327 if (adev->clock.dp_extclk) in dce_v11_0_pick_pll()
2345 if (adev->flags & AMD_IS_APU) { in dce_v11_0_pick_pll()
2367 struct amdgpu_device *adev = drm_to_adev(crtc->dev); in dce_v11_0_lock_cursor()
2371 cur_lock = RREG32(mmCUR_UPDATE + amdgpu_crtc->crtc_offset); in dce_v11_0_lock_cursor()
2376 WREG32(mmCUR_UPDATE + amdgpu_crtc->crtc_offset, cur_lock); in dce_v11_0_lock_cursor()
2382 struct amdgpu_device *adev = drm_to_adev(crtc->dev); in dce_v11_0_hide_cursor()
2385 tmp = RREG32(mmCUR_CONTROL + amdgpu_crtc->crtc_offset); in dce_v11_0_hide_cursor()
2387 WREG32(mmCUR_CONTROL + amdgpu_crtc->crtc_offset, tmp); in dce_v11_0_hide_cursor()
2393 struct amdgpu_device *adev = drm_to_adev(crtc->dev); in dce_v11_0_show_cursor()
2396 WREG32(mmCUR_SURFACE_ADDRESS_HIGH + amdgpu_crtc->crtc_offset, in dce_v11_0_show_cursor()
2397 upper_32_bits(amdgpu_crtc->cursor_addr)); in dce_v11_0_show_cursor()
2398 WREG32(mmCUR_SURFACE_ADDRESS + amdgpu_crtc->crtc_offset, in dce_v11_0_show_cursor()
2399 lower_32_bits(amdgpu_crtc->cursor_addr)); in dce_v11_0_show_cursor()
2401 tmp = RREG32(mmCUR_CONTROL + amdgpu_crtc->crtc_offset); in dce_v11_0_show_cursor()
2404 WREG32(mmCUR_CONTROL + amdgpu_crtc->crtc_offset, tmp); in dce_v11_0_show_cursor()
2411 struct amdgpu_device *adev = drm_to_adev(crtc->dev); in dce_v11_0_cursor_move_locked()
2414 amdgpu_crtc->cursor_x = x; in dce_v11_0_cursor_move_locked()
2415 amdgpu_crtc->cursor_y = y; in dce_v11_0_cursor_move_locked()
2418 x += crtc->x; in dce_v11_0_cursor_move_locked()
2419 y += crtc->y; in dce_v11_0_cursor_move_locked()
2420 DRM_DEBUG("x %d y %d c->x %d c->y %d\n", x, y, crtc->x, crtc->y); in dce_v11_0_cursor_move_locked()
2423 xorigin = min(-x, amdgpu_crtc->max_cursor_width - 1); in dce_v11_0_cursor_move_locked()
2427 yorigin = min(-y, amdgpu_crtc->max_cursor_height - 1); in dce_v11_0_cursor_move_locked()
2431 WREG32(mmCUR_POSITION + amdgpu_crtc->crtc_offset, (x << 16) | y); in dce_v11_0_cursor_move_locked()
2432 WREG32(mmCUR_HOT_SPOT + amdgpu_crtc->crtc_offset, (xorigin << 16) | yorigin); in dce_v11_0_cursor_move_locked()
2433 WREG32(mmCUR_SIZE + amdgpu_crtc->crtc_offset, in dce_v11_0_cursor_move_locked()
2434 ((amdgpu_crtc->cursor_width - 1) << 16) | (amdgpu_crtc->cursor_height - 1)); in dce_v11_0_cursor_move_locked()
2471 if ((width > amdgpu_crtc->max_cursor_width) || in dce_v11_0_crtc_cursor_set2()
2472 (height > amdgpu_crtc->max_cursor_height)) { in dce_v11_0_crtc_cursor_set2()
2474 return -EINVAL; in dce_v11_0_crtc_cursor_set2()
2479 DRM_ERROR("Cannot find cursor object %x for crtc %d\n", handle, amdgpu_crtc->crtc_id); in dce_v11_0_crtc_cursor_set2()
2480 return -ENOENT; in dce_v11_0_crtc_cursor_set2()
2497 amdgpu_crtc->cursor_addr = amdgpu_bo_gpu_offset(aobj); in dce_v11_0_crtc_cursor_set2()
2501 if (width != amdgpu_crtc->cursor_width || in dce_v11_0_crtc_cursor_set2()
2502 height != amdgpu_crtc->cursor_height || in dce_v11_0_crtc_cursor_set2()
2503 hot_x != amdgpu_crtc->cursor_hot_x || in dce_v11_0_crtc_cursor_set2()
2504 hot_y != amdgpu_crtc->cursor_hot_y) { in dce_v11_0_crtc_cursor_set2()
2507 x = amdgpu_crtc->cursor_x + amdgpu_crtc->cursor_hot_x - hot_x; in dce_v11_0_crtc_cursor_set2()
2508 y = amdgpu_crtc->cursor_y + amdgpu_crtc->cursor_hot_y - hot_y; in dce_v11_0_crtc_cursor_set2()
2512 amdgpu_crtc->cursor_width = width; in dce_v11_0_crtc_cursor_set2()
2513 amdgpu_crtc->cursor_height = height; in dce_v11_0_crtc_cursor_set2()
2514 amdgpu_crtc->cursor_hot_x = hot_x; in dce_v11_0_crtc_cursor_set2()
2515 amdgpu_crtc->cursor_hot_y = hot_y; in dce_v11_0_crtc_cursor_set2()
2522 if (amdgpu_crtc->cursor_bo) { in dce_v11_0_crtc_cursor_set2()
2523 struct amdgpu_bo *aobj = gem_to_amdgpu_bo(amdgpu_crtc->cursor_bo); in dce_v11_0_crtc_cursor_set2()
2529 drm_gem_object_put(amdgpu_crtc->cursor_bo); in dce_v11_0_crtc_cursor_set2()
2532 amdgpu_crtc->cursor_bo = obj; in dce_v11_0_crtc_cursor_set2()
2540 if (amdgpu_crtc->cursor_bo) { in dce_v11_0_cursor_reset()
2543 dce_v11_0_cursor_move_locked(crtc, amdgpu_crtc->cursor_x, in dce_v11_0_cursor_reset()
2544 amdgpu_crtc->cursor_y); in dce_v11_0_cursor_reset()
2584 struct drm_device *dev = crtc->dev; in dce_v11_0_crtc_dpms()
2591 amdgpu_crtc->enabled = true; in dce_v11_0_crtc_dpms()
2598 amdgpu_crtc->crtc_id); in dce_v11_0_crtc_dpms()
2599 amdgpu_irq_update(adev, &adev->crtc_irq, type); in dce_v11_0_crtc_dpms()
2600 amdgpu_irq_update(adev, &adev->pageflip_irq, type); in dce_v11_0_crtc_dpms()
2608 if (amdgpu_crtc->enabled) { in dce_v11_0_crtc_dpms()
2614 amdgpu_crtc->enabled = false; in dce_v11_0_crtc_dpms()
2638 struct drm_device *dev = crtc->dev; in dce_v11_0_crtc_disable()
2644 if (crtc->primary->fb) { in dce_v11_0_crtc_disable()
2648 abo = gem_to_amdgpu_bo(crtc->primary->fb->obj[0]); in dce_v11_0_crtc_disable()
2662 for (i = 0; i < adev->mode_info.num_crtc; i++) { in dce_v11_0_crtc_disable()
2663 if (adev->mode_info.crtcs[i] && in dce_v11_0_crtc_disable()
2664 adev->mode_info.crtcs[i]->enabled && in dce_v11_0_crtc_disable()
2665 i != amdgpu_crtc->crtc_id && in dce_v11_0_crtc_disable()
2666 amdgpu_crtc->pll_id == adev->mode_info.crtcs[i]->pll_id) { in dce_v11_0_crtc_disable()
2674 switch (amdgpu_crtc->pll_id) { in dce_v11_0_crtc_disable()
2679 amdgpu_atombios_crtc_program_pll(crtc, amdgpu_crtc->crtc_id, amdgpu_crtc->pll_id, in dce_v11_0_crtc_disable()
2689 amdgpu_atombios_crtc_program_pll(crtc, ATOM_CRTC_INVALID, amdgpu_crtc->pll_id, in dce_v11_0_crtc_disable()
2696 amdgpu_crtc->pll_id = ATOM_PPLL_INVALID; in dce_v11_0_crtc_disable()
2697 amdgpu_crtc->adjusted_clock = 0; in dce_v11_0_crtc_disable()
2698 amdgpu_crtc->encoder = NULL; in dce_v11_0_crtc_disable()
2699 amdgpu_crtc->connector = NULL; in dce_v11_0_crtc_disable()
2708 struct drm_device *dev = crtc->dev; in dce_v11_0_crtc_mode_set()
2711 if (!amdgpu_crtc->adjusted_clock) in dce_v11_0_crtc_mode_set()
2712 return -EINVAL; in dce_v11_0_crtc_mode_set()
2714 if ((adev->asic_type == CHIP_POLARIS10) || in dce_v11_0_crtc_mode_set()
2715 (adev->asic_type == CHIP_POLARIS11) || in dce_v11_0_crtc_mode_set()
2716 (adev->asic_type == CHIP_POLARIS12) || in dce_v11_0_crtc_mode_set()
2717 (adev->asic_type == CHIP_VEGAM)) { in dce_v11_0_crtc_mode_set()
2719 to_amdgpu_encoder(amdgpu_crtc->encoder); in dce_v11_0_crtc_mode_set()
2721 amdgpu_atombios_encoder_get_encoder_mode(amdgpu_crtc->encoder); in dce_v11_0_crtc_mode_set()
2724 amdgpu_atombios_crtc_program_pll(crtc, amdgpu_crtc->crtc_id, in dce_v11_0_crtc_mode_set()
2725 amdgpu_crtc->pll_id, in dce_v11_0_crtc_mode_set()
2726 encoder_mode, amdgpu_encoder->encoder_id, in dce_v11_0_crtc_mode_set()
2727 adjusted_mode->clock, 0, 0, 0, 0, in dce_v11_0_crtc_mode_set()
2728 amdgpu_crtc->bpc, amdgpu_crtc->ss_enabled, &amdgpu_crtc->ss); in dce_v11_0_crtc_mode_set()
2738 amdgpu_crtc->hw_mode = *adjusted_mode; in dce_v11_0_crtc_mode_set()
2748 struct drm_device *dev = crtc->dev; in dce_v11_0_crtc_mode_fixup()
2752 list_for_each_entry(encoder, &dev->mode_config.encoder_list, head) { in dce_v11_0_crtc_mode_fixup()
2753 if (encoder->crtc == crtc) { in dce_v11_0_crtc_mode_fixup()
2754 amdgpu_crtc->encoder = encoder; in dce_v11_0_crtc_mode_fixup()
2755 amdgpu_crtc->connector = amdgpu_get_connector_for_encoder(encoder); in dce_v11_0_crtc_mode_fixup()
2759 if ((amdgpu_crtc->encoder == NULL) || (amdgpu_crtc->connector == NULL)) { in dce_v11_0_crtc_mode_fixup()
2760 amdgpu_crtc->encoder = NULL; in dce_v11_0_crtc_mode_fixup()
2761 amdgpu_crtc->connector = NULL; in dce_v11_0_crtc_mode_fixup()
2769 amdgpu_crtc->pll_id = dce_v11_0_pick_pll(crtc); in dce_v11_0_crtc_mode_fixup()
2770 /* if we can't get a PPLL for a non-DP encoder, fail */ in dce_v11_0_crtc_mode_fixup()
2771 if ((amdgpu_crtc->pll_id == ATOM_PPLL_INVALID) && in dce_v11_0_crtc_mode_fixup()
2772 !ENCODER_MODE_IS_DP(amdgpu_atombios_encoder_get_encoder_mode(amdgpu_crtc->encoder))) in dce_v11_0_crtc_mode_fixup()
2810 return -ENOMEM; in dce_v11_0_crtc_init()
2812 drm_crtc_init(adev_to_drm(adev), &amdgpu_crtc->base, &dce_v11_0_crtc_funcs); in dce_v11_0_crtc_init()
2814 drm_mode_crtc_set_gamma_size(&amdgpu_crtc->base, 256); in dce_v11_0_crtc_init()
2815 amdgpu_crtc->crtc_id = index; in dce_v11_0_crtc_init()
2816 adev->mode_info.crtcs[index] = amdgpu_crtc; in dce_v11_0_crtc_init()
2818 amdgpu_crtc->max_cursor_width = 128; in dce_v11_0_crtc_init()
2819 amdgpu_crtc->max_cursor_height = 128; in dce_v11_0_crtc_init()
2820 adev_to_drm(adev)->mode_config.cursor_width = amdgpu_crtc->max_cursor_width; in dce_v11_0_crtc_init()
2821 adev_to_drm(adev)->mode_config.cursor_height = amdgpu_crtc->max_cursor_height; in dce_v11_0_crtc_init()
2823 switch (amdgpu_crtc->crtc_id) { in dce_v11_0_crtc_init()
2826 amdgpu_crtc->crtc_offset = CRTC0_REGISTER_OFFSET; in dce_v11_0_crtc_init()
2829 amdgpu_crtc->crtc_offset = CRTC1_REGISTER_OFFSET; in dce_v11_0_crtc_init()
2832 amdgpu_crtc->crtc_offset = CRTC2_REGISTER_OFFSET; in dce_v11_0_crtc_init()
2835 amdgpu_crtc->crtc_offset = CRTC3_REGISTER_OFFSET; in dce_v11_0_crtc_init()
2838 amdgpu_crtc->crtc_offset = CRTC4_REGISTER_OFFSET; in dce_v11_0_crtc_init()
2841 amdgpu_crtc->crtc_offset = CRTC5_REGISTER_OFFSET; in dce_v11_0_crtc_init()
2845 amdgpu_crtc->pll_id = ATOM_PPLL_INVALID; in dce_v11_0_crtc_init()
2846 amdgpu_crtc->adjusted_clock = 0; in dce_v11_0_crtc_init()
2847 amdgpu_crtc->encoder = NULL; in dce_v11_0_crtc_init()
2848 amdgpu_crtc->connector = NULL; in dce_v11_0_crtc_init()
2849 drm_crtc_helper_add(&amdgpu_crtc->base, &dce_v11_0_crtc_helper_funcs); in dce_v11_0_crtc_init()
2858 adev->audio_endpt_rreg = &dce_v11_0_audio_endpt_rreg; in dce_v11_0_early_init()
2859 adev->audio_endpt_wreg = &dce_v11_0_audio_endpt_wreg; in dce_v11_0_early_init()
2863 adev->mode_info.num_crtc = dce_v11_0_get_num_crtc(adev); in dce_v11_0_early_init()
2865 switch (adev->asic_type) { in dce_v11_0_early_init()
2867 adev->mode_info.num_hpd = 6; in dce_v11_0_early_init()
2868 adev->mode_info.num_dig = 9; in dce_v11_0_early_init()
2871 adev->mode_info.num_hpd = 6; in dce_v11_0_early_init()
2872 adev->mode_info.num_dig = 9; in dce_v11_0_early_init()
2876 adev->mode_info.num_hpd = 6; in dce_v11_0_early_init()
2877 adev->mode_info.num_dig = 6; in dce_v11_0_early_init()
2881 adev->mode_info.num_hpd = 5; in dce_v11_0_early_init()
2882 adev->mode_info.num_dig = 5; in dce_v11_0_early_init()
2886 return -EINVAL; in dce_v11_0_early_init()
2899 for (i = 0; i < adev->mode_info.num_crtc; i++) { in dce_v11_0_sw_init()
2900 r = amdgpu_irq_add_id(adev, AMDGPU_IRQ_CLIENTID_LEGACY, i + 1, &adev->crtc_irq); in dce_v11_0_sw_init()
2906 r = amdgpu_irq_add_id(adev, AMDGPU_IRQ_CLIENTID_LEGACY, i, &adev->pageflip_irq); in dce_v11_0_sw_init()
2911 /* HPD hotplug */ in dce_v11_0_sw_init()
2912 …irq_add_id(adev, AMDGPU_IRQ_CLIENTID_LEGACY, VISLANDS30_IV_SRCID_HOTPLUG_DETECT_A, &adev->hpd_irq); in dce_v11_0_sw_init()
2916 adev_to_drm(adev)->mode_config.funcs = &amdgpu_mode_funcs; in dce_v11_0_sw_init()
2918 adev_to_drm(adev)->mode_config.async_page_flip = true; in dce_v11_0_sw_init()
2920 adev_to_drm(adev)->mode_config.max_width = 16384; in dce_v11_0_sw_init()
2921 adev_to_drm(adev)->mode_config.max_height = 16384; in dce_v11_0_sw_init()
2923 adev_to_drm(adev)->mode_config.preferred_depth = 24; in dce_v11_0_sw_init()
2924 adev_to_drm(adev)->mode_config.prefer_shadow = 1; in dce_v11_0_sw_init()
2926 adev_to_drm(adev)->mode_config.fb_base = adev->gmc.aper_base; in dce_v11_0_sw_init()
2932 adev_to_drm(adev)->mode_config.max_width = 16384; in dce_v11_0_sw_init()
2933 adev_to_drm(adev)->mode_config.max_height = 16384; in dce_v11_0_sw_init()
2937 for (i = 0; i < adev->mode_info.num_crtc; i++) { in dce_v11_0_sw_init()
2946 return -EINVAL; in dce_v11_0_sw_init()
2959 adev->mode_info.mode_config_initialized = true; in dce_v11_0_sw_init()
2967 kfree(adev->mode_info.bios_hardcoded_edid); in dce_v11_0_sw_fini()
2976 adev->mode_info.mode_config_initialized = false; in dce_v11_0_sw_fini()
2993 if ((adev->asic_type == CHIP_POLARIS10) || in dce_v11_0_hw_init()
2994 (adev->asic_type == CHIP_POLARIS11) || in dce_v11_0_hw_init()
2995 (adev->asic_type == CHIP_POLARIS12) || in dce_v11_0_hw_init()
2996 (adev->asic_type == CHIP_VEGAM)) { in dce_v11_0_hw_init()
2997 amdgpu_atombios_crtc_set_dce_clock(adev, adev->clock.default_dispclk, in dce_v11_0_hw_init()
3002 amdgpu_atombios_crtc_set_disp_eng_pll(adev, adev->clock.default_dispclk); in dce_v11_0_hw_init()
3005 /* initialize hpd */ in dce_v11_0_hw_init()
3008 for (i = 0; i < adev->mode_info.audio.num_pins; i++) { in dce_v11_0_hw_init()
3009 dce_v11_0_audio_enable(adev, &adev->mode_info.audio.pin[i], false); in dce_v11_0_hw_init()
3024 for (i = 0; i < adev->mode_info.audio.num_pins; i++) { in dce_v11_0_hw_fini()
3025 dce_v11_0_audio_enable(adev, &adev->mode_info.audio.pin[i], false); in dce_v11_0_hw_fini()
3037 adev->mode_info.bl_level = in dce_v11_0_suspend()
3049 adev->mode_info.bl_level); in dce_v11_0_resume()
3054 if (adev->mode_info.bl_encoder) { in dce_v11_0_resume()
3056 adev->mode_info.bl_encoder); in dce_v11_0_resume()
3057 amdgpu_display_backlight_set_level(adev, adev->mode_info.bl_encoder, in dce_v11_0_resume()
3085 dev_info(adev->dev, "SRBM_SOFT_RESET=0x%08X\n", tmp); in dce_v11_0_soft_reset()
3107 if (crtc >= adev->mode_info.num_crtc) { in dce_v11_0_set_crtc_vblank_interrupt_state()
3136 if (crtc >= adev->mode_info.num_crtc) { in dce_v11_0_set_crtc_vline_interrupt_state()
3161 unsigned hpd, in dce_v11_0_set_hpd_irq_state() argument
3166 if (hpd >= adev->mode_info.num_hpd) { in dce_v11_0_set_hpd_irq_state()
3167 DRM_DEBUG("invalid hdp %d\n", hpd); in dce_v11_0_set_hpd_irq_state()
3173 tmp = RREG32(mmDC_HPD_INT_CONTROL + hpd_offsets[hpd]); in dce_v11_0_set_hpd_irq_state()
3175 WREG32(mmDC_HPD_INT_CONTROL + hpd_offsets[hpd], tmp); in dce_v11_0_set_hpd_irq_state()
3178 tmp = RREG32(mmDC_HPD_INT_CONTROL + hpd_offsets[hpd]); in dce_v11_0_set_hpd_irq_state()
3180 WREG32(mmDC_HPD_INT_CONTROL + hpd_offsets[hpd], tmp); in dce_v11_0_set_hpd_irq_state()
3244 if (type >= adev->mode_info.num_crtc) { in dce_v11_0_set_pageflip_irq_state()
3246 return -EINVAL; in dce_v11_0_set_pageflip_irq_state()
3269 crtc_id = (entry->src_id - 8) >> 1; in dce_v11_0_pageflip_irq()
3270 amdgpu_crtc = adev->mode_info.crtcs[crtc_id]; in dce_v11_0_pageflip_irq()
3272 if (crtc_id >= adev->mode_info.num_crtc) { in dce_v11_0_pageflip_irq()
3274 return -EINVAL; in dce_v11_0_pageflip_irq()
3286 spin_lock_irqsave(&adev_to_drm(adev)->event_lock, flags); in dce_v11_0_pageflip_irq()
3287 works = amdgpu_crtc->pflip_works; in dce_v11_0_pageflip_irq()
3288 if (amdgpu_crtc->pflip_status != AMDGPU_FLIP_SUBMITTED){ in dce_v11_0_pageflip_irq()
3289 DRM_DEBUG_DRIVER("amdgpu_crtc->pflip_status = %d != " in dce_v11_0_pageflip_irq()
3291 amdgpu_crtc->pflip_status, in dce_v11_0_pageflip_irq()
3293 spin_unlock_irqrestore(&adev_to_drm(adev)->event_lock, flags); in dce_v11_0_pageflip_irq()
3298 amdgpu_crtc->pflip_status = AMDGPU_FLIP_NONE; in dce_v11_0_pageflip_irq()
3299 amdgpu_crtc->pflip_works = NULL; in dce_v11_0_pageflip_irq()
3302 if(works->event) in dce_v11_0_pageflip_irq()
3303 drm_crtc_send_vblank_event(&amdgpu_crtc->base, works->event); in dce_v11_0_pageflip_irq()
3305 spin_unlock_irqrestore(&adev_to_drm(adev)->event_lock, flags); in dce_v11_0_pageflip_irq()
3307 drm_crtc_vblank_put(&amdgpu_crtc->base); in dce_v11_0_pageflip_irq()
3308 schedule_work(&works->unpin_work); in dce_v11_0_pageflip_irq()
3314 int hpd) in dce_v11_0_hpd_int_ack() argument
3318 if (hpd >= adev->mode_info.num_hpd) { in dce_v11_0_hpd_int_ack()
3319 DRM_DEBUG("invalid hdp %d\n", hpd); in dce_v11_0_hpd_int_ack()
3323 tmp = RREG32(mmDC_HPD_INT_CONTROL + hpd_offsets[hpd]); in dce_v11_0_hpd_int_ack()
3325 WREG32(mmDC_HPD_INT_CONTROL + hpd_offsets[hpd], tmp); in dce_v11_0_hpd_int_ack()
3333 if (crtc < 0 || crtc >= adev->mode_info.num_crtc) { in dce_v11_0_crtc_vblank_int_ack()
3348 if (crtc < 0 || crtc >= adev->mode_info.num_crtc) { in dce_v11_0_crtc_vline_int_ack()
3362 unsigned crtc = entry->src_id - 1; in dce_v11_0_crtc_irq()
3367 switch (entry->src_data[0]) { in dce_v11_0_crtc_irq()
3390 DRM_DEBUG("Unhandled interrupt: %d %d\n", entry->src_id, entry->src_data[0]); in dce_v11_0_crtc_irq()
3402 unsigned hpd; in dce_v11_0_hpd_irq() local
3404 if (entry->src_data[0] >= adev->mode_info.num_hpd) { in dce_v11_0_hpd_irq()
3405 DRM_DEBUG("Unhandled interrupt: %d %d\n", entry->src_id, entry->src_data[0]); in dce_v11_0_hpd_irq()
3409 hpd = entry->src_data[0]; in dce_v11_0_hpd_irq()
3410 disp_int = RREG32(interrupt_status_offsets[hpd].reg); in dce_v11_0_hpd_irq()
3411 mask = interrupt_status_offsets[hpd].hpd; in dce_v11_0_hpd_irq()
3414 dce_v11_0_hpd_int_ack(adev, hpd); in dce_v11_0_hpd_irq()
3415 schedule_work(&adev->hotplug_work); in dce_v11_0_hpd_irq()
3416 DRM_DEBUG("IH: HPD%d\n", hpd + 1); in dce_v11_0_hpd_irq()
3458 amdgpu_encoder->pixel_clock = adjusted_mode->clock; in dce_v11_0_encoder_mode_set()
3464 dce_v11_0_set_interleave(encoder->crtc, mode); in dce_v11_0_encoder_mode_set()
3474 struct amdgpu_device *adev = drm_to_adev(encoder->dev); in dce_v11_0_encoder_prepare()
3478 if ((amdgpu_encoder->active_device & in dce_v11_0_encoder_prepare()
3482 struct amdgpu_encoder_atom_dig *dig = amdgpu_encoder->enc_priv; in dce_v11_0_encoder_prepare()
3484 dig->dig_encoder = dce_v11_0_pick_dig_encoder(encoder); in dce_v11_0_encoder_prepare()
3485 if (amdgpu_encoder->active_device & ATOM_DEVICE_DFP_SUPPORT) in dce_v11_0_encoder_prepare()
3486 dig->afmt = adev->mode_info.afmt[dig->dig_encoder]; in dce_v11_0_encoder_prepare()
3496 if (amdgpu_connector->router.cd_valid) in dce_v11_0_encoder_prepare()
3500 if (connector->connector_type == DRM_MODE_CONNECTOR_eDP) in dce_v11_0_encoder_prepare()
3513 struct drm_device *dev = encoder->dev; in dce_v11_0_encoder_commit()
3531 dig = amdgpu_encoder->enc_priv; in dce_v11_0_encoder_disable()
3532 dig->dig_encoder = -1; in dce_v11_0_encoder_disable()
3534 amdgpu_encoder->active_device = 0; in dce_v11_0_encoder_disable()
3573 /* no detect for TMDS/LVDS yet */
3598 if (amdgpu_encoder->devices & (ATOM_DEVICE_LCD_SUPPORT)) in dce_v11_0_encoder_destroy()
3600 kfree(amdgpu_encoder->enc_priv); in dce_v11_0_encoder_destroy()
3619 list_for_each_entry(encoder, &dev->mode_config.encoder_list, head) { in dce_v11_0_encoder_add()
3621 if (amdgpu_encoder->encoder_enum == encoder_enum) { in dce_v11_0_encoder_add()
3622 amdgpu_encoder->devices |= supported_device; in dce_v11_0_encoder_add()
3633 encoder = &amdgpu_encoder->base; in dce_v11_0_encoder_add()
3634 switch (adev->mode_info.num_crtc) { in dce_v11_0_encoder_add()
3636 encoder->possible_crtcs = 0x1; in dce_v11_0_encoder_add()
3640 encoder->possible_crtcs = 0x3; in dce_v11_0_encoder_add()
3643 encoder->possible_crtcs = 0x7; in dce_v11_0_encoder_add()
3646 encoder->possible_crtcs = 0xf; in dce_v11_0_encoder_add()
3649 encoder->possible_crtcs = 0x1f; in dce_v11_0_encoder_add()
3652 encoder->possible_crtcs = 0x3f; in dce_v11_0_encoder_add()
3656 amdgpu_encoder->enc_priv = NULL; in dce_v11_0_encoder_add()
3658 amdgpu_encoder->encoder_enum = encoder_enum; in dce_v11_0_encoder_add()
3659 amdgpu_encoder->encoder_id = (encoder_enum & OBJECT_ID_MASK) >> OBJECT_ID_SHIFT; in dce_v11_0_encoder_add()
3660 amdgpu_encoder->devices = supported_device; in dce_v11_0_encoder_add()
3661 amdgpu_encoder->rmx_type = RMX_OFF; in dce_v11_0_encoder_add()
3662 amdgpu_encoder->underscan_type = UNDERSCAN_OFF; in dce_v11_0_encoder_add()
3663 amdgpu_encoder->is_ext_encoder = false; in dce_v11_0_encoder_add()
3664 amdgpu_encoder->caps = caps; in dce_v11_0_encoder_add()
3666 switch (amdgpu_encoder->encoder_id) { in dce_v11_0_encoder_add()
3678 if (amdgpu_encoder->devices & (ATOM_DEVICE_LCD_SUPPORT)) { in dce_v11_0_encoder_add()
3679 amdgpu_encoder->rmx_type = RMX_FULL; in dce_v11_0_encoder_add()
3682 amdgpu_encoder->enc_priv = amdgpu_atombios_encoder_get_lcd_info(amdgpu_encoder); in dce_v11_0_encoder_add()
3683 } else if (amdgpu_encoder->devices & (ATOM_DEVICE_CRT_SUPPORT)) { in dce_v11_0_encoder_add()
3686 amdgpu_encoder->enc_priv = amdgpu_atombios_encoder_get_dig_info(amdgpu_encoder); in dce_v11_0_encoder_add()
3690 amdgpu_encoder->enc_priv = amdgpu_atombios_encoder_get_dig_info(amdgpu_encoder); in dce_v11_0_encoder_add()
3704 amdgpu_encoder->is_ext_encoder = true; in dce_v11_0_encoder_add()
3705 if (amdgpu_encoder->devices & (ATOM_DEVICE_LCD_SUPPORT)) in dce_v11_0_encoder_add()
3708 else if (amdgpu_encoder->devices & (ATOM_DEVICE_CRT_SUPPORT)) in dce_v11_0_encoder_add()
3735 adev->mode_info.funcs = &dce_v11_0_display_funcs; in dce_v11_0_set_display_funcs()
3755 if (adev->mode_info.num_crtc > 0) in dce_v11_0_set_irq_funcs()
3756 adev->crtc_irq.num_types = AMDGPU_CRTC_IRQ_VLINE1 + adev->mode_info.num_crtc; in dce_v11_0_set_irq_funcs()
3758 adev->crtc_irq.num_types = 0; in dce_v11_0_set_irq_funcs()
3759 adev->crtc_irq.funcs = &dce_v11_0_crtc_irq_funcs; in dce_v11_0_set_irq_funcs()
3761 adev->pageflip_irq.num_types = adev->mode_info.num_crtc; in dce_v11_0_set_irq_funcs()
3762 adev->pageflip_irq.funcs = &dce_v11_0_pageflip_irq_funcs; in dce_v11_0_set_irq_funcs()
3764 adev->hpd_irq.num_types = adev->mode_info.num_hpd; in dce_v11_0_set_irq_funcs()
3765 adev->hpd_irq.funcs = &dce_v11_0_hpd_irq_funcs; in dce_v11_0_set_irq_funcs()