Lines Matching +full:no +full:- +full:hpd
16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
88 uint32_t hpd; member
94 .hpd = DISP_INTERRUPT_STATUS__DC_HPD1_INTERRUPT_MASK
99 .hpd = DISP_INTERRUPT_STATUS_CONTINUE__DC_HPD2_INTERRUPT_MASK
104 .hpd = DISP_INTERRUPT_STATUS_CONTINUE2__DC_HPD3_INTERRUPT_MASK
109 .hpd = DISP_INTERRUPT_STATUS_CONTINUE3__DC_HPD4_INTERRUPT_MASK
114 .hpd = DISP_INTERRUPT_STATUS_CONTINUE4__DC_HPD5_INTERRUPT_MASK
119 .hpd = DISP_INTERRUPT_STATUS_CONTINUE5__DC_HPD6_INTERRUPT_MASK
152 switch (adev->asic_type) { in dce_v10_0_init_golden_registers()
180 spin_lock_irqsave(&adev->audio_endpt_idx_lock, flags); in dce_v10_0_audio_endpt_rreg()
183 spin_unlock_irqrestore(&adev->audio_endpt_idx_lock, flags); in dce_v10_0_audio_endpt_rreg()
193 spin_lock_irqsave(&adev->audio_endpt_idx_lock, flags); in dce_v10_0_audio_endpt_wreg()
196 spin_unlock_irqrestore(&adev->audio_endpt_idx_lock, flags); in dce_v10_0_audio_endpt_wreg()
201 if (crtc >= adev->mode_info.num_crtc) in dce_v10_0_vblank_get_counter()
212 for (i = 0; i < adev->mode_info.num_crtc; i++) in dce_v10_0_pageflip_interrupt_init()
213 amdgpu_irq_get(adev, &adev->pageflip_irq, i); in dce_v10_0_pageflip_interrupt_init()
221 for (i = 0; i < adev->mode_info.num_crtc; i++) in dce_v10_0_pageflip_interrupt_fini()
222 amdgpu_irq_put(adev, &adev->pageflip_irq, i); in dce_v10_0_pageflip_interrupt_fini()
226 * dce_v10_0_page_flip - pageflip callback.
238 struct amdgpu_crtc *amdgpu_crtc = adev->mode_info.crtcs[crtc_id]; in dce_v10_0_page_flip()
239 struct drm_framebuffer *fb = amdgpu_crtc->base.primary->fb; in dce_v10_0_page_flip()
243 tmp = RREG32(mmGRPH_FLIP_CONTROL + amdgpu_crtc->crtc_offset); in dce_v10_0_page_flip()
246 WREG32(mmGRPH_FLIP_CONTROL + amdgpu_crtc->crtc_offset, tmp); in dce_v10_0_page_flip()
248 WREG32(mmGRPH_PITCH + amdgpu_crtc->crtc_offset, in dce_v10_0_page_flip()
249 fb->pitches[0] / fb->format->cpp[0]); in dce_v10_0_page_flip()
251 WREG32(mmGRPH_PRIMARY_SURFACE_ADDRESS_HIGH + amdgpu_crtc->crtc_offset, in dce_v10_0_page_flip()
254 WREG32(mmGRPH_PRIMARY_SURFACE_ADDRESS + amdgpu_crtc->crtc_offset, in dce_v10_0_page_flip()
257 RREG32(mmGRPH_PRIMARY_SURFACE_ADDRESS + amdgpu_crtc->crtc_offset); in dce_v10_0_page_flip()
263 if ((crtc < 0) || (crtc >= adev->mode_info.num_crtc)) in dce_v10_0_crtc_get_scanoutpos()
264 return -EINVAL; in dce_v10_0_crtc_get_scanoutpos()
273 * dce_v10_0_hpd_sense - hpd sense callback.
276 * @hpd: hpd (hotplug detect) pin
282 enum amdgpu_hpd_id hpd) in dce_v10_0_hpd_sense() argument
286 if (hpd >= adev->mode_info.num_hpd) in dce_v10_0_hpd_sense()
289 if (RREG32(mmDC_HPD_INT_STATUS + hpd_offsets[hpd]) & in dce_v10_0_hpd_sense()
297 * dce_v10_0_hpd_set_polarity - hpd set polarity callback.
300 * @hpd: hpd (hotplug detect) pin
302 * Set the polarity of the hpd pin (evergreen+).
305 enum amdgpu_hpd_id hpd) in dce_v10_0_hpd_set_polarity() argument
308 bool connected = dce_v10_0_hpd_sense(adev, hpd); in dce_v10_0_hpd_set_polarity()
310 if (hpd >= adev->mode_info.num_hpd) in dce_v10_0_hpd_set_polarity()
313 tmp = RREG32(mmDC_HPD_INT_CONTROL + hpd_offsets[hpd]); in dce_v10_0_hpd_set_polarity()
318 WREG32(mmDC_HPD_INT_CONTROL + hpd_offsets[hpd], tmp); in dce_v10_0_hpd_set_polarity()
322 * dce_v10_0_hpd_init - hpd setup callback.
326 * Setup the hpd pins used by the card (evergreen+).
327 * Enable the pin, set the polarity, and enable the hpd interrupts.
340 if (amdgpu_connector->hpd.hpd >= adev->mode_info.num_hpd) in dce_v10_0_hpd_init()
343 if (connector->connector_type == DRM_MODE_CONNECTOR_eDP || in dce_v10_0_hpd_init()
344 connector->connector_type == DRM_MODE_CONNECTOR_LVDS) { in dce_v10_0_hpd_init()
345 /* don't try to enable hpd on eDP or LVDS avoid breaking the in dce_v10_0_hpd_init()
350 tmp = RREG32(mmDC_HPD_INT_CONTROL + hpd_offsets[amdgpu_connector->hpd.hpd]); in dce_v10_0_hpd_init()
352 WREG32(mmDC_HPD_INT_CONTROL + hpd_offsets[amdgpu_connector->hpd.hpd], tmp); in dce_v10_0_hpd_init()
356 tmp = RREG32(mmDC_HPD_CONTROL + hpd_offsets[amdgpu_connector->hpd.hpd]); in dce_v10_0_hpd_init()
358 WREG32(mmDC_HPD_CONTROL + hpd_offsets[amdgpu_connector->hpd.hpd], tmp); in dce_v10_0_hpd_init()
360 tmp = RREG32(mmDC_HPD_TOGGLE_FILT_CNTL + hpd_offsets[amdgpu_connector->hpd.hpd]); in dce_v10_0_hpd_init()
367 WREG32(mmDC_HPD_TOGGLE_FILT_CNTL + hpd_offsets[amdgpu_connector->hpd.hpd], tmp); in dce_v10_0_hpd_init()
369 dce_v10_0_hpd_set_polarity(adev, amdgpu_connector->hpd.hpd); in dce_v10_0_hpd_init()
370 amdgpu_irq_get(adev, &adev->hpd_irq, in dce_v10_0_hpd_init()
371 amdgpu_connector->hpd.hpd); in dce_v10_0_hpd_init()
377 * dce_v10_0_hpd_fini - hpd tear down callback.
381 * Tear down the hpd pins used by the card (evergreen+).
382 * Disable the hpd interrupts.
395 if (amdgpu_connector->hpd.hpd >= adev->mode_info.num_hpd) in dce_v10_0_hpd_fini()
398 tmp = RREG32(mmDC_HPD_CONTROL + hpd_offsets[amdgpu_connector->hpd.hpd]); in dce_v10_0_hpd_fini()
400 WREG32(mmDC_HPD_CONTROL + hpd_offsets[amdgpu_connector->hpd.hpd], tmp); in dce_v10_0_hpd_fini()
402 amdgpu_irq_put(adev, &adev->hpd_irq, in dce_v10_0_hpd_fini()
403 amdgpu_connector->hpd.hpd); in dce_v10_0_hpd_fini()
419 for (i = 0; i < adev->mode_info.num_crtc; i++) { in dce_v10_0_is_display_hung()
428 for (i = 0; i < adev->mode_info.num_crtc; i++) { in dce_v10_0_is_display_hung()
469 switch (adev->asic_type) { in dce_v10_0_get_num_crtc()
506 struct drm_device *dev = encoder->dev; in dce_v10_0_program_fmt()
509 struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(encoder->crtc); in dce_v10_0_program_fmt()
518 dither = amdgpu_connector->dither; in dce_v10_0_program_fmt()
522 if (amdgpu_encoder->devices & ATOM_DEVICE_LCD_SUPPORT) in dce_v10_0_program_fmt()
526 if ((amdgpu_encoder->encoder_id == ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DAC1) || in dce_v10_0_program_fmt()
527 (amdgpu_encoder->encoder_id == ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DAC2)) in dce_v10_0_program_fmt()
577 WREG32(mmFMT_BIT_DEPTH_CONTROL + amdgpu_crtc->crtc_offset, tmp); in dce_v10_0_program_fmt()
583 * dce_v10_0_line_buffer_adjust - Set up the line buffer
599 u32 pipe_offset = amdgpu_crtc->crtc_id; in dce_v10_0_line_buffer_adjust()
608 if (amdgpu_crtc->base.enabled && mode) { in dce_v10_0_line_buffer_adjust()
609 if (mode->crtc_hdisplay < 1920) { in dce_v10_0_line_buffer_adjust()
612 } else if (mode->crtc_hdisplay < 2560) { in dce_v10_0_line_buffer_adjust()
615 } else if (mode->crtc_hdisplay < 4096) { in dce_v10_0_line_buffer_adjust()
617 buffer_alloc = (adev->flags & AMD_IS_APU) ? 2 : 4; in dce_v10_0_line_buffer_adjust()
621 buffer_alloc = (adev->flags & AMD_IS_APU) ? 2 : 4; in dce_v10_0_line_buffer_adjust()
628 tmp = RREG32(mmLB_MEMORY_CTRL + amdgpu_crtc->crtc_offset); in dce_v10_0_line_buffer_adjust()
630 WREG32(mmLB_MEMORY_CTRL + amdgpu_crtc->crtc_offset, tmp); in dce_v10_0_line_buffer_adjust()
636 for (i = 0; i < adev->usec_timeout; i++) { in dce_v10_0_line_buffer_adjust()
643 if (amdgpu_crtc->base.enabled && mode) { in dce_v10_0_line_buffer_adjust()
655 /* controller not enabled, so no lb used */ in dce_v10_0_line_buffer_adjust()
660 * cik_get_number_of_dram_channels - get the number of dram channels
712 * dce_v10_0_dram_bandwidth - get the dram bandwidth
728 yclk.full = dfixed_const(wm->yclk); in dce_v10_0_dram_bandwidth()
730 dram_channels.full = dfixed_const(wm->dram_channels * 4); in dce_v10_0_dram_bandwidth()
741 * dce_v10_0_dram_bandwidth_for_display - get the dram bandwidth for display
757 yclk.full = dfixed_const(wm->yclk); in dce_v10_0_dram_bandwidth_for_display()
759 dram_channels.full = dfixed_const(wm->dram_channels * 4); in dce_v10_0_dram_bandwidth_for_display()
770 * dce_v10_0_data_return_bandwidth - get the data return bandwidth
786 sclk.full = dfixed_const(wm->sclk); in dce_v10_0_data_return_bandwidth()
799 * dce_v10_0_dmif_request_bandwidth - get the dmif bandwidth
815 disp_clk.full = dfixed_const(wm->disp_clk); in dce_v10_0_dmif_request_bandwidth()
830 * dce_v10_0_available_bandwidth - get the min available bandwidth
849 * dce_v10_0_average_bandwidth - get the average available bandwidth
870 line_time.full = dfixed_const(wm->active_time + wm->blank_time); in dce_v10_0_average_bandwidth()
872 bpp.full = dfixed_const(wm->bytes_per_pixel); in dce_v10_0_average_bandwidth()
873 src_width.full = dfixed_const(wm->src_width); in dce_v10_0_average_bandwidth()
875 bandwidth.full = dfixed_mul(bandwidth, wm->vsc); in dce_v10_0_average_bandwidth()
882 * dce_v10_0_latency_watermark - get the latency watermark
897 u32 dc_latency = 40000000 / wm->disp_clk; /* dc pipe latency */ in dce_v10_0_latency_watermark()
898 u32 other_heads_data_return_time = ((wm->num_heads + 1) * worst_chunk_return_time) + in dce_v10_0_latency_watermark()
899 (wm->num_heads * cursor_line_pair_return_time); in dce_v10_0_latency_watermark()
905 if (wm->num_heads == 0) in dce_v10_0_latency_watermark()
910 if ((wm->vsc.full > a.full) || in dce_v10_0_latency_watermark()
911 ((wm->vsc.full > b.full) && (wm->vtaps >= 3)) || in dce_v10_0_latency_watermark()
912 (wm->vtaps >= 5) || in dce_v10_0_latency_watermark()
913 ((wm->vsc.full >= a.full) && wm->interlaced)) in dce_v10_0_latency_watermark()
919 b.full = dfixed_const(wm->num_heads); in dce_v10_0_latency_watermark()
921 tmp = div_u64((u64) dmif_size * (u64) wm->disp_clk, mc_latency + 512); in dce_v10_0_latency_watermark()
924 lb_fill_bw = min(tmp, wm->disp_clk * wm->bytes_per_pixel / 1000); in dce_v10_0_latency_watermark()
926 a.full = dfixed_const(max_src_lines_per_dst_line * wm->src_width * wm->bytes_per_pixel); in dce_v10_0_latency_watermark()
933 if (line_fill_time < wm->active_time) in dce_v10_0_latency_watermark()
936 return latency + (line_fill_time - wm->active_time); in dce_v10_0_latency_watermark()
941 * dce_v10_0_average_bandwidth_vs_dram_bandwidth_for_display - check
954 (dce_v10_0_dram_bandwidth_for_display(wm) / wm->num_heads)) in dce_v10_0_average_bandwidth_vs_dram_bandwidth_for_display()
961 * dce_v10_0_average_bandwidth_vs_available_bandwidth - check
974 (dce_v10_0_available_bandwidth(wm) / wm->num_heads)) in dce_v10_0_average_bandwidth_vs_available_bandwidth()
981 * dce_v10_0_check_latency_hiding - check latency hiding
991 u32 lb_partitions = wm->lb_size / wm->src_width; in dce_v10_0_check_latency_hiding()
992 u32 line_time = wm->active_time + wm->blank_time; in dce_v10_0_check_latency_hiding()
998 if (wm->vsc.full > a.full) in dce_v10_0_check_latency_hiding()
1001 if (lb_partitions <= (wm->vtaps + 1)) in dce_v10_0_check_latency_hiding()
1007 latency_hiding = (latency_tolerant_lines * line_time + wm->blank_time); in dce_v10_0_check_latency_hiding()
1016 * dce_v10_0_program_watermarks - program display watermarks
1030 struct drm_display_mode *mode = &amdgpu_crtc->base.mode; in dce_v10_0_program_watermarks()
1037 if (amdgpu_crtc->base.enabled && num_heads && mode) { in dce_v10_0_program_watermarks()
1038 active_time = (u32) div_u64((u64)mode->crtc_hdisplay * 1000000, in dce_v10_0_program_watermarks()
1039 (u32)mode->clock); in dce_v10_0_program_watermarks()
1040 line_time = (u32) div_u64((u64)mode->crtc_htotal * 1000000, in dce_v10_0_program_watermarks()
1041 (u32)mode->clock); in dce_v10_0_program_watermarks()
1045 if (adev->pm.dpm_enabled) { in dce_v10_0_program_watermarks()
1051 wm_high.yclk = adev->pm.current_mclk * 10; in dce_v10_0_program_watermarks()
1052 wm_high.sclk = adev->pm.current_sclk * 10; in dce_v10_0_program_watermarks()
1055 wm_high.disp_clk = mode->clock; in dce_v10_0_program_watermarks()
1056 wm_high.src_width = mode->crtc_hdisplay; in dce_v10_0_program_watermarks()
1058 wm_high.blank_time = line_time - wm_high.active_time; in dce_v10_0_program_watermarks()
1060 if (mode->flags & DRM_MODE_FLAG_INTERLACE) in dce_v10_0_program_watermarks()
1062 wm_high.vsc = amdgpu_crtc->vsc; in dce_v10_0_program_watermarks()
1064 if (amdgpu_crtc->rmx_type != RMX_OFF) in dce_v10_0_program_watermarks()
1079 (adev->mode_info.disp_priority == 2)) { in dce_v10_0_program_watermarks()
1084 if (adev->pm.dpm_enabled) { in dce_v10_0_program_watermarks()
1090 wm_low.yclk = adev->pm.current_mclk * 10; in dce_v10_0_program_watermarks()
1091 wm_low.sclk = adev->pm.current_sclk * 10; in dce_v10_0_program_watermarks()
1094 wm_low.disp_clk = mode->clock; in dce_v10_0_program_watermarks()
1095 wm_low.src_width = mode->crtc_hdisplay; in dce_v10_0_program_watermarks()
1097 wm_low.blank_time = line_time - wm_low.active_time; in dce_v10_0_program_watermarks()
1099 if (mode->flags & DRM_MODE_FLAG_INTERLACE) in dce_v10_0_program_watermarks()
1101 wm_low.vsc = amdgpu_crtc->vsc; in dce_v10_0_program_watermarks()
1103 if (amdgpu_crtc->rmx_type != RMX_OFF) in dce_v10_0_program_watermarks()
1118 (adev->mode_info.disp_priority == 2)) { in dce_v10_0_program_watermarks()
1121 lb_vblank_lead_lines = DIV_ROUND_UP(lb_size, mode->crtc_hdisplay); in dce_v10_0_program_watermarks()
1125 wm_mask = RREG32(mmDPG_WATERMARK_MASK_CONTROL + amdgpu_crtc->crtc_offset); in dce_v10_0_program_watermarks()
1127 WREG32(mmDPG_WATERMARK_MASK_CONTROL + amdgpu_crtc->crtc_offset, tmp); in dce_v10_0_program_watermarks()
1128 tmp = RREG32(mmDPG_PIPE_URGENCY_CONTROL + amdgpu_crtc->crtc_offset); in dce_v10_0_program_watermarks()
1131 WREG32(mmDPG_PIPE_URGENCY_CONTROL + amdgpu_crtc->crtc_offset, tmp); in dce_v10_0_program_watermarks()
1134 WREG32(mmDPG_WATERMARK_MASK_CONTROL + amdgpu_crtc->crtc_offset, tmp); in dce_v10_0_program_watermarks()
1135 tmp = RREG32(mmDPG_PIPE_URGENCY_CONTROL + amdgpu_crtc->crtc_offset); in dce_v10_0_program_watermarks()
1138 WREG32(mmDPG_PIPE_URGENCY_CONTROL + amdgpu_crtc->crtc_offset, tmp); in dce_v10_0_program_watermarks()
1140 WREG32(mmDPG_WATERMARK_MASK_CONTROL + amdgpu_crtc->crtc_offset, wm_mask); in dce_v10_0_program_watermarks()
1143 amdgpu_crtc->line_time = line_time; in dce_v10_0_program_watermarks()
1144 amdgpu_crtc->wm_high = latency_watermark_a; in dce_v10_0_program_watermarks()
1145 amdgpu_crtc->wm_low = latency_watermark_b; in dce_v10_0_program_watermarks()
1147 amdgpu_crtc->lb_vblank_lead_lines = lb_vblank_lead_lines; in dce_v10_0_program_watermarks()
1151 * dce_v10_0_bandwidth_update - program display watermarks
1166 for (i = 0; i < adev->mode_info.num_crtc; i++) { in dce_v10_0_bandwidth_update()
1167 if (adev->mode_info.crtcs[i]->base.enabled) in dce_v10_0_bandwidth_update()
1170 for (i = 0; i < adev->mode_info.num_crtc; i++) { in dce_v10_0_bandwidth_update()
1171 mode = &adev->mode_info.crtcs[i]->base.mode; in dce_v10_0_bandwidth_update()
1172 lb_size = dce_v10_0_line_buffer_adjust(adev, adev->mode_info.crtcs[i], mode); in dce_v10_0_bandwidth_update()
1173 dce_v10_0_program_watermarks(adev, adev->mode_info.crtcs[i], in dce_v10_0_bandwidth_update()
1183 for (i = 0; i < adev->mode_info.audio.num_pins; i++) { in dce_v10_0_audio_get_connected_pins()
1184 offset = adev->mode_info.audio.pin[i].offset; in dce_v10_0_audio_get_connected_pins()
1190 adev->mode_info.audio.pin[i].connected = false; in dce_v10_0_audio_get_connected_pins()
1192 adev->mode_info.audio.pin[i].connected = true; in dce_v10_0_audio_get_connected_pins()
1202 for (i = 0; i < adev->mode_info.audio.num_pins; i++) { in dce_v10_0_audio_get_pin()
1203 if (adev->mode_info.audio.pin[i].connected) in dce_v10_0_audio_get_pin()
1204 return &adev->mode_info.audio.pin[i]; in dce_v10_0_audio_get_pin()
1206 DRM_ERROR("No connected audio pins found!\n"); in dce_v10_0_audio_get_pin()
1212 struct amdgpu_device *adev = drm_to_adev(encoder->dev); in dce_v10_0_afmt_audio_select_pin()
1214 struct amdgpu_encoder_atom_dig *dig = amdgpu_encoder->enc_priv; in dce_v10_0_afmt_audio_select_pin()
1217 if (!dig || !dig->afmt || !dig->afmt->pin) in dce_v10_0_afmt_audio_select_pin()
1220 tmp = RREG32(mmAFMT_AUDIO_SRC_CONTROL + dig->afmt->offset); in dce_v10_0_afmt_audio_select_pin()
1221 tmp = REG_SET_FIELD(tmp, AFMT_AUDIO_SRC_CONTROL, AFMT_AUDIO_SRC_SELECT, dig->afmt->pin->id); in dce_v10_0_afmt_audio_select_pin()
1222 WREG32(mmAFMT_AUDIO_SRC_CONTROL + dig->afmt->offset, tmp); in dce_v10_0_afmt_audio_select_pin()
1228 struct drm_device *dev = encoder->dev; in dce_v10_0_audio_write_latency_fields()
1231 struct amdgpu_encoder_atom_dig *dig = amdgpu_encoder->enc_priv; in dce_v10_0_audio_write_latency_fields()
1238 if (!dig || !dig->afmt || !dig->afmt->pin) in dce_v10_0_audio_write_latency_fields()
1243 if (connector->encoder == encoder) { in dce_v10_0_audio_write_latency_fields()
1255 if (mode->flags & DRM_MODE_FLAG_INTERLACE) in dce_v10_0_audio_write_latency_fields()
1257 if (connector->latency_present[interlace]) { in dce_v10_0_audio_write_latency_fields()
1259 VIDEO_LIPSYNC, connector->video_latency[interlace]); in dce_v10_0_audio_write_latency_fields()
1261 AUDIO_LIPSYNC, connector->audio_latency[interlace]); in dce_v10_0_audio_write_latency_fields()
1268 WREG32_AUDIO_ENDPT(dig->afmt->pin->offset, in dce_v10_0_audio_write_latency_fields()
1274 struct drm_device *dev = encoder->dev; in dce_v10_0_audio_write_speaker_allocation()
1277 struct amdgpu_encoder_atom_dig *dig = amdgpu_encoder->enc_priv; in dce_v10_0_audio_write_speaker_allocation()
1285 if (!dig || !dig->afmt || !dig->afmt->pin) in dce_v10_0_audio_write_speaker_allocation()
1290 if (connector->encoder == encoder) { in dce_v10_0_audio_write_speaker_allocation()
1309 tmp = RREG32_AUDIO_ENDPT(dig->afmt->pin->offset, in dce_v10_0_audio_write_speaker_allocation()
1322 WREG32_AUDIO_ENDPT(dig->afmt->pin->offset, in dce_v10_0_audio_write_speaker_allocation()
1330 struct drm_device *dev = encoder->dev; in dce_v10_0_audio_write_sad_regs()
1333 struct amdgpu_encoder_atom_dig *dig = amdgpu_encoder->enc_priv; in dce_v10_0_audio_write_sad_regs()
1355 if (!dig || !dig->afmt || !dig->afmt->pin) in dce_v10_0_audio_write_sad_regs()
1360 if (connector->encoder == encoder) { in dce_v10_0_audio_write_sad_regs()
1382 int max_channels = -1; in dce_v10_0_audio_write_sad_regs()
1388 if (sad->format == eld_reg_to_type[i][1]) { in dce_v10_0_audio_write_sad_regs()
1389 if (sad->channels > max_channels) { in dce_v10_0_audio_write_sad_regs()
1391 MAX_CHANNELS, sad->channels); in dce_v10_0_audio_write_sad_regs()
1393 DESCRIPTOR_BYTE_2, sad->byte2); in dce_v10_0_audio_write_sad_regs()
1395 SUPPORTED_FREQUENCIES, sad->freq); in dce_v10_0_audio_write_sad_regs()
1396 max_channels = sad->channels; in dce_v10_0_audio_write_sad_regs()
1399 if (sad->format == HDMI_AUDIO_CODING_TYPE_PCM) in dce_v10_0_audio_write_sad_regs()
1400 stereo_freqs |= sad->freq; in dce_v10_0_audio_write_sad_regs()
1408 WREG32_AUDIO_ENDPT(dig->afmt->pin->offset, eld_reg_to_type[i][0], tmp); in dce_v10_0_audio_write_sad_regs()
1421 WREG32_AUDIO_ENDPT(pin->offset, ixAZALIA_F0_CODEC_PIN_CONTROL_HOT_PLUG_CONTROL, in dce_v10_0_audio_enable()
1443 adev->mode_info.audio.enabled = true; in dce_v10_0_audio_init()
1445 adev->mode_info.audio.num_pins = 7; in dce_v10_0_audio_init()
1447 for (i = 0; i < adev->mode_info.audio.num_pins; i++) { in dce_v10_0_audio_init()
1448 adev->mode_info.audio.pin[i].channels = -1; in dce_v10_0_audio_init()
1449 adev->mode_info.audio.pin[i].rate = -1; in dce_v10_0_audio_init()
1450 adev->mode_info.audio.pin[i].bits_per_sample = -1; in dce_v10_0_audio_init()
1451 adev->mode_info.audio.pin[i].status_bits = 0; in dce_v10_0_audio_init()
1452 adev->mode_info.audio.pin[i].category_code = 0; in dce_v10_0_audio_init()
1453 adev->mode_info.audio.pin[i].connected = false; in dce_v10_0_audio_init()
1454 adev->mode_info.audio.pin[i].offset = pin_offsets[i]; in dce_v10_0_audio_init()
1455 adev->mode_info.audio.pin[i].id = i; in dce_v10_0_audio_init()
1458 dce_v10_0_audio_enable(adev, &adev->mode_info.audio.pin[i], false); in dce_v10_0_audio_init()
1471 if (!adev->mode_info.audio.enabled) in dce_v10_0_audio_fini()
1474 for (i = 0; i < adev->mode_info.audio.num_pins; i++) in dce_v10_0_audio_fini()
1475 dce_v10_0_audio_enable(adev, &adev->mode_info.audio.pin[i], false); in dce_v10_0_audio_fini()
1477 adev->mode_info.audio.enabled = false; in dce_v10_0_audio_fini()
1485 struct drm_device *dev = encoder->dev; in dce_v10_0_afmt_update_ACR()
1489 struct amdgpu_encoder_atom_dig *dig = amdgpu_encoder->enc_priv; in dce_v10_0_afmt_update_ACR()
1492 tmp = RREG32(mmHDMI_ACR_32_0 + dig->afmt->offset); in dce_v10_0_afmt_update_ACR()
1494 WREG32(mmHDMI_ACR_32_0 + dig->afmt->offset, tmp); in dce_v10_0_afmt_update_ACR()
1495 tmp = RREG32(mmHDMI_ACR_32_1 + dig->afmt->offset); in dce_v10_0_afmt_update_ACR()
1497 WREG32(mmHDMI_ACR_32_1 + dig->afmt->offset, tmp); in dce_v10_0_afmt_update_ACR()
1499 tmp = RREG32(mmHDMI_ACR_44_0 + dig->afmt->offset); in dce_v10_0_afmt_update_ACR()
1501 WREG32(mmHDMI_ACR_44_0 + dig->afmt->offset, tmp); in dce_v10_0_afmt_update_ACR()
1502 tmp = RREG32(mmHDMI_ACR_44_1 + dig->afmt->offset); in dce_v10_0_afmt_update_ACR()
1504 WREG32(mmHDMI_ACR_44_1 + dig->afmt->offset, tmp); in dce_v10_0_afmt_update_ACR()
1506 tmp = RREG32(mmHDMI_ACR_48_0 + dig->afmt->offset); in dce_v10_0_afmt_update_ACR()
1508 WREG32(mmHDMI_ACR_48_0 + dig->afmt->offset, tmp); in dce_v10_0_afmt_update_ACR()
1509 tmp = RREG32(mmHDMI_ACR_48_1 + dig->afmt->offset); in dce_v10_0_afmt_update_ACR()
1511 WREG32(mmHDMI_ACR_48_1 + dig->afmt->offset, tmp); in dce_v10_0_afmt_update_ACR()
1521 struct drm_device *dev = encoder->dev; in dce_v10_0_afmt_update_avi_infoframe()
1524 struct amdgpu_encoder_atom_dig *dig = amdgpu_encoder->enc_priv; in dce_v10_0_afmt_update_avi_infoframe()
1528 WREG32(mmAFMT_AVI_INFO0 + dig->afmt->offset, in dce_v10_0_afmt_update_avi_infoframe()
1530 WREG32(mmAFMT_AVI_INFO1 + dig->afmt->offset, in dce_v10_0_afmt_update_avi_infoframe()
1532 WREG32(mmAFMT_AVI_INFO2 + dig->afmt->offset, in dce_v10_0_afmt_update_avi_infoframe()
1534 WREG32(mmAFMT_AVI_INFO3 + dig->afmt->offset, in dce_v10_0_afmt_update_avi_infoframe()
1540 struct drm_device *dev = encoder->dev; in dce_v10_0_audio_set_dto()
1543 struct amdgpu_encoder_atom_dig *dig = amdgpu_encoder->enc_priv; in dce_v10_0_audio_set_dto()
1544 struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(encoder->crtc); in dce_v10_0_audio_set_dto()
1549 if (!dig || !dig->afmt) in dce_v10_0_audio_set_dto()
1559 amdgpu_crtc->crtc_id); in dce_v10_0_audio_set_dto()
1571 struct drm_device *dev = encoder->dev; in dce_v10_0_afmt_setmode()
1574 struct amdgpu_encoder_atom_dig *dig = amdgpu_encoder->enc_priv; in dce_v10_0_afmt_setmode()
1582 if (!dig || !dig->afmt) in dce_v10_0_afmt_setmode()
1586 if (!dig->afmt->enabled) in dce_v10_0_afmt_setmode()
1590 if (encoder->crtc) { in dce_v10_0_afmt_setmode()
1591 struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(encoder->crtc); in dce_v10_0_afmt_setmode()
1592 bpc = amdgpu_crtc->bpc; in dce_v10_0_afmt_setmode()
1596 dig->afmt->pin = dce_v10_0_audio_get_pin(adev); in dce_v10_0_afmt_setmode()
1597 dce_v10_0_audio_enable(adev, dig->afmt->pin, false); in dce_v10_0_afmt_setmode()
1599 dce_v10_0_audio_set_dto(encoder, mode->clock); in dce_v10_0_afmt_setmode()
1601 tmp = RREG32(mmHDMI_VBI_PACKET_CONTROL + dig->afmt->offset); in dce_v10_0_afmt_setmode()
1603 WREG32(mmHDMI_VBI_PACKET_CONTROL + dig->afmt->offset, tmp); /* send null packets when required */ in dce_v10_0_afmt_setmode()
1605 WREG32(mmAFMT_AUDIO_CRC_CONTROL + dig->afmt->offset, 0x1000); in dce_v10_0_afmt_setmode()
1607 tmp = RREG32(mmHDMI_CONTROL + dig->afmt->offset); in dce_v10_0_afmt_setmode()
1617 connector->name, bpc); in dce_v10_0_afmt_setmode()
1623 connector->name); in dce_v10_0_afmt_setmode()
1629 connector->name); in dce_v10_0_afmt_setmode()
1632 WREG32(mmHDMI_CONTROL + dig->afmt->offset, tmp); in dce_v10_0_afmt_setmode()
1634 tmp = RREG32(mmHDMI_VBI_PACKET_CONTROL + dig->afmt->offset); in dce_v10_0_afmt_setmode()
1638 WREG32(mmHDMI_VBI_PACKET_CONTROL + dig->afmt->offset, tmp); in dce_v10_0_afmt_setmode()
1640 tmp = RREG32(mmHDMI_INFOFRAME_CONTROL0 + dig->afmt->offset); in dce_v10_0_afmt_setmode()
1645 WREG32(mmHDMI_INFOFRAME_CONTROL0 + dig->afmt->offset, tmp); in dce_v10_0_afmt_setmode()
1647 tmp = RREG32(mmAFMT_INFOFRAME_CONTROL0 + dig->afmt->offset); in dce_v10_0_afmt_setmode()
1650 WREG32(mmAFMT_INFOFRAME_CONTROL0 + dig->afmt->offset, tmp); in dce_v10_0_afmt_setmode()
1652 tmp = RREG32(mmHDMI_INFOFRAME_CONTROL1 + dig->afmt->offset); in dce_v10_0_afmt_setmode()
1655 WREG32(mmHDMI_INFOFRAME_CONTROL1 + dig->afmt->offset, tmp); in dce_v10_0_afmt_setmode()
1657 WREG32(mmHDMI_GC + dig->afmt->offset, 0); /* unset HDMI_GC_AVMUTE */ in dce_v10_0_afmt_setmode()
1659 tmp = RREG32(mmHDMI_AUDIO_PACKET_CONTROL + dig->afmt->offset); in dce_v10_0_afmt_setmode()
1664 WREG32(mmHDMI_AUDIO_PACKET_CONTROL + dig->afmt->offset, tmp); in dce_v10_0_afmt_setmode()
1666 tmp = RREG32(mmAFMT_AUDIO_PACKET_CONTROL + dig->afmt->offset); in dce_v10_0_afmt_setmode()
1669 WREG32(mmAFMT_AUDIO_PACKET_CONTROL + dig->afmt->offset, tmp); in dce_v10_0_afmt_setmode()
1671 tmp = RREG32(mmHDMI_ACR_PACKET_CONTROL + dig->afmt->offset); in dce_v10_0_afmt_setmode()
1680 WREG32(mmHDMI_ACR_PACKET_CONTROL + dig->afmt->offset, tmp); in dce_v10_0_afmt_setmode()
1682 dce_v10_0_afmt_update_ACR(encoder, mode->clock); in dce_v10_0_afmt_setmode()
1684 tmp = RREG32(mmAFMT_60958_0 + dig->afmt->offset); in dce_v10_0_afmt_setmode()
1686 WREG32(mmAFMT_60958_0 + dig->afmt->offset, tmp); in dce_v10_0_afmt_setmode()
1688 tmp = RREG32(mmAFMT_60958_1 + dig->afmt->offset); in dce_v10_0_afmt_setmode()
1690 WREG32(mmAFMT_60958_1 + dig->afmt->offset, tmp); in dce_v10_0_afmt_setmode()
1692 tmp = RREG32(mmAFMT_60958_2 + dig->afmt->offset); in dce_v10_0_afmt_setmode()
1699 WREG32(mmAFMT_60958_2 + dig->afmt->offset, tmp); in dce_v10_0_afmt_setmode()
1703 WREG32(mmAFMT_AUDIO_PACKET_CONTROL2 + dig->afmt->offset, in dce_v10_0_afmt_setmode()
1724 tmp = RREG32(mmHDMI_INFOFRAME_CONTROL0 + dig->afmt->offset); in dce_v10_0_afmt_setmode()
1729 WREG32(mmHDMI_INFOFRAME_CONTROL0 + dig->afmt->offset, tmp); in dce_v10_0_afmt_setmode()
1731 tmp = RREG32(mmHDMI_INFOFRAME_CONTROL1 + dig->afmt->offset); in dce_v10_0_afmt_setmode()
1733 WREG32(mmHDMI_INFOFRAME_CONTROL1 + dig->afmt->offset, tmp); in dce_v10_0_afmt_setmode()
1735 tmp = RREG32(mmAFMT_AUDIO_PACKET_CONTROL + dig->afmt->offset); in dce_v10_0_afmt_setmode()
1738 WREG32(mmAFMT_AUDIO_PACKET_CONTROL + dig->afmt->offset, tmp); in dce_v10_0_afmt_setmode()
1740 WREG32(mmAFMT_RAMP_CONTROL0 + dig->afmt->offset, 0x00FFFFFF); in dce_v10_0_afmt_setmode()
1741 WREG32(mmAFMT_RAMP_CONTROL1 + dig->afmt->offset, 0x007FFFFF); in dce_v10_0_afmt_setmode()
1742 WREG32(mmAFMT_RAMP_CONTROL2 + dig->afmt->offset, 0x00000001); in dce_v10_0_afmt_setmode()
1743 WREG32(mmAFMT_RAMP_CONTROL3 + dig->afmt->offset, 0x00000001); in dce_v10_0_afmt_setmode()
1746 dce_v10_0_audio_enable(adev, dig->afmt->pin, true); in dce_v10_0_afmt_setmode()
1751 struct drm_device *dev = encoder->dev; in dce_v10_0_afmt_enable()
1754 struct amdgpu_encoder_atom_dig *dig = amdgpu_encoder->enc_priv; in dce_v10_0_afmt_enable()
1756 if (!dig || !dig->afmt) in dce_v10_0_afmt_enable()
1760 if (enable && dig->afmt->enabled) in dce_v10_0_afmt_enable()
1762 if (!enable && !dig->afmt->enabled) in dce_v10_0_afmt_enable()
1765 if (!enable && dig->afmt->pin) { in dce_v10_0_afmt_enable()
1766 dce_v10_0_audio_enable(adev, dig->afmt->pin, false); in dce_v10_0_afmt_enable()
1767 dig->afmt->pin = NULL; in dce_v10_0_afmt_enable()
1770 dig->afmt->enabled = enable; in dce_v10_0_afmt_enable()
1773 enable ? "En" : "Dis", dig->afmt->offset, amdgpu_encoder->encoder_id); in dce_v10_0_afmt_enable()
1780 for (i = 0; i < adev->mode_info.num_dig; i++) in dce_v10_0_afmt_init()
1781 adev->mode_info.afmt[i] = NULL; in dce_v10_0_afmt_init()
1784 for (i = 0; i < adev->mode_info.num_dig; i++) { in dce_v10_0_afmt_init()
1785 adev->mode_info.afmt[i] = kzalloc(sizeof(struct amdgpu_afmt), GFP_KERNEL); in dce_v10_0_afmt_init()
1786 if (adev->mode_info.afmt[i]) { in dce_v10_0_afmt_init()
1787 adev->mode_info.afmt[i]->offset = dig_offsets[i]; in dce_v10_0_afmt_init()
1788 adev->mode_info.afmt[i]->id = i; in dce_v10_0_afmt_init()
1792 kfree(adev->mode_info.afmt[j]); in dce_v10_0_afmt_init()
1793 adev->mode_info.afmt[j] = NULL; in dce_v10_0_afmt_init()
1795 return -ENOMEM; in dce_v10_0_afmt_init()
1805 for (i = 0; i < adev->mode_info.num_dig; i++) { in dce_v10_0_afmt_fini()
1806 kfree(adev->mode_info.afmt[i]); in dce_v10_0_afmt_fini()
1807 adev->mode_info.afmt[i] = NULL; in dce_v10_0_afmt_fini()
1824 struct drm_device *dev = crtc->dev; in dce_v10_0_vga_enable()
1828 vga_control = RREG32(vga_control_regs[amdgpu_crtc->crtc_id]) & ~1; in dce_v10_0_vga_enable()
1830 WREG32(vga_control_regs[amdgpu_crtc->crtc_id], vga_control | 1); in dce_v10_0_vga_enable()
1832 WREG32(vga_control_regs[amdgpu_crtc->crtc_id], vga_control); in dce_v10_0_vga_enable()
1838 struct drm_device *dev = crtc->dev; in dce_v10_0_grph_enable()
1842 WREG32(mmGRPH_ENABLE + amdgpu_crtc->crtc_offset, 1); in dce_v10_0_grph_enable()
1844 WREG32(mmGRPH_ENABLE + amdgpu_crtc->crtc_offset, 0); in dce_v10_0_grph_enable()
1852 struct drm_device *dev = crtc->dev; in dce_v10_0_crtc_do_set_base()
1866 /* no fb bound */ in dce_v10_0_crtc_do_set_base()
1867 if (!atomic && !crtc->primary->fb) { in dce_v10_0_crtc_do_set_base()
1868 DRM_DEBUG_KMS("No FB bound\n"); in dce_v10_0_crtc_do_set_base()
1875 target_fb = crtc->primary->fb; in dce_v10_0_crtc_do_set_base()
1880 obj = target_fb->obj[0]; in dce_v10_0_crtc_do_set_base()
1890 return -EINVAL; in dce_v10_0_crtc_do_set_base()
1900 switch (target_fb->format->format) { in dce_v10_0_crtc_do_set_base()
1957 /* Greater 8 bpc fb needs to bypass hw-lut to retain precision */ in dce_v10_0_crtc_do_set_base()
1968 /* Greater 8 bpc fb needs to bypass hw-lut to retain precision */ in dce_v10_0_crtc_do_set_base()
1984 drm_get_format_name(target_fb->format->format, &format_name)); in dce_v10_0_crtc_do_set_base()
1985 return -EINVAL; in dce_v10_0_crtc_do_set_base()
2021 tmp = RREG32(mmGRPH_FLIP_CONTROL + amdgpu_crtc->crtc_offset); in dce_v10_0_crtc_do_set_base()
2024 WREG32(mmGRPH_FLIP_CONTROL + amdgpu_crtc->crtc_offset, tmp); in dce_v10_0_crtc_do_set_base()
2026 WREG32(mmGRPH_PRIMARY_SURFACE_ADDRESS_HIGH + amdgpu_crtc->crtc_offset, in dce_v10_0_crtc_do_set_base()
2028 WREG32(mmGRPH_SECONDARY_SURFACE_ADDRESS_HIGH + amdgpu_crtc->crtc_offset, in dce_v10_0_crtc_do_set_base()
2030 WREG32(mmGRPH_PRIMARY_SURFACE_ADDRESS + amdgpu_crtc->crtc_offset, in dce_v10_0_crtc_do_set_base()
2032 WREG32(mmGRPH_SECONDARY_SURFACE_ADDRESS + amdgpu_crtc->crtc_offset, in dce_v10_0_crtc_do_set_base()
2034 WREG32(mmGRPH_CONTROL + amdgpu_crtc->crtc_offset, fb_format); in dce_v10_0_crtc_do_set_base()
2035 WREG32(mmGRPH_SWAP_CNTL + amdgpu_crtc->crtc_offset, fb_swap); in dce_v10_0_crtc_do_set_base()
2042 tmp = RREG32(mmGRPH_LUT_10BIT_BYPASS + amdgpu_crtc->crtc_offset); in dce_v10_0_crtc_do_set_base()
2047 WREG32(mmGRPH_LUT_10BIT_BYPASS + amdgpu_crtc->crtc_offset, tmp); in dce_v10_0_crtc_do_set_base()
2052 WREG32(mmGRPH_SURFACE_OFFSET_X + amdgpu_crtc->crtc_offset, 0); in dce_v10_0_crtc_do_set_base()
2053 WREG32(mmGRPH_SURFACE_OFFSET_Y + amdgpu_crtc->crtc_offset, 0); in dce_v10_0_crtc_do_set_base()
2054 WREG32(mmGRPH_X_START + amdgpu_crtc->crtc_offset, 0); in dce_v10_0_crtc_do_set_base()
2055 WREG32(mmGRPH_Y_START + amdgpu_crtc->crtc_offset, 0); in dce_v10_0_crtc_do_set_base()
2056 WREG32(mmGRPH_X_END + amdgpu_crtc->crtc_offset, target_fb->width); in dce_v10_0_crtc_do_set_base()
2057 WREG32(mmGRPH_Y_END + amdgpu_crtc->crtc_offset, target_fb->height); in dce_v10_0_crtc_do_set_base()
2059 fb_pitch_pixels = target_fb->pitches[0] / target_fb->format->cpp[0]; in dce_v10_0_crtc_do_set_base()
2060 WREG32(mmGRPH_PITCH + amdgpu_crtc->crtc_offset, fb_pitch_pixels); in dce_v10_0_crtc_do_set_base()
2064 WREG32(mmLB_DESKTOP_HEIGHT + amdgpu_crtc->crtc_offset, in dce_v10_0_crtc_do_set_base()
2065 target_fb->height); in dce_v10_0_crtc_do_set_base()
2069 WREG32(mmVIEWPORT_START + amdgpu_crtc->crtc_offset, in dce_v10_0_crtc_do_set_base()
2071 viewport_w = crtc->mode.hdisplay; in dce_v10_0_crtc_do_set_base()
2072 viewport_h = (crtc->mode.vdisplay + 1) & ~1; in dce_v10_0_crtc_do_set_base()
2073 WREG32(mmVIEWPORT_SIZE + amdgpu_crtc->crtc_offset, in dce_v10_0_crtc_do_set_base()
2077 WREG32(mmMASTER_UPDATE_MODE + amdgpu_crtc->crtc_offset, 0); in dce_v10_0_crtc_do_set_base()
2079 if (!atomic && fb && fb != crtc->primary->fb) { in dce_v10_0_crtc_do_set_base()
2080 abo = gem_to_amdgpu_bo(fb->obj[0]); in dce_v10_0_crtc_do_set_base()
2097 struct drm_device *dev = crtc->dev; in dce_v10_0_set_interleave()
2102 tmp = RREG32(mmLB_DATA_FORMAT + amdgpu_crtc->crtc_offset); in dce_v10_0_set_interleave()
2103 if (mode->flags & DRM_MODE_FLAG_INTERLACE) in dce_v10_0_set_interleave()
2107 WREG32(mmLB_DATA_FORMAT + amdgpu_crtc->crtc_offset, tmp); in dce_v10_0_set_interleave()
2113 struct drm_device *dev = crtc->dev; in dce_v10_0_crtc_load_lut()
2119 DRM_DEBUG_KMS("%d\n", amdgpu_crtc->crtc_id); in dce_v10_0_crtc_load_lut()
2121 tmp = RREG32(mmINPUT_CSC_CONTROL + amdgpu_crtc->crtc_offset); in dce_v10_0_crtc_load_lut()
2124 WREG32(mmINPUT_CSC_CONTROL + amdgpu_crtc->crtc_offset, tmp); in dce_v10_0_crtc_load_lut()
2126 tmp = RREG32(mmPRESCALE_GRPH_CONTROL + amdgpu_crtc->crtc_offset); in dce_v10_0_crtc_load_lut()
2128 WREG32(mmPRESCALE_GRPH_CONTROL + amdgpu_crtc->crtc_offset, tmp); in dce_v10_0_crtc_load_lut()
2130 tmp = RREG32(mmPRESCALE_OVL_CONTROL + amdgpu_crtc->crtc_offset); in dce_v10_0_crtc_load_lut()
2132 WREG32(mmPRESCALE_OVL_CONTROL + amdgpu_crtc->crtc_offset, tmp); in dce_v10_0_crtc_load_lut()
2134 tmp = RREG32(mmINPUT_GAMMA_CONTROL + amdgpu_crtc->crtc_offset); in dce_v10_0_crtc_load_lut()
2137 WREG32(mmINPUT_GAMMA_CONTROL + amdgpu_crtc->crtc_offset, tmp); in dce_v10_0_crtc_load_lut()
2139 WREG32(mmDC_LUT_CONTROL + amdgpu_crtc->crtc_offset, 0); in dce_v10_0_crtc_load_lut()
2141 WREG32(mmDC_LUT_BLACK_OFFSET_BLUE + amdgpu_crtc->crtc_offset, 0); in dce_v10_0_crtc_load_lut()
2142 WREG32(mmDC_LUT_BLACK_OFFSET_GREEN + amdgpu_crtc->crtc_offset, 0); in dce_v10_0_crtc_load_lut()
2143 WREG32(mmDC_LUT_BLACK_OFFSET_RED + amdgpu_crtc->crtc_offset, 0); in dce_v10_0_crtc_load_lut()
2145 WREG32(mmDC_LUT_WHITE_OFFSET_BLUE + amdgpu_crtc->crtc_offset, 0xffff); in dce_v10_0_crtc_load_lut()
2146 WREG32(mmDC_LUT_WHITE_OFFSET_GREEN + amdgpu_crtc->crtc_offset, 0xffff); in dce_v10_0_crtc_load_lut()
2147 WREG32(mmDC_LUT_WHITE_OFFSET_RED + amdgpu_crtc->crtc_offset, 0xffff); in dce_v10_0_crtc_load_lut()
2149 WREG32(mmDC_LUT_RW_MODE + amdgpu_crtc->crtc_offset, 0); in dce_v10_0_crtc_load_lut()
2150 WREG32(mmDC_LUT_WRITE_EN_MASK + amdgpu_crtc->crtc_offset, 0x00000007); in dce_v10_0_crtc_load_lut()
2152 WREG32(mmDC_LUT_RW_INDEX + amdgpu_crtc->crtc_offset, 0); in dce_v10_0_crtc_load_lut()
2153 r = crtc->gamma_store; in dce_v10_0_crtc_load_lut()
2154 g = r + crtc->gamma_size; in dce_v10_0_crtc_load_lut()
2155 b = g + crtc->gamma_size; in dce_v10_0_crtc_load_lut()
2157 WREG32(mmDC_LUT_30_COLOR + amdgpu_crtc->crtc_offset, in dce_v10_0_crtc_load_lut()
2163 tmp = RREG32(mmDEGAMMA_CONTROL + amdgpu_crtc->crtc_offset); in dce_v10_0_crtc_load_lut()
2167 WREG32(mmDEGAMMA_CONTROL + amdgpu_crtc->crtc_offset, tmp); in dce_v10_0_crtc_load_lut()
2169 tmp = RREG32(mmGAMUT_REMAP_CONTROL + amdgpu_crtc->crtc_offset); in dce_v10_0_crtc_load_lut()
2172 WREG32(mmGAMUT_REMAP_CONTROL + amdgpu_crtc->crtc_offset, tmp); in dce_v10_0_crtc_load_lut()
2174 tmp = RREG32(mmREGAMMA_CONTROL + amdgpu_crtc->crtc_offset); in dce_v10_0_crtc_load_lut()
2177 WREG32(mmREGAMMA_CONTROL + amdgpu_crtc->crtc_offset, tmp); in dce_v10_0_crtc_load_lut()
2179 tmp = RREG32(mmOUTPUT_CSC_CONTROL + amdgpu_crtc->crtc_offset); in dce_v10_0_crtc_load_lut()
2182 WREG32(mmOUTPUT_CSC_CONTROL + amdgpu_crtc->crtc_offset, tmp); in dce_v10_0_crtc_load_lut()
2185 WREG32(mmDENORM_CONTROL + amdgpu_crtc->crtc_offset, 0); in dce_v10_0_crtc_load_lut()
2189 tmp = RREG32(mmALPHA_CONTROL + amdgpu_crtc->crtc_offset); in dce_v10_0_crtc_load_lut()
2191 WREG32(mmALPHA_CONTROL + amdgpu_crtc->crtc_offset, tmp); in dce_v10_0_crtc_load_lut()
2197 struct amdgpu_encoder_atom_dig *dig = amdgpu_encoder->enc_priv; in dce_v10_0_pick_dig_encoder()
2199 switch (amdgpu_encoder->encoder_id) { in dce_v10_0_pick_dig_encoder()
2201 if (dig->linkb) in dce_v10_0_pick_dig_encoder()
2207 if (dig->linkb) in dce_v10_0_pick_dig_encoder()
2213 if (dig->linkb) in dce_v10_0_pick_dig_encoder()
2222 DRM_ERROR("invalid encoder_id: 0x%x\n", amdgpu_encoder->encoder_id); in dce_v10_0_pick_dig_encoder()
2228 * dce_v10_0_pick_pll - Allocate a PPLL for use by the crtc.
2233 * a single PPLL can be used for all DP crtcs/encoders. For non-DP
2236 * as there is no need to program the PLL itself. If we are not able to
2244 * - PPLL1, PPLL2 are available for all UNIPHY (both DP and non-DP)
2246 * - PPLL0, PPLL1, PPLL2 are available for all UNIPHY (both DP and non-DP) and DAC
2252 struct drm_device *dev = crtc->dev; in dce_v10_0_pick_pll()
2257 if (ENCODER_MODE_IS_DP(amdgpu_atombios_encoder_get_encoder_mode(amdgpu_crtc->encoder))) { in dce_v10_0_pick_pll()
2258 if (adev->clock.dp_extclk) in dce_v10_0_pick_pll()
2288 struct amdgpu_device *adev = drm_to_adev(crtc->dev); in dce_v10_0_lock_cursor()
2292 cur_lock = RREG32(mmCUR_UPDATE + amdgpu_crtc->crtc_offset); in dce_v10_0_lock_cursor()
2297 WREG32(mmCUR_UPDATE + amdgpu_crtc->crtc_offset, cur_lock); in dce_v10_0_lock_cursor()
2303 struct amdgpu_device *adev = drm_to_adev(crtc->dev); in dce_v10_0_hide_cursor()
2306 tmp = RREG32(mmCUR_CONTROL + amdgpu_crtc->crtc_offset); in dce_v10_0_hide_cursor()
2308 WREG32(mmCUR_CONTROL + amdgpu_crtc->crtc_offset, tmp); in dce_v10_0_hide_cursor()
2314 struct amdgpu_device *adev = drm_to_adev(crtc->dev); in dce_v10_0_show_cursor()
2317 WREG32(mmCUR_SURFACE_ADDRESS_HIGH + amdgpu_crtc->crtc_offset, in dce_v10_0_show_cursor()
2318 upper_32_bits(amdgpu_crtc->cursor_addr)); in dce_v10_0_show_cursor()
2319 WREG32(mmCUR_SURFACE_ADDRESS + amdgpu_crtc->crtc_offset, in dce_v10_0_show_cursor()
2320 lower_32_bits(amdgpu_crtc->cursor_addr)); in dce_v10_0_show_cursor()
2322 tmp = RREG32(mmCUR_CONTROL + amdgpu_crtc->crtc_offset); in dce_v10_0_show_cursor()
2325 WREG32(mmCUR_CONTROL + amdgpu_crtc->crtc_offset, tmp); in dce_v10_0_show_cursor()
2332 struct amdgpu_device *adev = drm_to_adev(crtc->dev); in dce_v10_0_cursor_move_locked()
2335 amdgpu_crtc->cursor_x = x; in dce_v10_0_cursor_move_locked()
2336 amdgpu_crtc->cursor_y = y; in dce_v10_0_cursor_move_locked()
2339 x += crtc->x; in dce_v10_0_cursor_move_locked()
2340 y += crtc->y; in dce_v10_0_cursor_move_locked()
2341 DRM_DEBUG("x %d y %d c->x %d c->y %d\n", x, y, crtc->x, crtc->y); in dce_v10_0_cursor_move_locked()
2344 xorigin = min(-x, amdgpu_crtc->max_cursor_width - 1); in dce_v10_0_cursor_move_locked()
2348 yorigin = min(-y, amdgpu_crtc->max_cursor_height - 1); in dce_v10_0_cursor_move_locked()
2352 WREG32(mmCUR_POSITION + amdgpu_crtc->crtc_offset, (x << 16) | y); in dce_v10_0_cursor_move_locked()
2353 WREG32(mmCUR_HOT_SPOT + amdgpu_crtc->crtc_offset, (xorigin << 16) | yorigin); in dce_v10_0_cursor_move_locked()
2354 WREG32(mmCUR_SIZE + amdgpu_crtc->crtc_offset, in dce_v10_0_cursor_move_locked()
2355 ((amdgpu_crtc->cursor_width - 1) << 16) | (amdgpu_crtc->cursor_height - 1)); in dce_v10_0_cursor_move_locked()
2392 if ((width > amdgpu_crtc->max_cursor_width) || in dce_v10_0_crtc_cursor_set2()
2393 (height > amdgpu_crtc->max_cursor_height)) { in dce_v10_0_crtc_cursor_set2()
2395 return -EINVAL; in dce_v10_0_crtc_cursor_set2()
2400 DRM_ERROR("Cannot find cursor object %x for crtc %d\n", handle, amdgpu_crtc->crtc_id); in dce_v10_0_crtc_cursor_set2()
2401 return -ENOENT; in dce_v10_0_crtc_cursor_set2()
2418 amdgpu_crtc->cursor_addr = amdgpu_bo_gpu_offset(aobj); in dce_v10_0_crtc_cursor_set2()
2422 if (width != amdgpu_crtc->cursor_width || in dce_v10_0_crtc_cursor_set2()
2423 height != amdgpu_crtc->cursor_height || in dce_v10_0_crtc_cursor_set2()
2424 hot_x != amdgpu_crtc->cursor_hot_x || in dce_v10_0_crtc_cursor_set2()
2425 hot_y != amdgpu_crtc->cursor_hot_y) { in dce_v10_0_crtc_cursor_set2()
2428 x = amdgpu_crtc->cursor_x + amdgpu_crtc->cursor_hot_x - hot_x; in dce_v10_0_crtc_cursor_set2()
2429 y = amdgpu_crtc->cursor_y + amdgpu_crtc->cursor_hot_y - hot_y; in dce_v10_0_crtc_cursor_set2()
2433 amdgpu_crtc->cursor_width = width; in dce_v10_0_crtc_cursor_set2()
2434 amdgpu_crtc->cursor_height = height; in dce_v10_0_crtc_cursor_set2()
2435 amdgpu_crtc->cursor_hot_x = hot_x; in dce_v10_0_crtc_cursor_set2()
2436 amdgpu_crtc->cursor_hot_y = hot_y; in dce_v10_0_crtc_cursor_set2()
2443 if (amdgpu_crtc->cursor_bo) { in dce_v10_0_crtc_cursor_set2()
2444 struct amdgpu_bo *aobj = gem_to_amdgpu_bo(amdgpu_crtc->cursor_bo); in dce_v10_0_crtc_cursor_set2()
2450 drm_gem_object_put(amdgpu_crtc->cursor_bo); in dce_v10_0_crtc_cursor_set2()
2453 amdgpu_crtc->cursor_bo = obj; in dce_v10_0_crtc_cursor_set2()
2461 if (amdgpu_crtc->cursor_bo) { in dce_v10_0_cursor_reset()
2464 dce_v10_0_cursor_move_locked(crtc, amdgpu_crtc->cursor_x, in dce_v10_0_cursor_reset()
2465 amdgpu_crtc->cursor_y); in dce_v10_0_cursor_reset()
2505 struct drm_device *dev = crtc->dev; in dce_v10_0_crtc_dpms()
2512 amdgpu_crtc->enabled = true; in dce_v10_0_crtc_dpms()
2519 amdgpu_crtc->crtc_id); in dce_v10_0_crtc_dpms()
2520 amdgpu_irq_update(adev, &adev->crtc_irq, type); in dce_v10_0_crtc_dpms()
2521 amdgpu_irq_update(adev, &adev->pageflip_irq, type); in dce_v10_0_crtc_dpms()
2529 if (amdgpu_crtc->enabled) { in dce_v10_0_crtc_dpms()
2535 amdgpu_crtc->enabled = false; in dce_v10_0_crtc_dpms()
2559 struct drm_device *dev = crtc->dev; in dce_v10_0_crtc_disable()
2565 if (crtc->primary->fb) { in dce_v10_0_crtc_disable()
2569 abo = gem_to_amdgpu_bo(crtc->primary->fb->obj[0]); in dce_v10_0_crtc_disable()
2583 for (i = 0; i < adev->mode_info.num_crtc; i++) { in dce_v10_0_crtc_disable()
2584 if (adev->mode_info.crtcs[i] && in dce_v10_0_crtc_disable()
2585 adev->mode_info.crtcs[i]->enabled && in dce_v10_0_crtc_disable()
2586 i != amdgpu_crtc->crtc_id && in dce_v10_0_crtc_disable()
2587 amdgpu_crtc->pll_id == adev->mode_info.crtcs[i]->pll_id) { in dce_v10_0_crtc_disable()
2595 switch (amdgpu_crtc->pll_id) { in dce_v10_0_crtc_disable()
2600 amdgpu_atombios_crtc_program_pll(crtc, amdgpu_crtc->crtc_id, amdgpu_crtc->pll_id, in dce_v10_0_crtc_disable()
2607 amdgpu_crtc->pll_id = ATOM_PPLL_INVALID; in dce_v10_0_crtc_disable()
2608 amdgpu_crtc->adjusted_clock = 0; in dce_v10_0_crtc_disable()
2609 amdgpu_crtc->encoder = NULL; in dce_v10_0_crtc_disable()
2610 amdgpu_crtc->connector = NULL; in dce_v10_0_crtc_disable()
2620 if (!amdgpu_crtc->adjusted_clock) in dce_v10_0_crtc_mode_set()
2621 return -EINVAL; in dce_v10_0_crtc_mode_set()
2630 amdgpu_crtc->hw_mode = *adjusted_mode; in dce_v10_0_crtc_mode_set()
2640 struct drm_device *dev = crtc->dev; in dce_v10_0_crtc_mode_fixup()
2644 list_for_each_entry(encoder, &dev->mode_config.encoder_list, head) { in dce_v10_0_crtc_mode_fixup()
2645 if (encoder->crtc == crtc) { in dce_v10_0_crtc_mode_fixup()
2646 amdgpu_crtc->encoder = encoder; in dce_v10_0_crtc_mode_fixup()
2647 amdgpu_crtc->connector = amdgpu_get_connector_for_encoder(encoder); in dce_v10_0_crtc_mode_fixup()
2651 if ((amdgpu_crtc->encoder == NULL) || (amdgpu_crtc->connector == NULL)) { in dce_v10_0_crtc_mode_fixup()
2652 amdgpu_crtc->encoder = NULL; in dce_v10_0_crtc_mode_fixup()
2653 amdgpu_crtc->connector = NULL; in dce_v10_0_crtc_mode_fixup()
2661 amdgpu_crtc->pll_id = dce_v10_0_pick_pll(crtc); in dce_v10_0_crtc_mode_fixup()
2662 /* if we can't get a PPLL for a non-DP encoder, fail */ in dce_v10_0_crtc_mode_fixup()
2663 if ((amdgpu_crtc->pll_id == ATOM_PPLL_INVALID) && in dce_v10_0_crtc_mode_fixup()
2664 !ENCODER_MODE_IS_DP(amdgpu_atombios_encoder_get_encoder_mode(amdgpu_crtc->encoder))) in dce_v10_0_crtc_mode_fixup()
2702 return -ENOMEM; in dce_v10_0_crtc_init()
2704 drm_crtc_init(adev_to_drm(adev), &amdgpu_crtc->base, &dce_v10_0_crtc_funcs); in dce_v10_0_crtc_init()
2706 drm_mode_crtc_set_gamma_size(&amdgpu_crtc->base, 256); in dce_v10_0_crtc_init()
2707 amdgpu_crtc->crtc_id = index; in dce_v10_0_crtc_init()
2708 adev->mode_info.crtcs[index] = amdgpu_crtc; in dce_v10_0_crtc_init()
2710 amdgpu_crtc->max_cursor_width = 128; in dce_v10_0_crtc_init()
2711 amdgpu_crtc->max_cursor_height = 128; in dce_v10_0_crtc_init()
2712 adev_to_drm(adev)->mode_config.cursor_width = amdgpu_crtc->max_cursor_width; in dce_v10_0_crtc_init()
2713 adev_to_drm(adev)->mode_config.cursor_height = amdgpu_crtc->max_cursor_height; in dce_v10_0_crtc_init()
2715 switch (amdgpu_crtc->crtc_id) { in dce_v10_0_crtc_init()
2718 amdgpu_crtc->crtc_offset = CRTC0_REGISTER_OFFSET; in dce_v10_0_crtc_init()
2721 amdgpu_crtc->crtc_offset = CRTC1_REGISTER_OFFSET; in dce_v10_0_crtc_init()
2724 amdgpu_crtc->crtc_offset = CRTC2_REGISTER_OFFSET; in dce_v10_0_crtc_init()
2727 amdgpu_crtc->crtc_offset = CRTC3_REGISTER_OFFSET; in dce_v10_0_crtc_init()
2730 amdgpu_crtc->crtc_offset = CRTC4_REGISTER_OFFSET; in dce_v10_0_crtc_init()
2733 amdgpu_crtc->crtc_offset = CRTC5_REGISTER_OFFSET; in dce_v10_0_crtc_init()
2737 amdgpu_crtc->pll_id = ATOM_PPLL_INVALID; in dce_v10_0_crtc_init()
2738 amdgpu_crtc->adjusted_clock = 0; in dce_v10_0_crtc_init()
2739 amdgpu_crtc->encoder = NULL; in dce_v10_0_crtc_init()
2740 amdgpu_crtc->connector = NULL; in dce_v10_0_crtc_init()
2741 drm_crtc_helper_add(&amdgpu_crtc->base, &dce_v10_0_crtc_helper_funcs); in dce_v10_0_crtc_init()
2750 adev->audio_endpt_rreg = &dce_v10_0_audio_endpt_rreg; in dce_v10_0_early_init()
2751 adev->audio_endpt_wreg = &dce_v10_0_audio_endpt_wreg; in dce_v10_0_early_init()
2755 adev->mode_info.num_crtc = dce_v10_0_get_num_crtc(adev); in dce_v10_0_early_init()
2757 switch (adev->asic_type) { in dce_v10_0_early_init()
2760 adev->mode_info.num_hpd = 6; in dce_v10_0_early_init()
2761 adev->mode_info.num_dig = 7; in dce_v10_0_early_init()
2765 return -EINVAL; in dce_v10_0_early_init()
2778 for (i = 0; i < adev->mode_info.num_crtc; i++) { in dce_v10_0_sw_init()
2779 r = amdgpu_irq_add_id(adev, AMDGPU_IRQ_CLIENTID_LEGACY, i + 1, &adev->crtc_irq); in dce_v10_0_sw_init()
2785 r = amdgpu_irq_add_id(adev, AMDGPU_IRQ_CLIENTID_LEGACY, i, &adev->pageflip_irq); in dce_v10_0_sw_init()
2790 /* HPD hotplug */ in dce_v10_0_sw_init()
2791 …irq_add_id(adev, AMDGPU_IRQ_CLIENTID_LEGACY, VISLANDS30_IV_SRCID_HOTPLUG_DETECT_A, &adev->hpd_irq); in dce_v10_0_sw_init()
2795 adev_to_drm(adev)->mode_config.funcs = &amdgpu_mode_funcs; in dce_v10_0_sw_init()
2797 adev_to_drm(adev)->mode_config.async_page_flip = true; in dce_v10_0_sw_init()
2799 adev_to_drm(adev)->mode_config.max_width = 16384; in dce_v10_0_sw_init()
2800 adev_to_drm(adev)->mode_config.max_height = 16384; in dce_v10_0_sw_init()
2802 adev_to_drm(adev)->mode_config.preferred_depth = 24; in dce_v10_0_sw_init()
2803 adev_to_drm(adev)->mode_config.prefer_shadow = 1; in dce_v10_0_sw_init()
2805 adev_to_drm(adev)->mode_config.fb_base = adev->gmc.aper_base; in dce_v10_0_sw_init()
2811 adev_to_drm(adev)->mode_config.max_width = 16384; in dce_v10_0_sw_init()
2812 adev_to_drm(adev)->mode_config.max_height = 16384; in dce_v10_0_sw_init()
2815 for (i = 0; i < adev->mode_info.num_crtc; i++) { in dce_v10_0_sw_init()
2824 return -EINVAL; in dce_v10_0_sw_init()
2837 adev->mode_info.mode_config_initialized = true; in dce_v10_0_sw_init()
2845 kfree(adev->mode_info.bios_hardcoded_edid); in dce_v10_0_sw_fini()
2854 adev->mode_info.mode_config_initialized = false; in dce_v10_0_sw_fini()
2870 amdgpu_atombios_crtc_set_disp_eng_pll(adev, adev->clock.default_dispclk); in dce_v10_0_hw_init()
2872 /* initialize hpd */ in dce_v10_0_hw_init()
2875 for (i = 0; i < adev->mode_info.audio.num_pins; i++) { in dce_v10_0_hw_init()
2876 dce_v10_0_audio_enable(adev, &adev->mode_info.audio.pin[i], false); in dce_v10_0_hw_init()
2891 for (i = 0; i < adev->mode_info.audio.num_pins; i++) { in dce_v10_0_hw_fini()
2892 dce_v10_0_audio_enable(adev, &adev->mode_info.audio.pin[i], false); in dce_v10_0_hw_fini()
2904 adev->mode_info.bl_level = in dce_v10_0_suspend()
2916 adev->mode_info.bl_level); in dce_v10_0_resume()
2921 if (adev->mode_info.bl_encoder) { in dce_v10_0_resume()
2923 adev->mode_info.bl_encoder); in dce_v10_0_resume()
2924 amdgpu_display_backlight_set_level(adev, adev->mode_info.bl_encoder, in dce_v10_0_resume()
2959 dev_info(adev->dev, "SRBM_SOFT_RESET=0x%08X\n", tmp); in dce_v10_0_soft_reset()
2981 if (crtc >= adev->mode_info.num_crtc) { in dce_v10_0_set_crtc_vblank_interrupt_state()
3010 if (crtc >= adev->mode_info.num_crtc) { in dce_v10_0_set_crtc_vline_interrupt_state()
3035 unsigned hpd, in dce_v10_0_set_hpd_irq_state() argument
3040 if (hpd >= adev->mode_info.num_hpd) { in dce_v10_0_set_hpd_irq_state()
3041 DRM_DEBUG("invalid hdp %d\n", hpd); in dce_v10_0_set_hpd_irq_state()
3047 tmp = RREG32(mmDC_HPD_INT_CONTROL + hpd_offsets[hpd]); in dce_v10_0_set_hpd_irq_state()
3049 WREG32(mmDC_HPD_INT_CONTROL + hpd_offsets[hpd], tmp); in dce_v10_0_set_hpd_irq_state()
3052 tmp = RREG32(mmDC_HPD_INT_CONTROL + hpd_offsets[hpd]); in dce_v10_0_set_hpd_irq_state()
3054 WREG32(mmDC_HPD_INT_CONTROL + hpd_offsets[hpd], tmp); in dce_v10_0_set_hpd_irq_state()
3118 if (type >= adev->mode_info.num_crtc) { in dce_v10_0_set_pageflip_irq_state()
3120 return -EINVAL; in dce_v10_0_set_pageflip_irq_state()
3143 crtc_id = (entry->src_id - 8) >> 1; in dce_v10_0_pageflip_irq()
3144 amdgpu_crtc = adev->mode_info.crtcs[crtc_id]; in dce_v10_0_pageflip_irq()
3146 if (crtc_id >= adev->mode_info.num_crtc) { in dce_v10_0_pageflip_irq()
3148 return -EINVAL; in dce_v10_0_pageflip_irq()
3160 spin_lock_irqsave(&adev_to_drm(adev)->event_lock, flags); in dce_v10_0_pageflip_irq()
3161 works = amdgpu_crtc->pflip_works; in dce_v10_0_pageflip_irq()
3162 if (amdgpu_crtc->pflip_status != AMDGPU_FLIP_SUBMITTED) { in dce_v10_0_pageflip_irq()
3163 DRM_DEBUG_DRIVER("amdgpu_crtc->pflip_status = %d != " in dce_v10_0_pageflip_irq()
3165 amdgpu_crtc->pflip_status, in dce_v10_0_pageflip_irq()
3167 spin_unlock_irqrestore(&adev_to_drm(adev)->event_lock, flags); in dce_v10_0_pageflip_irq()
3172 amdgpu_crtc->pflip_status = AMDGPU_FLIP_NONE; in dce_v10_0_pageflip_irq()
3173 amdgpu_crtc->pflip_works = NULL; in dce_v10_0_pageflip_irq()
3176 if (works->event) in dce_v10_0_pageflip_irq()
3177 drm_crtc_send_vblank_event(&amdgpu_crtc->base, works->event); in dce_v10_0_pageflip_irq()
3179 spin_unlock_irqrestore(&adev_to_drm(adev)->event_lock, flags); in dce_v10_0_pageflip_irq()
3181 drm_crtc_vblank_put(&amdgpu_crtc->base); in dce_v10_0_pageflip_irq()
3182 schedule_work(&works->unpin_work); in dce_v10_0_pageflip_irq()
3188 int hpd) in dce_v10_0_hpd_int_ack() argument
3192 if (hpd >= adev->mode_info.num_hpd) { in dce_v10_0_hpd_int_ack()
3193 DRM_DEBUG("invalid hdp %d\n", hpd); in dce_v10_0_hpd_int_ack()
3197 tmp = RREG32(mmDC_HPD_INT_CONTROL + hpd_offsets[hpd]); in dce_v10_0_hpd_int_ack()
3199 WREG32(mmDC_HPD_INT_CONTROL + hpd_offsets[hpd], tmp); in dce_v10_0_hpd_int_ack()
3207 if (crtc >= adev->mode_info.num_crtc) { in dce_v10_0_crtc_vblank_int_ack()
3222 if (crtc >= adev->mode_info.num_crtc) { in dce_v10_0_crtc_vline_int_ack()
3236 unsigned crtc = entry->src_id - 1; in dce_v10_0_crtc_irq()
3240 switch (entry->src_data[0]) { in dce_v10_0_crtc_irq()
3263 DRM_DEBUG("Unhandled interrupt: %d %d\n", entry->src_id, entry->src_data[0]); in dce_v10_0_crtc_irq()
3275 unsigned hpd; in dce_v10_0_hpd_irq() local
3277 if (entry->src_data[0] >= adev->mode_info.num_hpd) { in dce_v10_0_hpd_irq()
3278 DRM_DEBUG("Unhandled interrupt: %d %d\n", entry->src_id, entry->src_data[0]); in dce_v10_0_hpd_irq()
3282 hpd = entry->src_data[0]; in dce_v10_0_hpd_irq()
3283 disp_int = RREG32(interrupt_status_offsets[hpd].reg); in dce_v10_0_hpd_irq()
3284 mask = interrupt_status_offsets[hpd].hpd; in dce_v10_0_hpd_irq()
3287 dce_v10_0_hpd_int_ack(adev, hpd); in dce_v10_0_hpd_irq()
3288 schedule_work(&adev->hotplug_work); in dce_v10_0_hpd_irq()
3289 DRM_DEBUG("IH: HPD%d\n", hpd + 1); in dce_v10_0_hpd_irq()
3332 amdgpu_encoder->pixel_clock = adjusted_mode->clock; in dce_v10_0_encoder_mode_set()
3338 dce_v10_0_set_interleave(encoder->crtc, mode); in dce_v10_0_encoder_mode_set()
3348 struct amdgpu_device *adev = drm_to_adev(encoder->dev); in dce_v10_0_encoder_prepare()
3352 if ((amdgpu_encoder->active_device & in dce_v10_0_encoder_prepare()
3356 struct amdgpu_encoder_atom_dig *dig = amdgpu_encoder->enc_priv; in dce_v10_0_encoder_prepare()
3358 dig->dig_encoder = dce_v10_0_pick_dig_encoder(encoder); in dce_v10_0_encoder_prepare()
3359 if (amdgpu_encoder->active_device & ATOM_DEVICE_DFP_SUPPORT) in dce_v10_0_encoder_prepare()
3360 dig->afmt = adev->mode_info.afmt[dig->dig_encoder]; in dce_v10_0_encoder_prepare()
3370 if (amdgpu_connector->router.cd_valid) in dce_v10_0_encoder_prepare()
3374 if (connector->connector_type == DRM_MODE_CONNECTOR_eDP) in dce_v10_0_encoder_prepare()
3387 struct drm_device *dev = encoder->dev; in dce_v10_0_encoder_commit()
3405 dig = amdgpu_encoder->enc_priv; in dce_v10_0_encoder_disable()
3406 dig->dig_encoder = -1; in dce_v10_0_encoder_disable()
3408 amdgpu_encoder->active_device = 0; in dce_v10_0_encoder_disable()
3447 /* no detect for TMDS/LVDS yet */
3472 if (amdgpu_encoder->devices & (ATOM_DEVICE_LCD_SUPPORT)) in dce_v10_0_encoder_destroy()
3474 kfree(amdgpu_encoder->enc_priv); in dce_v10_0_encoder_destroy()
3493 list_for_each_entry(encoder, &dev->mode_config.encoder_list, head) { in dce_v10_0_encoder_add()
3495 if (amdgpu_encoder->encoder_enum == encoder_enum) { in dce_v10_0_encoder_add()
3496 amdgpu_encoder->devices |= supported_device; in dce_v10_0_encoder_add()
3507 encoder = &amdgpu_encoder->base; in dce_v10_0_encoder_add()
3508 switch (adev->mode_info.num_crtc) { in dce_v10_0_encoder_add()
3510 encoder->possible_crtcs = 0x1; in dce_v10_0_encoder_add()
3514 encoder->possible_crtcs = 0x3; in dce_v10_0_encoder_add()
3517 encoder->possible_crtcs = 0xf; in dce_v10_0_encoder_add()
3520 encoder->possible_crtcs = 0x3f; in dce_v10_0_encoder_add()
3524 amdgpu_encoder->enc_priv = NULL; in dce_v10_0_encoder_add()
3526 amdgpu_encoder->encoder_enum = encoder_enum; in dce_v10_0_encoder_add()
3527 amdgpu_encoder->encoder_id = (encoder_enum & OBJECT_ID_MASK) >> OBJECT_ID_SHIFT; in dce_v10_0_encoder_add()
3528 amdgpu_encoder->devices = supported_device; in dce_v10_0_encoder_add()
3529 amdgpu_encoder->rmx_type = RMX_OFF; in dce_v10_0_encoder_add()
3530 amdgpu_encoder->underscan_type = UNDERSCAN_OFF; in dce_v10_0_encoder_add()
3531 amdgpu_encoder->is_ext_encoder = false; in dce_v10_0_encoder_add()
3532 amdgpu_encoder->caps = caps; in dce_v10_0_encoder_add()
3534 switch (amdgpu_encoder->encoder_id) { in dce_v10_0_encoder_add()
3546 if (amdgpu_encoder->devices & (ATOM_DEVICE_LCD_SUPPORT)) { in dce_v10_0_encoder_add()
3547 amdgpu_encoder->rmx_type = RMX_FULL; in dce_v10_0_encoder_add()
3550 amdgpu_encoder->enc_priv = amdgpu_atombios_encoder_get_lcd_info(amdgpu_encoder); in dce_v10_0_encoder_add()
3551 } else if (amdgpu_encoder->devices & (ATOM_DEVICE_CRT_SUPPORT)) { in dce_v10_0_encoder_add()
3554 amdgpu_encoder->enc_priv = amdgpu_atombios_encoder_get_dig_info(amdgpu_encoder); in dce_v10_0_encoder_add()
3558 amdgpu_encoder->enc_priv = amdgpu_atombios_encoder_get_dig_info(amdgpu_encoder); in dce_v10_0_encoder_add()
3572 amdgpu_encoder->is_ext_encoder = true; in dce_v10_0_encoder_add()
3573 if (amdgpu_encoder->devices & (ATOM_DEVICE_LCD_SUPPORT)) in dce_v10_0_encoder_add()
3576 else if (amdgpu_encoder->devices & (ATOM_DEVICE_CRT_SUPPORT)) in dce_v10_0_encoder_add()
3603 adev->mode_info.funcs = &dce_v10_0_display_funcs; in dce_v10_0_set_display_funcs()
3623 if (adev->mode_info.num_crtc > 0) in dce_v10_0_set_irq_funcs()
3624 adev->crtc_irq.num_types = AMDGPU_CRTC_IRQ_VLINE1 + adev->mode_info.num_crtc; in dce_v10_0_set_irq_funcs()
3626 adev->crtc_irq.num_types = 0; in dce_v10_0_set_irq_funcs()
3627 adev->crtc_irq.funcs = &dce_v10_0_crtc_irq_funcs; in dce_v10_0_set_irq_funcs()
3629 adev->pageflip_irq.num_types = adev->mode_info.num_crtc; in dce_v10_0_set_irq_funcs()
3630 adev->pageflip_irq.funcs = &dce_v10_0_pageflip_irq_funcs; in dce_v10_0_set_irq_funcs()
3632 adev->hpd_irq.num_types = adev->mode_info.num_hpd; in dce_v10_0_set_irq_funcs()
3633 adev->hpd_irq.funcs = &dce_v10_0_hpd_irq_funcs; in dce_v10_0_set_irq_funcs()