88 	uint32_t        hpd;  member
94 	.hpd = DISP_INTERRUPT_STATUS__DC_HPD1_INTERRUPT_MASK
99 	.hpd = DISP_INTERRUPT_STATUS_CONTINUE__DC_HPD2_INTERRUPT_MASK
104 	.hpd = DISP_INTERRUPT_STATUS_CONTINUE2__DC_HPD3_INTERRUPT_MASK
109 	.hpd = DISP_INTERRUPT_STATUS_CONTINUE3__DC_HPD4_INTERRUPT_MASK
114 	.hpd = DISP_INTERRUPT_STATUS_CONTINUE4__DC_HPD5_INTERRUPT_MASK
119 	.hpd = DISP_INTERRUPT_STATUS_CONTINUE5__DC_HPD6_INTERRUPT_MASK
273  * dce_v10_0_hpd_sense - hpd sense callback.
276  * @hpd: hpd (hotplug detect) pin
282 			       enum amdgpu_hpd_id hpd)  in dce_v10_0_hpd_sense()  argument
286 	if (hpd >= adev->mode_info.num_hpd)  in dce_v10_0_hpd_sense()
289 	if (RREG32(mmDC_HPD_INT_STATUS + hpd_offsets[hpd]) &  in dce_v10_0_hpd_sense()
297  * dce_v10_0_hpd_set_polarity - hpd set polarity callback.
300  * @hpd: hpd (hotplug detect) pin
302  * Set the polarity of the hpd pin (evergreen+).
305 				      enum amdgpu_hpd_id hpd)  in dce_v10_0_hpd_set_polarity()  argument
308 	bool connected = dce_v10_0_hpd_sense(adev, hpd);  in dce_v10_0_hpd_set_polarity()
310 	if (hpd >= adev->mode_info.num_hpd)  in dce_v10_0_hpd_set_polarity()
313 	tmp = RREG32(mmDC_HPD_INT_CONTROL + hpd_offsets[hpd]);  in dce_v10_0_hpd_set_polarity()
318 	WREG32(mmDC_HPD_INT_CONTROL + hpd_offsets[hpd], tmp);  in dce_v10_0_hpd_set_polarity()
322  * dce_v10_0_hpd_init - hpd setup callback.
326  * Setup the hpd pins used by the card (evergreen+).
327  * Enable the pin, set the polarity, and enable the hpd interrupts.
340 		if (amdgpu_connector->hpd.hpd >= adev->mode_info.num_hpd)  in dce_v10_0_hpd_init()
345 			/* don't try to enable hpd on eDP or LVDS avoid breaking the  in dce_v10_0_hpd_init()
350 			tmp = RREG32(mmDC_HPD_INT_CONTROL + hpd_offsets[amdgpu_connector->hpd.hpd]);  in dce_v10_0_hpd_init()
352 			WREG32(mmDC_HPD_INT_CONTROL + hpd_offsets[amdgpu_connector->hpd.hpd], tmp);  in dce_v10_0_hpd_init()
356 		tmp = RREG32(mmDC_HPD_CONTROL + hpd_offsets[amdgpu_connector->hpd.hpd]);  in dce_v10_0_hpd_init()
358 		WREG32(mmDC_HPD_CONTROL + hpd_offsets[amdgpu_connector->hpd.hpd], tmp);  in dce_v10_0_hpd_init()
360 		tmp = RREG32(mmDC_HPD_TOGGLE_FILT_CNTL + hpd_offsets[amdgpu_connector->hpd.hpd]);  in dce_v10_0_hpd_init()
367 		WREG32(mmDC_HPD_TOGGLE_FILT_CNTL + hpd_offsets[amdgpu_connector->hpd.hpd], tmp);  in dce_v10_0_hpd_init()
369 		dce_v10_0_hpd_set_polarity(adev, amdgpu_connector->hpd.hpd);  in dce_v10_0_hpd_init()
371 			       amdgpu_connector->hpd.hpd);  in dce_v10_0_hpd_init()
377  * dce_v10_0_hpd_fini - hpd tear down callback.
381  * Tear down the hpd pins used by the card (evergreen+).
382  * Disable the hpd interrupts.
395 		if (amdgpu_connector->hpd.hpd >= adev->mode_info.num_hpd)  in dce_v10_0_hpd_fini()
398 		tmp = RREG32(mmDC_HPD_CONTROL + hpd_offsets[amdgpu_connector->hpd.hpd]);  in dce_v10_0_hpd_fini()
400 		WREG32(mmDC_HPD_CONTROL + hpd_offsets[amdgpu_connector->hpd.hpd], tmp);  in dce_v10_0_hpd_fini()
403 			       amdgpu_connector->hpd.hpd);  in dce_v10_0_hpd_fini()
2790 	/* HPD hotplug */  in dce_v10_0_sw_init()
2872 	/* initialize hpd */  in dce_v10_0_hw_init()
3035 				       unsigned hpd,  in dce_v10_0_set_hpd_irq_state()  argument
3040 	if (hpd >= adev->mode_info.num_hpd) {  in dce_v10_0_set_hpd_irq_state()
3041 		DRM_DEBUG("invalid hdp %d\n", hpd);  in dce_v10_0_set_hpd_irq_state()
3047 		tmp = RREG32(mmDC_HPD_INT_CONTROL + hpd_offsets[hpd]);  in dce_v10_0_set_hpd_irq_state()
3049 		WREG32(mmDC_HPD_INT_CONTROL + hpd_offsets[hpd], tmp);  in dce_v10_0_set_hpd_irq_state()
3052 		tmp = RREG32(mmDC_HPD_INT_CONTROL + hpd_offsets[hpd]);  in dce_v10_0_set_hpd_irq_state()
3054 		WREG32(mmDC_HPD_INT_CONTROL + hpd_offsets[hpd], tmp);  in dce_v10_0_set_hpd_irq_state()
3188 				  int hpd)  in dce_v10_0_hpd_int_ack()  argument
3192 	if (hpd >= adev->mode_info.num_hpd) {  in dce_v10_0_hpd_int_ack()
3193 		DRM_DEBUG("invalid hdp %d\n", hpd);  in dce_v10_0_hpd_int_ack()
3197 	tmp = RREG32(mmDC_HPD_INT_CONTROL + hpd_offsets[hpd]);  in dce_v10_0_hpd_int_ack()
3199 	WREG32(mmDC_HPD_INT_CONTROL + hpd_offsets[hpd], tmp);  in dce_v10_0_hpd_int_ack()
3275 	unsigned hpd;  in dce_v10_0_hpd_irq()  local
3282 	hpd = entry->src_data[0];  in dce_v10_0_hpd_irq()
3283 	disp_int = RREG32(interrupt_status_offsets[hpd].reg);  in dce_v10_0_hpd_irq()
3284 	mask = interrupt_status_offsets[hpd].hpd;  in dce_v10_0_hpd_irq()
3287 		dce_v10_0_hpd_int_ack(adev, hpd);  in dce_v10_0_hpd_irq()
3289 		DRM_DEBUG("IH: HPD%d\n", hpd + 1);  in dce_v10_0_hpd_irq()