Lines Matching +full:0 +full:x0000000b
36 #define AMDGPU_VCN_HARVEST_VCN0 (1 << 0)
39 #define VCN_DEC_KMD_CMD 0x80000000
40 #define VCN_DEC_CMD_FENCE 0x00000000
41 #define VCN_DEC_CMD_TRAP 0x00000001
42 #define VCN_DEC_CMD_WRITE_REG 0x00000004
43 #define VCN_DEC_CMD_REG_READ_COND_WAIT 0x00000006
44 #define VCN_DEC_CMD_PACKET_START 0x0000000a
45 #define VCN_DEC_CMD_PACKET_END 0x0000000b
47 #define VCN_ENC_CMD_NO_OP 0x00000000
48 #define VCN_ENC_CMD_END 0x00000001
49 #define VCN_ENC_CMD_IB 0x00000002
50 #define VCN_ENC_CMD_FENCE 0x00000003
51 #define VCN_ENC_CMD_TRAP 0x00000004
52 #define VCN_ENC_CMD_REG_WRITE 0x0000000b
53 #define VCN_ENC_CMD_REG_WAIT 0x0000000c
55 #define VCN_VID_SOC_ADDRESS_2_0 0x1fa00
56 #define VCN1_VID_SOC_ADDRESS_3_0 0x48200
57 #define VCN_AON_SOC_ADDRESS_2_0 0x1f800
58 #define VCN1_AON_SOC_ADDRESS_3_0 0x48000
59 #define VCN_VID_IP_ADDRESS_2_0 0x0
60 #define VCN_AON_IP_ADDRESS_2_0 0x30000
62 #define mmUVD_RBC_XX_IB_REG_CHECK 0x026b
64 #define mmUVD_REG_XX_MASK 0x026c
89 } while (0)
98 video_range = ((((0xFFFFF & addr) >= (VCN_VID_SOC_ADDRESS_2_0)) && \
99 ((0xFFFFF & addr) < ((VCN_VID_SOC_ADDRESS_2_0 + 0x2600))))); \
100 video1_range = ((((0xFFFFF & addr) >= (VCN1_VID_SOC_ADDRESS_3_0)) && \
101 ((0xFFFFF & addr) < ((VCN1_VID_SOC_ADDRESS_3_0 + 0x2600))))); \
102 aon_range = ((((0xFFFFF & addr) >= (VCN_AON_SOC_ADDRESS_2_0)) && \
103 ((0xFFFFF & addr) < ((VCN_AON_SOC_ADDRESS_2_0 + 0x600))))); \
104 aon1_range = ((((0xFFFFF & addr) >= (VCN1_AON_SOC_ADDRESS_3_0)) && \
105 ((0xFFFFF & addr) < ((VCN1_AON_SOC_ADDRESS_3_0 + 0x600))))); \
107 internal_reg_offset = ((0xFFFFF & addr) - (VCN_VID_SOC_ADDRESS_2_0) + \
110 internal_reg_offset = ((0xFFFFF & addr) - (VCN_AON_SOC_ADDRESS_2_0) + \
113 internal_reg_offset = ((0xFFFFF & addr) - (VCN1_VID_SOC_ADDRESS_3_0) + \
116 internal_reg_offset = ((0xFFFFF & addr) - (VCN1_AON_SOC_ADDRESS_3_0) + \
119 internal_reg_offset = (0xFFFFF & addr); \
127 (0x0 << UVD_DPG_LMA_CTL__READ_WRITE__SHIFT | \
138 (0x1 << UVD_DPG_LMA_CTL__READ_WRITE__SHIFT | \
145 } while (0)
155 UVD_PGFSM_STATUS__UVDM_UVDU_PWR_ON = 0x2AAAA0,
156 UVD_PGFSM_STATUS__UVDM_UVDU_PWR_ON_2_0 = 0xAAAA0,
157 UVD_PGFSM_STATUS__UVDM_UVDU_UVDLM_PWR_ON_3_0 = 0x2A2A8AA0,
158 UVD_PGFSM_CONFIG__UVDM_UVDU_PWR_ON = 0x00000002,
159 UVD_STATUS__UVD_BUSY = 0x00000004,
160 GB_ADDR_CONFIG_DEFAULT = 0x26010011,
161 UVD_STATUS__IDLE = 0x2,
162 UVD_STATUS__BUSY = 0x5,
163 UVD_POWER_STATUS__UVD_POWER_STATUS_TILES_OFF = 0x1,
164 UVD_STATUS__RBC_BUSY = 0x1,
165 UVD_PGFSM_STATUS_UVDJ_PWR_ON = 0,
169 VCN_DPG_STATE__UNPAUSE = 0,